JPS63229938A - Communication control system - Google Patents

Abstract

PURPOSE:To reduce required transmission time by sending signal other than a transmission request signal not through a comparator circuit comparing the priority code. CONSTITUTION:A comparator circuit 40 is provided, which sends a received signal while giving nearly one bit of time delay thereto, compares the received priority code with its own priority code and sends its own priority code in place of the received priority code when its own priority is higher in the priority than the received priority code. Then the transmission right request signal is sent to other transmission line through the comparator circuit 40 and the signals other than the transmission right request signal are sent to the other transmission line not through the comparator circuit 40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication control method used in a data transmission system that is composed of a plurality of communication devices connected in a loop.

[Conventional technology]

LAN (Local Ar@a Network)
, and various on-premises control equipment, etc., as proposed in Japanese Patent Application No. 59-260800 filed separately by the present applicant, a transmission path between multiple communication devices for transmitting and receiving data is proposed. After connecting as a cylindrical loop,
The transmission direction of the data signal is determined, and when one of the communication devices acquires the transmission right and is transmitting, the other communication device relays the signal received from one transmission path and transmits it to the other transmission path. When acquiring a new transmission right in response to the end of transmission, the communication device requesting the transmission right sends a transmission right request signal, generally called a token (Tok@n), to the priority of the transmission right. A code indicating a message is added and transmitted, and each communication device with a high priority acquires the transmission right.

However, conventionally, in order to ensure transmission right handover, each communication device determines whether to relay and transmit the received signal or whether it should itself receive the signal, and when receiving the transmission right request signal, the communication device The decision as to whether to acquire the transmission right or to relay the transmission without acquiring it is made after all signals have been received.If the relay transmission is necessary, the time required to make the decision is determined for each communication device. This results in an increase in the delay time due to the decision, especially in the transmission of the transmission right request signal.

As a countermeasure against this, the received signal is transmitted with a time delay of approximately 1 bit, and the received priority code is compared with the own priority code, and if the own priority code is high, the received priority code is A circuit is provided to transmit its own priority code instead of the code, and the delay time required for relaying is #? i″1
A method of reducing the number of bits has been proposed, and details thereof are disclosed in Japanese Patent Application No. 132626/1983 filed separately by the present applicant.

[Problem that the invention seeks to solve]

However, in the case of the method disclosed in Japanese Patent Application No. 761-132626, a delay of about 1 bit is always given to the relay transmission of the received signal, and each communication device connected in a loop has a delay of about 1 bit. Therefore, as the number of communication devices increases, a problem arises in that it becomes impossible to further reduce the time required for transmission.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, in the above-mentioned method of adding a transmission right priority code to the transmission right request signal and transmitting it, the received signal is transmitted with a time delay of 19:1 bits, and the received priority code and its own A comparison circuit is provided that compares the priority code with the priority code and transmits the priority code of the other party in place of the received priority code when the priority code of the other party is high. It is assumed that signals other than the transmission right request signal are transmitted to the other transmission path without going through the comparison circuit.

[Effect]

Therefore, the comparison circuit compares the priority codes only for the transmission right request signal, and other signals are transmitted without going through the comparison circuit, and there is a delay of about 1 bit. This greatly reduces overall transmission time.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 2 is a block diagram showing the entire configuration, in which a plurality of communication devices (hereinafter referred to as STA), CA person ~ CED are transmission paths 2, ~
In this example, signals are transmitted in the direction indicated by the arrow. For example, STA-CEA acquires the transmission right and STA-CEA
When transmitting to TA working CED, STA @
cEa and CEc each relay and transmit the received signals.

FIG. 3 is a block diagram showing the details of each of the 8TA-CEs. An interface (hereinafter referred to as INF) 1b is provided for the main device 1a of the STA/CE, and one side is connected to the receiving power RI. The transmission line 2R is connected, and a switch SW is inserted between the transmission line 2R and the other transmission line 2S, which normally connects the transmission line 2R and 28. However, the transmission line 2S is connected to the transmission output SO of the I/F 1b in response to the control signal Sot from the I/F'1b.

In addition, a switch S is also provided between the transmission output SO and the switch SW.
W is provided, and the transmission line 2R and the switch SW2 are operated according to the control signal sat+Sc.

A D-type flip-flop circuit (hereinafter referred to as FFC) 11 is interposed as a delay element between the transmission line 2S via SW, and is synchronized with the received signal sR applied from I/F''1b to its clock terminal CK. According to the clock pulse CLK, the received signal sR applied to the data terminal is held sequentially and sent out from the output Q. This gives the received signal a delay of 1 bit (#1) and transmits it. Road 2
It is to be transmitted to S as a transmission signal Ss.

However, when the I/F1b generates only the control signal 81, the switch SW responds and connects the transmission line 2S to the transmission output SO of the I/Fib, so the signal from the I/Flb is directly connected to the transmission line 2S. It becomes what is sent.

FIG. 4 is a block diagram showing the specific configuration of the main device 1a, I/F 1b, and FFCII.
RAM) 22 Fixed memory (ROM) 23
, a bus controller (hereinafter referred to as BCT) 24, a serial/parallel converter such as a shift register (hereinafter referred to as spc) 31,
n hit deletion circuit (hereinafter referred to as ZEL) 32, CRC (C
ycltc Redundancy Cheek) detection circuit (hereinafter referred to as CHD) 33, Abort (Abor
t, ) ++ Idle detection circuit (hereinafter referred to as AAD) 3
4. CRC signal generation circuit (hereinafter referred to as "CRG") 35.
Abort signal generation circuit (hereinafter referred to as AsG) 36, parallel-to-serial converter such as shift register (hereinafter referred to as PSC) 37, “O
In addition, a switch SW2 shown in Fig. 3 is inserted between the PSC 37 and ZIS 38, and in the transmission mode, the switch SW2 is inserted. ZIS the output of PSC37
38 input directly.

Further, the received signal sR from the transmission path 2R is ZEI.

32, according to the HDLC order of JISC6363 etc., the ``'O'' bit is deleted, the 5PC31 converts it into parallel data, and the data is sent to the CPU 21 via the bus 39.
It executes the command in M23, makes judgments on received data and control decisions while accessing predetermined data in the RAM 22, and sends CRG35.M23 as necessary for transmission. ASG36
PSC37 controls parallel data transmission data.
and by sending the control signal Scl to the switch SW.
1 and set the transmission mode.

Then, the transmission data is converted into serial data in the PSC 37, a CRC signal from the CRG 35 is inserted, and the data is sent to the ZIS 38 via the switch SW2.
In IS3B, the υ* Os bit is inserted according to the HDLC procedure described above, and if necessary, an abort signal from the ASG 36 is inserted, and then the signal is sent to the transmission path 2S as a transmission signal Ss. Ru.

Note that the received signal sR is also given to the AAD34,
While the CPU 21 performs predetermined control according to the detection output of this and the output indicating the check result of the CRD 33, depending on the conditions, the DMA (Dir@ctMemory
Access, ) control causes the received data from the 98PC 31 to be directly stored in the RAM 22 via the BCT 24, or the contents of the RAM 22 to be sent directly to the PSC 37.

In addition, the output of ZEL32 is a comparator circuit (hereinafter referred to as cpC)
40 and given to the data terminal of 9FFC11,
The output Q of this is AND gate 41. It is applied to the input of the ZIS 38 via the OR gate 42 and the switch SW, and when performing the comparison described later, the switch Sw2 is operated and the CPU 21 sends the signal to the clear terminal CL of the control FFC 43t1432. is the clear signal CLR
is given as a logic value of '1' to release the reset state of the FFCs 431 and 432, but initially the output Q of these is a logic value of '0', and while the AND gate 44 is turned off, the inverter The output of FFC11 becomes ``1'' and the AND gate 41 turns on, so that the signal from output Q of FFC11 becomes ZIS38.
This is transmitted as the transmission signal Ss.

However, when only receiving is performed without transmitting, the received data is judged and the received signal sR from the transmission line 2R is sent as is to the transmission line 2S via the switch SWI. There is.

Regarding the above, when the self acquires the transmission right, the switch S
W is brought into operation, and the outputs of the ZIS 38 and ASG 36 are transmitted to the transmission line 2S as a transmission signal Ss.

On the other hand, when the CPU 21 determines that a transmission right request should be made to the PSC 37, it sends an il indicating the priority of the transmission right.
In order to set the transmission right request signal containing the code by the combination of l, l″O”, this content is the clock pulse CL.
The data are sequentially sent out as serial data in accordance with K and applied to an exclusive OR (hereinafter referred to as EXOR) gate 47.

That is, if the CPU 2j determines that a transmission right takeover signal has been received, it sets the transmission data including the code indicating its own transmission right request priority in the PSC 37 before receiving the code indicating the priority. .

Therefore, when the output of ZEL 32 contains a similar code indicating the received priority, this is what is applied to the other input of EXOR gate 47.
Here, both codes are compared, and if the conditions are that the ZEL32O output is O" and the PSC37 output is 11",
EXOR game) The output of 47 is 11", this is MΦ
It is applied to the data terminal of FFC431 via gate 48, FFC431 is set in response to clock pulse CLK, and FFC432 is also set in response to this to set the output Q to 1''. PSC 37 turned on and delayed by delay circuit 46
The output of is sent out as a transmission signal SS.

The details of these operating conditions will be described later, and the output Q of the FFC 432 and the OR gate 42
The output of is given to the CPU 21 via the bus 39,
These are used to determine whether or not the own transmission data set by the CPU 21 in the PSC 37 has been transmitted.

FIG. 5 (4) shows an example of the contents of a transmission right request signal indicating the above situation. In each field, a destination code 52, a transmission right request code 53, a priority code 54, a source code 55 indicating the address of the sending STA, a CRC signal 56, and an end flag 57 are set. When the received signal sR is configured as shown in the figure, the priority code 54 indicates "2" in binary and is added at the source STA indicated by the source code 55 roooooooolJ. The assigned priority is ■.

On the other hand, the transmission right request signal that the own STA should transmit as the transmission signal SS includes a start flag 51, a destination code 52 with GLS set, a transmission right request code 53,
The end flag 57 is the same as the received signal sR, and only the priority code 54, source code 55, and CRC signal 56 are different. In this example, the priority is "4" in binary. Therefore, the priority level (2) of the received signal is higher than the priority level (2) of itself, and it is allowed to request transmission rights preferentially.

Therefore, in response to reception of the transmission right request signal, the switch sw
0FFC11 in FIG. 4, and receives the received signal sR.
Ha#'! 'If the signal is delayed one bit at a time and transmitted as the transmission signal Ss, then the reception signal sR, ! :The signal from the psc37 is compared by the EXOR gate 47, and since the start flag 51 to the fifth bit of the priority code 54 are the same, the output of the EXOR gate 47 remains positive. , when reaching the 6th bit of the priority code 54, the received signal Snl'l:@O'', the output of 5RG47 is 91''
Yes, the judgment condition that the priority of the player is high is satisfied, and as mentioned above, the output of the EXOR game) 47 changes to '1',
Instead of the priority code of the received signal sR, its own priority code is transmitted, and thereafter the output of the PSC 37 is transmitted in the same way.

Note that the delay circuit 46 connects the output of the PSC 37 and the FFC 11.
Please check the output and timing of the book.
In this case, the delay time may be set to approximately 1 bit worth of delay time.

) in FIG. 5 is a timing chart showing changes in the control signal So sent from the output Q of the clear signal CLRSFFC432 and the preset signal PSE.
When the PU 21 determines that up to the transmission right request code 53 of the transmission right request signal has been received, the clear signal CLR is changed from ``0'' to @1'' in response to this, and the FFC 431,
At the same time, the preset signal PSE is set to a non-signal state of ``1'', and the control signal SaS from the output Q of the FFC 432 is set from the 6th bit of the priority code 54 to ``1''. 1”, 9, AND
The gate 44 is turned on.

Note that the CPU 21 transmits its own transmission right request signal to another ST.
When the signal goes around all the transmission lines 21 to 24 via A and is received by itself, it is determined that it can acquire the transmission right.

FIG. 6 is a timing chart showing the signal status in each part of FIG. 4. υFFC11 responds to the rise of the clock pulse CLK (1) synchronized with the received signal sR changing from 10" to 1". Therefore, the output (a) of ZEL32 is delayed by approximately 1z2 cycles of clock pulse (1) and becomes the output (b) of FFC11, while the output (C) of PS037 is delayed by the delay circuit 46 by the same amount. becomes the delayed output (d), and depending on the mismatch between the two outputs (a) and (C), the output (・) of the EXOR gate 47 becomes '@
When it changes to 1", it is initially reset and the output Q of FFC43s is 1", so 1. The output (f) of the gate 48 of υ is '1'', and the next clock pulse (
1), FFC43 at time 1c
1 is set, turning the output Q(g) to ``1'' and turning the output Q to 0''.

Therefore, the melon gate 48 is immediately turned off and the output (f
) is returned to @0'', υFFC43r is reset by the rising edge of the next clock pulse (i), and the output (x) is
0'', but the output (g) is given to the clock terminal CK of FFC432, and the output (-) changes from 'O'' to '1''.
When switching to t, FFC43z is set by '1' of output (e) applied to the data terminal, and at time t
After e, the output (h) of the FFC 432 maintains ``1'', and this is sent to the melon gate 44 and the inverter 45 as the control signal S03.

Therefore, in (4) and ω) of FIG. 5, it is determined that the received priority is also higher than the received priority.
In response to this, a switch $6 consisting of gates 41, 44, OR gate 42 and inverter 45 is controlled.

FIG. 1 is a timing chart showing the status of signal transmission and reception between STAs when this method is applied to the method disclosed in Japanese Patent Application No. 61-132626. A takeover signal cp indicates that the transmission right is to be taken over when the data transmission is completed.
Transmission S is performed using the data as GLS.

Then, this is immediately relayed and received at STA-CEB-C1:Fu, and reception R is performed at STA/CEA via a loop-shaped transmission path.

In response to receiving the takeover signal CP, the 5TA-CEA determines that this has been received by another STA @CEB-CEz, and transmits an enabling signal OK indicating that the takeover signal CP should be recognized as valid. , this is another STA
- Received at CEB~CEM and STA
Also received at @CEA.

Note that mode M is the transmission mode shown by the solid line, and the transmission mode shown by the chain line.
Comparison mode by 90P04G, other indicates reception mode, STA-CEB, C with transmission data according to reception of takeover signal CP and enable signal OK.
Eo and CEx are switch SW.

The comparison mode is set under the control of 2.

On the other hand, when the STA-CIA receives the activation signal OK and further requests to occupy the transmission right, it sends a blank code (NuLt, ) NU is added and sent, and this is the STA.
” CEB N CED
At EB, it is relayed without any delay.

However, the request signal CTA(NU) is STA-CEB
The signal is received by the receiver R, but the above-described operation determines its own high priority V, and this is added to the request signal CTB (b), which is transmitted with a delay of about 1 bit.

The request signal CTB(V) is received by the STA-CED, but since its own priority is V and is equal to the received priority V, the received request signal CTB(V) is received by the STA-CED.
) is that #? i' is transmitted with a delay of 1 bit.

This transmission is received by STA-CEx K) and here it is determined by its own high priority (■), and this is added to the request signal CT (■
), which is received at STA-(JA).

Then, 5TA-CIA transmits its own request signal C.
Since TA (NU) was not received, it was determined that the utendenryu that had been occupied until now should be abandoned, and the 9-request redemption code CT was received.
In response to g(■), an occupancy signal BTK that prohibits other interrupts is transmitted, and this is sequentially relayed to the STA-
When the CE message is received, STA@CE Aya sends it further and determines that it has acquired the right to send it.
After setting the transmission mode, use the enable signal O as a confirmation signal.
After transmitting K, this is relayed sequentially and goes around, and if it can be received by the other STA-CEANCED
Also, it is determined that the STA@CE tile has confirmed that it has acquired the transmission right, and enters the transmission state of the transmission data DTK.

In addition, in response to re-reception of the exclusive signal BTI, the STA and CIA give up the transmission right and shift to reception mode.
While the occupancy signal BTx is not re-relayed, STA・C
At EB, the occupancy signal BT! Upon receipt of the STA
@CED returns to the receiving mode in response to the transfer of the request signal CTB(V).

Therefore, in the reception mode that does not go through the CPC 40, the received signal is relayed and transmitted without any delay, while in the comparison mode, the CPC 40 is inserted, and the transmission that goes through it has a delay of about 1 bit. However, since the CPC 40 is inserted only when necessary, the overall transmission speed is improved, and various data transmission and control responsiveness are realized at high speed.

In addition, a request signal CT, an occupancy signal BT, and an enable signal O
By making one cycle of K, the transmission right is reliably handed over, and the time required for the handover is shortened.

However, as the request signal CT and the occupation signal BT, so-called free tokens, visit tokens, etc. may be used, and the activation signal OK is originally for validating the GLS that should be received by all STAs. The same effect can be obtained even if this is not used as the confirmation signal, and a separate signal is used as the confirmation signal.

Note that the transmission and reception of the confirmation signal may be omitted; in this case, in response to the transmission and reception of the takeover signal CP, the STA/CEA relinquishes the transmission right, and each STA-CEB to CED transfers the transmission right to the CTA-CF, CTA-CF, It is sufficient to confirm that the information has been acquired.

FIG. 7 is a general flowchart of the control situation by the CPU 21, in which fi is executed while accessing necessary data to the RAM 22 in response to instructions in the ROM 23.

That is, after 1 initialization m101, each STA
- CE ~ A judgment is made as to whether the CED will be the primary side that has the transmission right or the secondary side that does not have the transmission right, and depending on the result, the ``primary side?'' 102 determination is made. , the necessary parts are cleared.

Note that step 101 is performed when the power is turned on or when the power supply recovers from a power outage. For example, the determination in step 102 is based on setting a waiting time for each STA @ CEA-CEI+ according to its address number, and if no signal is received during this time, it is determined that the STA has the right to transmit, and the STA does not accept requests from others. If the signal is received, it is determined that there is no transmission right.

If step 102 is Y (YES), the control signal Sa
t, operate the switch switch SW, and select "Transmission mode setting"
After executing step 111, the takeover signal ``CP transmission'' 112 is executed, and the same signal ``CP reception? ) , and a certain period of time rTRx has elapsed according to the timer in the CPU 21?J 114 is N
During this time, steps 113 and subsequent steps are repeated, and if step 114 becomes Y due to time-up of the timer, the CPU
Until the maximum number of repeated transmissions M set in the counter in 21 is reached, steps 112 and subsequent steps are repeated via "Number of transmissions = M?" 115 ON, and when step 115 becomes Y, "abnormality processing" is performed. The process moves to step 116, where an alarm is sent out and displayed.

If step 113 becomes Y while step 115 is N, the validation signal rOK is sent" 117, and step 1
Similarly to step 13, check J118 for the same signal "OK received?", and while this is N, the same as steps 114 and 115 (
Has rT11 passed? J119 and “Number of transmissions = M?J1
20, repeat steps 118 or 117 and subsequent steps, and proceed to step 116 depending on Y in step 120.9
go

If step 118 becomes Y while step 120 is N, a blank code NU is added and the request signal [self-CT(NU
) Transmission" 121, and check whether the open signal rCT is received or not as shown in FIG. 1. Check with J122,
While this is N, the same as steps 114 and 115<rT
AT progress? J123 and "Number of transmissions = M? Repeat steps 122 or 121 and subsequent steps via N in J124,
In response to step 124 becoming Y, the process moves to step 116, while step 122 becomes Y while step 124 is N0, and the received content is determined to be the blank code "NU?J125" sent by the self. However, when this is Y, it is possible to acquire the transmission right rather than the request signal CT from another STA, so it sends a message to itself saying “Do you have data to send? J12
Check 6.

On the other hand, if step 125 is N, other STA
The CPC 40 compares the priority code added to the request signal CT with its own priority code, and determines "Self priority ≧ reception priority? J131, and if this is N. In response to this, the control signal SaS is o'', and the received request signal is stored in the buffer memory BFM (BFM+-CT) 132 using a part of the RAM 22, and its contents are stored once. "Other BT transmission J 133 transmits the occupancy signal BT according to the switch SW,
, “Receive mode setting” 13 according to the recovery control of SW2
After performing step 4, the activation signal rOK as a confirmation signal
Reception? If J135 becomes Y, the transmission right is abandoned and the process moves to "receive mode setting" 183, which will be described later. On the other hand, while step 135 is N0, "T old progress?" 136 is monitored as in step 114, In response to this being Y, perform "Set transmission mode" 137 in the same way as step 111, and "
Number of transmissions = M? Step 133 and subsequent steps are repeated via J138, and as step 138 becomes Y, the process returns to step 112.

Furthermore, if step 126t or step 131 becomes Y, it means that the self has acquired the transmission right, so the same as step 132 (rBFM4-CTJ 141 is performed, and in response, the own exclusive signal "self BT transmission" is performed) After performing step 142, select "Reception mode setting" 14 as in step 134.
4, and similarly to step 113, the occupancy signal 1'-B is
T reception? Check J144, and depending on the N of this, the same as steps 114 and 115 <rT old progress? J145
and "Number of transmissions = M?" Step 144 or 142 onwards are repeated via N in J14B, and step 146 is Y.
If so, the process moves to step 116.

If step 144 becomes Y while step 148 is N, the validation signal rOK is sent" 151, and step 1
Similarly to steps 18 to 120, while the same signal "OK reception?" 152 is N, "T old progress?" As 154 becomes Y, the process moves to step 116.

If step 152 becomes Y while step 154 is N, when new transmission data is generated, it is determined whether the priority of this data is higher than the priority of the data transmitted after step 115 (described later). In order to check whether "occurrence priority>transmission method priority? By comparing with the priority transmitted after step 175, it is determined "Is the other highest priority = transmission method priority?" 156, and if step 156 is N, repeat steps 112 and after. While giving other STAs an opportunity to acquire the transmission right, even in response to Y in step 155, steps 112 and subsequent steps are repeated.

Also, step 155 is N1 and step 156 is Y.
In this case, the "data transmission process" 15T is performed, and steps 155 and subsequent steps are repeated, and until step 156 reaches N, the own transmission data is transmitted in order from the one with the highest priority, but when step 156 is N, After that, other STA
If a request signal CT with a higher priority is transmitted, and step 131 becomes N, then step 135 becomes Y, the process moves to reception mode setting 183, which will be described later.

If step 102 is NO for the lift, switch s'
After restoring wl and performing "reception mode setting" 161, the takeover signal "CP reception?J" is sent as in step 113.
162, and in accordance with Y, step 118
Similarly, the enabling signal "OK received?" 163 is further checked, and while this is N, in preparation for repeated transmission of the takeover signal CP, the open signal RCP received? ”164, repeating steps 162 and subsequent steps corresponding to Y, step 164 is N
Then, similarly to step 114, TR1<< Has the predetermined time rTRz set as TR2 elapsed? J165 is monitored, and step 164 is Y or step 165 is N.
During this time, steps 162 and subsequent steps are repeated, whereas if step 165 becomes Y, the process moves to step 116.

If step 163 becomes Y while step 165 is N, it means that the opportunity to acquire the transmission right has arrived, so the user says ``Check the transmission data A1J16B, and if this is Y, the 5th
Give the own priority code 54 and subsequent ones shown in the figure to the PSC 37, perform the data set to r psc 1'71, and send the control signal 8B+ to the switch 17
At the same time, in order to input the CPC4G, the switch ``sw2 operation'' 173 is performed by sending the control signal Sc2, and the comparison mode by the CPC40 is set, and the other ST
Reception of request signal rCT from A (51-53)? J1
74 becomes Y, and when the reception from the start flag 51 to the GLS code 53 is completed, the process shown in Fig. 5 CB) is performed.
Clear signal “mouth=11” 175 is executed, FFC43
2 and the output of the OR gate 42, it monitors whether or not its own priority code FP or later has been transmitted.
Self-priority>Reception priority? After determining J178, if this is Y, it is determined that its own transmission priority is higher than other transmission priorities and that it has the right to transmit, but in step 178
, it is determined that the transmission right is not granted to itself.

Note that while step 174 is N, in preparation for repeated sending of the enabling signal OK, the open signal rOK is received? J176 is checked and 1 is the same as step 165 according to the NK of < rTn2 TR2 progress? J193 is performed, and steps 114 and subsequent steps are repeated according to Y in step 176 or N in step 177, and if Y in step 177, the process moves to step 116.

When step 178 is N, "SW, restoration" 181 is performed by stopping the transmission of the control signal SCI, and "s'w2 restoration" 182 is performed by stopping the transmission of the control signal SC2. "Receive mode setting" 183, "Receive data processing" 184 and "Receive data processing" 184
After performing "monitoring process" 185, steps 162 and subsequent steps are repeated.

Note that if step 178 is Y, the own priority code 54 will be transmitted from step 173 onwards, and if step 178 is N, the priority code 54 received from step 173 onwards will be transmitted as is; Also in this case, the start flag 51 and subsequent parts of the request signal CT are transmitted with a delay of approximately 1 bit.

On the other hand, if step 178 is Y, the clear signal “Fan =
After resetting the FFCs 431 and 432 using "O" 191, check the request signal "CT reception (51-53)?J192" and monitor "TR2 progress?J193" as in steps 174 and 177. ,
If step 193 becomes Y, the process moves to step 116, whereas step 192 shows Y while step 193 is N, the clear signal rcLR="l"" 194 is performed in the same way as step 175, priority code 54
Occupancy signal rBT?J whose 8th bit is @1”
195, and if this is N, step 1
78, when step 195 is Y, clear signal 1'-CLR=' as in step 191.
``O'''' 196 and determines whether the received occupancy signal BT designates itself based on ``own BT? 1. Same as step 182 <"sw2recovery" 19B
At the same time, as in step 111, "transmission mode setting" 199 is performed, and then the process moves to step 151.

Note that if step 198 is N, it is ultimately impossible to acquire the transmission right, and the process moves to step 181.

Therefore, only when step 166 is Y and requests the transmission right, the comparison mode is set after step 172 and CPC 40 is inserted, while in other cases, CP04G is excluded and relaying is not performed. No delay at all.

Furthermore, by transmitting the request signal CT with the blank code NU added in step 121, the possibility that other STAs with the same priority will also be able to acquire the transmission right increases, and the same STA
The continued possession of transmission rights by a TA is precluded;
Equal opportunities for acquiring transmission rights will be achieved.

FIG. 8 is a flowchart showing the details of step 153.
If the result is N, only “data transmission” 202 is performed, but when step 201 is Y, r GLS transmission” 211 is performed.
In addition, whether or not this is received via all transmission paths is monitored by "Transmission GLS Reception? J212, and while this is No, rTRt bond over? J213 Y and “Number of transmissions = M?
Steps 211 and subsequent steps are repeated via N in J214, and when step 214 becomes Y, "abnormality processing" 215 is performed in the same manner as step 116.

If step 212 becomes Y while step 214 is N, the enabling signal rOK is activated as in steps 117 to 120.
Transmission" 221 and same signal 1'-OK received? ”22
Has a certain period of time rTut passed through N in 2? Judgment of J223, "Number of transmissions = M?J224175N" corresponding to Y of this
Step 221 and subsequent steps are repeated via step 224, and as the result of step 224 becomes Y, the process moves to step 215. If the OK times signal can be received while step 224 is N, step 222 becomes Y.

FIG. 9 is a flowchart showing the details of step 184. In response to Y of received data A1J30Q, [received data is CI, S? After performing "clear" 3o2, it checks "addressed to self? J303" based on the address code 52 of the destination added to the received data, and performs "content decoding" 304 in response to Y of this.

Moreover, when step 301 is Y, the contents are valid, and the validation signal roy, ? J31t, and if the result is N, store GLS in the buffer memory BFM by rBFM4-GLsJ 312, repeat step 162 onward in FIG. In response to step 311 being Y, check ``81M Contents A1J321'' and follow this Y to ``BFM''.
322, and the process moves to step 304.

FIG. 10 is a 70-chart showing details of step 185. The main table and sub-table shown below are provided in the RAM 22 as specific areas, and these are used.

That is, the main table (hereinafter referred to as MT) and the sub-table (hereinafter referred to as ST) correspond to each STA-CEA to CE in FIG.
If the operating status of each STA is determined to be normal during a certain monitoring period, the code is indicated by an O symbol, and similarly, if the operating status of each STA is determined to be abnormal, the code is indicated by an X symbol. The information is stored in accordance with the above information, and registration is performed based on this information.

Note that for the MTs in Table 1, the judgment results during the previous monitoring period are registered as they are, and the MTs in Table 3 are used as the MTs in Table 1 in the next monitoring period.

In FIG. 10, "Power ON?J 401 is judged, and if this is Y, all "Timer Star) J 4
After performing step 11, perform "all × registration to ST" 412 as shown in Table 1, and depending on the result of step 304, which 5TArCKl acquires the transmission right? J421 is determined, and if this is Y, "CEi of MT = X? j
422, and if it is Y, select “MT
Perform "○ registration" 431 to CEi of fist ST, for example, CE
i = In the CIA, the state is set as shown in Table 2, and according to the rcEi recovery notification 432, the STA-CEi is displayed that it has recovered from abnormality to normal, and a message that it can be selected as a communication partner is stored in the RAM 22. Perform processing such as

If step 422 is N, "Register ST to CEL" 433 is performed. For example, if CEi=CEB, the procedure shown in Table 2 is performed, and "Timer time up? J44
While 1 is N, steps 421 and subsequent steps are repeated, and step 4
After performing “judgment processing” 442 in response to Y in step 41,
The above operations are repeated through step 162 and subsequent steps in FIG.

Therefore, for example, STA @CEA and CEc acquire the transmission right in sequence, and STA ``CEB+CED''
If the result is not obtained, the state in Table 2 is changed, and in step 442, the contents of MT that showed the previous result are finally updated, and the state shown in Table 3 is changed. Becomes the property of

That is, in step 422, the contents of the following table are executed.

Table 4 Note that "Abnormality Occurrence Notification" includes a display similar to step 432 and a message in RAM 2 indicating that it cannot be selected as a communication partner.
Processing such as storing to 2 is executed.

Therefore, if all or at least a plurality of STA/CEA to cED perform the above operations, an abnormality will be determined based on the comparison at the time of "x registration" in Table 4, and a corresponding notification will be issued. At the same time, the recovery to normality is also notified in step 432, and this is done in each STA, so even if any STA loses its monitoring function, the overall monitoring function will not be lost. The reliability of the entire system is improved.

However, step 431 may be for ST only, MT O registration may be included in step 442, and step 43
Similar results can be obtained by similarly including 2 in step 442.

As described above, signals other than the request signal CT are relayed without delay between each STA connected in a loop, and only the request signal CT is delayed by approximately 1 bit as necessary. transmission speed is improved.

Furthermore, when the STA that had previously occupied the transmission right finishes transmitting, it adds a blank code NU to the request signal CT and sends it. If the blank code NU is the lowest priority, even if there is another STA with the same priority as the STA that has previously occupied the transmission right, the STA that has previously occupied the transmission right will Furthermore, there is no need to acquire a transmission right, and each STA has an equal opportunity to acquire a transmission right, and overall data transmission congestion can be eliminated.

However, when FFC11 is used as a delay element, it is suitable because it also exhibits a waveform shaping effect, but other elements or circuits may be used, and the delay time may be larger than 1 bit or more as long as it does not cause any practical problems. The same is true for the configuration shown in Figure 4, which can be selected arbitrarily according to the conditions, and in the configuration shown in Figure 5, even if the priority code other than 54 is transmitted after reversing the order of each bit. good.

In addition, the priority may be determined by assigning a code indicating the importance to each transmitted data, and the rank of this is (I) to (
In addition to (■), it may be determined according to the conditions, and the destination address code of the data signal can be used to determine which STA has the right to transmit.
When all other STA are specified at the same time, each specified STA may maintain the reception mode.

In addition, if the validation signal OK as a confirmation signal is omitted, various modifications may be made, such as using a request signal CT in place of each of the steps shown in FIGS. 7 to 10.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the overall transmission time between loop-connected STAs is significantly shortened, and data transmission speed and control status are highly responsive. It has achieved remarkable effects in various data transmission and control.

[Brief explanation of drawings]

The figures show an embodiment of the present invention, Fig. 1 is a timing chart showing the transmission and reception status of signals between each STA, Fig. 2 is a block diagram showing the overall configuration, and Fig. 3 is a block diagram showing the configuration of the STA. , FIG. 4 is a block diagram showing the specific configuration of STA, FIG. 6 is a timing chart showing the signal status in each part of FIG. 4, FIG. 7 is an overall flowchart, and FIGS. 8 to 10 are flowcharts showing lower routines of FIG. 7. . zl~z02R+ 23 "'""Transmission line, 11
, 43t. 432...FFC (flip-flop circuit L21)
...@CPU (processor), 22...RAM (
variable memory), 23...ROM (fixed memory),
31... spc (serial parallel converter), 37...
psc (parallel-serial converter), 40... cpc (comparison circuit), 41, 44, 48... fist/AND gate, 4
2... @OR game), 45. War... Inverter, 46
...Delay circuit, 4T...EXOR (exclusive OR) gate, 53...Transmission right request code, 54...
-Priority code, CEA-CED...STA (
communication device), sR...reception signal, Ss...fist transmission signal, SO...transmission output, RI...reception input, Swl, Sw2...switcher, CT...φ or transmission right request signal. 2nd (21 Figure 3 Figure 6 tC ■ (1) LJ LJ
LJ LJ LFigure 9

Claims (1)

[Claims] Consisting of a plurality of communication devices connected in a loop, a signal received from one transmission path is transmitted to the other transmission path, and the communication device requesting the transmission right gives priority to the transmission right to the transmission right request signal. In this method, the received signal is transmitted with a time delay of approximately 1 bit, and the received priority code is compared with the own priority code to determine the own priority code. is provided with a comparison circuit that transmits its own priority code in place of the received priority code when the priority code is high; A communication control system characterized in that signals other than the transmission right request signal are transmitted to the other transmission path without going through the comparison circuit.