JPS62175050A - Transmitting right request signal transmitting system - Google Patents

Abstract

PURPOSE:To widely shorten the time needed for relaying and the changing-over transmission of a priority right request signal by comparing the priority degree received in accordance with the receiving of a transmitting right request signal and own transmitting right request priority degree and controlling a switch when own priority degree is high. CONSTITUTION:Between a transmission line 2R and other transmission line 2S, a D-shaped flip-flop circuit FFC 11 interposes as a delaying element. In accordance with a clock pulse CLK synchronized with a receiving signal SR given from an I/F 1b to this clock terminal CK, a receiving signal SR given to a data terminal D is successively held and sent from an output Q. Thus, by a delaying element equipped at respective communicating devices, the receiving signal receives only the delay of at least approximately one bit, is transmitted to other transmission line through a switch, the delaying time due to relaying is decreased, when own priority degree is higher than the priority degree in accordance with the receiving of the transmitting right request signal, the control of the switch is executed, own transmitting output is connected to other transmission line, transmission is executed after the code to show own priority degree and the transmission of the transmitting right request signal is executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transmission method applied to transmitting and relaying a transmission right request signal between a plurality of communication devices connected in a loop.

[Conventional technology] LAN (Local Area Network,
), various on-premises control equipment, etc., as proposed in Japanese Patent Application No. 59-260800 filed separately by the present applicant, a transmission line is used to connect multiple communication devices that transmit and receive data in a loop-like manner. Once connected, the direction of data signal transmission is determined, and while one of the communication devices acquires the transmission right and is transmitting, the other communication device receives from one transmission path and relays the signal, and the other communication device receives the signal from the other transmission path. When transmitting to a transmission path and acquiring a new transmission right upon completion of transmission, the communication device requesting the transmission right generally uses a token (Token).
A code indicating the priority of the transmission right is added to a transmission right request signal called ken) and transmitted, and the communication device with the highest priority acquires the transmission right.

[Problem that the invention seeks to solve]

However, conventionally, each communication device determines whether it should relay and transmit Reception No. 4 or should itself receive it, and when receiving the transmission right request signal, determines whether it should acquire the transmission right or not. The decision as to whether to transmit without relay [2] is made after all signals are received, and if relay transmission is to be performed, the time required for determination 1 is added for each communication device, especially for transmission right request signals. This has resulted in the problem of increased delay time due to transmission decisions.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, in the above method, a delay element that transmits a received signal with a time delay of at least approximately 1 bit;
Each communication device is equipped with a switch that switches from the output of this delay element to its own transmission output and connects it to the other transmission path, and the priority received in response to the reception of the transmission right request signal and the own transmission right request priority. , and when its own priority is high, it controls the switching device to transmit a code indicating its own priority instead of the received priority code, and performs subsequent transmissions from itself. It is said that

[For production]

Therefore, due to the delay element provided in each communication device, the received signal 4 is transmitted to the other transmission path via the switch with only a delay of at least 1 bit, reducing the delay time due to relaying. At the same time, in response to reception of a transmission right request signal, if the priority of the transmission right request signal is higher than that of the transmission right request signal, the switching device is controlled, and the transmission output of the transmission right is connected to the transmission line of the other side, and the transmission output of the transmission right is connected to the other transmission line. The code after the priority code is transmitted, and the transmission of the transmission m-* request signal is also speeded up.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 2 is a block diagram showing the entire configuration. A plurality of communication devices (hereinafter referred to as ST) 11 to 14 are connected in a loop through transmission lines 21 to 24, and in this example, signals are transmitted in the direction indicated by the arrow. The transmission is to be carried out,
For example, when 5T11 acquires the transmission right and is transmitting to 5T14, 8T1x and 8T13 relay and transmit the received signals.

FIG. 3 is a block diagram showing details of %ST1, in which an interface (
Hereinafter, I/F) lb is set up, and the receiving power R of this is set up.
1, one transmission line 2R is connected to the other transmission line 2S, and a D-type flip-flop circuit (hereinafter referred to as FFC) 11 is interposed as a delay element between the transmission line 2R and the other transmission line 2S. Reception No. 4 S given from I/Flb to CK
According to the clock pulse CLK synchronized with R, the 4th reception signal SR given to the data terminal is held sequentially and sent out from the output Q. As a result, about 1 bit worth of data is sent to the reception No. 4. Give delay and send to transmission line 2S No. 4 S
It is to be transmitted as 3.

! In addition, the output Q of the FFC 11 is connected to the transmission line 2S via the switch SW, and when the I/F1b generates the control signal Sc, the switch SW responds to change the output Q of the FFC 11 to the r/F1b. Since the transmission output is switched to SO and connected to the transmission line 2S, the signal from the I/F 1b is transmitted to the transmission line 2S.

Figure 1 shows the main device 1a, I/Flb, F'FC
11 and a block diagram showing a specific configuration of the so-called switching device), a processor such as MicroMoro
) 21, variable memory (hereinafter referred to as RAM) 22, fixed memory (hereinafter referred to as ROM) 23, bus controller (hereinafter referred to as BC)
T) 24, serial/parallel converter such as shift register (hereinafter referred to as 5)
PC) 31, “0” bit deletion circuit (hereinafter referred to as ZI2L)
32, CRC (Cyclic RedundancyC)
heck, ) detection circuit (hereinafter referred to as CRD) 33, abort (AbOrt)/idle detection circuit (hereinafter referred to as AAD)
) 34, CRC signal generation circuit (hereinafter referred to as CRG) 35, abort signal generation circuit (hereinafter referred to as A, 5G) 36, shift i.
Parallel-serial converter (hereinafter referred to as PSC) 3L such as a register
O'l: 7-tooth insertion circuit (hereinafter referred to as ZIS) 38 etc. is provided, and the reception number 4 811 of the transmission line 2R side is connected to ZEL32.
In JISC6363 etc. (D HDLC procedure, the υ°0" bit is deleted, the 5PC31 converts it into parallel data, and it is given to the CPU 21 via the bus 39, and the instructions in the ROM 23 are sent to the CPU 21 via the bus 39. The CRG35.AS
G36 and provides parallel data transmission data to the PSC37.

Then, the transmission data becomes serial data9 in the PSC37, a CRC signal from the CRG35 is inserted, and the data is transmitted to the ZIS3 via the transmission circuit (hereinafter referred to as 5SC) 4G.
8 and the aforementioned HDLC in ZI83B
The procedure inserts the ``0'' bit, and
When interrupting transmission as necessary, after inserting an abort signal from ASG36, transmit No. 4 SB to transmission path 2S.
Sent as .

Note that the reception No. 4 SR is also given to the AAD 34, and the CPO 21 performs predetermined control according to its detection power and the output indicating the check result of the CHD 33. Depending on the conditions, the DMA (Direct Me
mor)' Access, ) control, 98PC31
The received data from the BCT24 is transferred to the RAM22
Otherwise, the contents of the RAM 22 are sent directly to the PSC 37.

In addition, the output of ZgL32 is the FF included in 5SC40.
It is applied to the data terminal of C11, and the output Q of this is applied to the data terminal of AN.
D gate 41. It is supplied to the input of ZIS3B via the OR gate 42, and is normally connected to the control FFC431,4.
For h, the CPU 21 gives the clear signal CLR to the clear terminal CL of this, and resets the FFCs 431 and 432. Therefore, the output Q of this is the logical value "0", and the AND game 144 is turned off. On the other hand, the output of the inverter 45 becomes the logical value 1'', and 9, AND
Since the gate 41 is in the on state, the signal from the output Q of the FFC 11 becomes zis3 as in FIG.
8, and this is transmitted as transmission No. 4 Ss.

In contrast to the above, when the user obtains the transmission right, FFC4
Since the CPU 21 gives the preset signal PSE to the preset terminal PR of the 3z, the FFC 43 is set and the output Q is set to "1", and the AND gate 44 is turned on, while the output of the inverter 45 is set to "0" and the A
Turn off the ND gate 41, apply the signal from the delay circuit 46 instead of the output Q of the FFC 11 to the input of the ZIS 38 via the AND gate 44 and the 01N gate 42, and transmit it to the transmission line 2S as the transmission No. 4 Ss. Become something.

On the other hand, for the PSC 37, when the CPU 21 determines that a transmission right request should be made, it sets a transmission right request signal that includes a code that is a combination of '1' and 'On' indicating the priority of the transmission right. Content is clock pulse C
The data is sequentially sent out as serial data in accordance with LK and applied to an exclusive OR (hereinafter referred to as Ili:X0R) gate 47.

That is, if the CPU 21 determines that the reception of the transmission right request signal is to start, the CPU 21 sends the transmission data including the code indicating the priority of its own transmission right request to the PSC before receiving the code indicating the priority.
It is designed to be set to 37 degrees.

Therefore, when the ZEL32 output contains a similar code indicating the received priority, this is the EXOR
p is applied to the other input of gate 47.
, ZgL32 output is 0", PSC37 output is "l"
If the condition is met, the output of the gXOR gate 47 becomes "1", which is applied to the data terminal of the FFC 431 via the AND gate 4, and the FFC 431 is set according to the clock pulses CI and K, and this According to “CFF”
Since C4h is also set and the output Q is set to "1", the same < AND gate 44 as described above is turned on, and the output of PSC3γ delayed by the delay circuit 46 is sent to the transmitter No. 4 S.
Sent as s.

Note that these operating conditions will be described in detail later.

FIG. 4(A) shows an example of the contents of a transmission right request signal indicating the above situation, in which case the signal includes a start flag 51 of each 8 bits, a global code 52 indicating that it should be received in all STs, A transmission right request code 53, a priority code 54, a transmission source code 55 indicating the address of the transmission ST,
It is configured by the CRC signal 56 and the end flag 5γ, and when the reception No. 4 SR is in the illustrated state, the priority code is 5.
4 indicates "2" in binary, and the sender code is 5.
S of the source indicated by r 0OOOOOOIJ of 5
The priority added to T is ■.

On the other hand, the transmission right request signal to be transmitted by the own ST as transmission No. 4 S- is the start flag 51,
The global code 52, the transmission right request code 53, and the end flag 5T are the same as the received signal SR, the priority code 54, the source code 55, and the CRC signal 56.
In this example, the priority is "4" in binary
Therefore, its own priority ■ is higher than the priority ■ of the receiver No. 4, and it is allowed to make a transmission right request preferentially.

Therefore, according to the FFC 11 in FIG. 1, the received signal SR
is delayed by M1 bits, and the transmission No.4 SR and PSC37
The gXOR gate 47 compares the signals from the start flag 51 to the fifth pit 1 of the priority code 54, so the output of the gXOR gate 47 is "
0", but when reaching the 6th bin of priority code 54, the receiving No. 4 SR is "o" and the output of 5RG47 is "
1, and the judgment condition that its own priority is high is satisfied, and as described above, the output of the EXOR gate 47 is ``1''.
', and instead of the priority code of the received No. 4 SR, its own priority code is transmitted, and from then on, the output of PS03T is transmitted in the same way.

Note that the delay circuit 46 connects the output of the PSC 37 and the FFC 11.
This is to match the timing with the output of
In this case, the delay time may be set to a delay time of 1 bit.

Figure 4(n) shows the clear signal CLR, FFC4:h
In the timing chart showing the change status of the control signal Sc and preset signal PSE sent from the output Q of , and determines that it should also request the transmission right, changes the clear signal CLR from "0" to "1" accordingly, and the FF
In addition to canceling the reset state of C43s and 4h, the preset signal mamomi is set to a no-signal state of "1",
As mentioned above, the control signal Sc becomes 1'' from the sixth bit of the priority code 54, which turns the AND gate 44 on.

Note that when the own transmission right request signal goes around all the transmission lines 21 to 24 via other STs and is received by itself, the CPU 21 determines that it can acquire the transmission right, and sets the preset signal PSE to 0. ", the FFC 432 is forcibly set.

On the other hand, Fig. 4(c) is a sunset timing chart similar to (B) in which the received No. 4 SR is sent to the ST. The signal PSE is in the preset state of 101, 9, and g.
Accordingly, the control signal Sc becomes "l", and the AND gate 4
Keep 4 on and send the output of P4O10 to Aoi Ss, L
-l- Send 1. Figure 5 is a timing chart showing the signal status in each part of Figure 1, and shows that the clock pulse CLK(i) synchronized with the receiving No. 4 SR is 1.
Since the FFC11 responds to the rising edge that changes from 0' to "1", the output (a) of ZEL32 becomes the clock pulse (i) Oho";
FC11O output (b), while PSC37 output (
c) receives an equivalent delay from the delay circuit 46, and the delayed output (
d), and when the output (e) of the mXOR gate 4γ changes to "1" in response to the mismatch between the two outputs (a) and (c), it is initially reset and the output Q of the FFC431
is '1°, so the output of AND gate 48 (
f) is “l” υ′, and the next clock pulse (i
), FFC4 at time tc
3+ is set, output Q(g)f: is turned to "1", and output Q is turned to "0".

Therefore, the AND gate 48 is immediately turned off, the output (f) is returned to "0", and pF'Fc43t is reset by the rising edge of the next clock pulse (i), and the output (g
) is “O”, but the output (g) is given to the clock terminal CK of FFC43!, and the output (g) is “0”.
When the signal changes from "1" to "1", FFC43□ is set by "1" of the output (c) given to the data terminal, and after time t0, the output (h) of FFC4h becomes "1".
l'' is maintained and sent to AND gate 44 and inverter 45 as control signal Sc.

Therefore, as shown in FIGS. 4(A) and CB), it is determined that its own priority is higher than the received priority, and the switch SW is controlled accordingly.

FIG. 6 is a timing chart showing the signal transmission and reception status between each 87 when this method is applied to the method according to the above-mentioned Japanese Patent Application No. 59-260800. In order to request possession of the transmission right, the transmitter S adds its own priority ■ to the request signal CTI indicating the request for the transmission right and transmits it.This is received by the receiver R at 5T12, but the above-mentioned operation A determination is made as to the high priority (2) of the N9 self, and this is added and transmitted as the υ request signal CT2 with a delay of one bit.

This transmission is received by 5T13), but based on its own high priority judgment, this is added and transmitted as a request signal CTs with a delay of the Sol bit, and in 5T14 , this is soma\ha so1
relayed and transmitted with a bit delay, 5T11
received at.

Then, ST1+ receives the request signal CT sent by itself.
l(I[I) is not received, it is determined that the transmission right that has been occupied so far should be abandoned, and the received request signal CTs
(V) is stored once and then transmitted, and if this is relayed sequentially and received by 5T13,
5T1B further transmits this, determines that it has acquired the transmission right, transmits an activation signal OK, and this is relayed in sequence, making a round, and if it can be received by itself, it is transmitted to other ST1. .

12.14 as well, it is determined that ST13 has confirmed that it has acquired the transmission right, and enters the transmission state.

In addition, ST1. relinquishes the transmission right in response to re-reception of request signal CT3(V), and also releases request signal CTs(V).
will not be re-relayed.

Therefore, the relay transmission of the received signals is carried out with only a delay of 1 bit, and the time required for relaying is greatly shortened, and the transmission right request signal can be relayed and the transmission right request signal can be switched to the own transmission right request signal. Although the time required for processing is the same, the overall transmission speed is improved, and various data transmission and control response speeds are realized.

However, when using the FFC11 as the delay element, it is preferable to use it because it also exhibits a waveform shaping effect, or other elements or circuits may be used, and the delay time may be greater than 1 bit as long as it does not cause any practical problems. The configuration in Figure 1 can be selected arbitrarily according to the conditions, and in Figure 4 (4), the order of each bit is inverted and transmitted except for the priority code 54. Various modifications are possible.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, the time required for relaying and switching and transmitting priority request signals between each 87 loop connections is significantly shortened, and the overall transmission speed is improved. S-q! Significant effects can be obtained in r types of data transmission and control.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the specific configuration of the ST, Figure 2 is a block diagram showing the overall configuration, Figure 3 is a block diagram showing the configuration of the ST, and Figure 4 is a block diagram showing the configuration of the ST. Figure (4
) is a diagram showing the configuration of the transmission right request signal, FIGS. 4(B) and (C) are timing charts showing changes in the clear signal, control signal, and brisset signal, and FIG. 5 is a diagram showing the structure of each part of FIG. 1. FIG. 6 is a timing chart showing the signal status. FIG. 6 is a timing chart showing the signal transmission/reception status between each ST. 11-14...ST (communication equipment [), 21-24.
2R, 2S...Transmission line, 11, 43s. 432-・e・FFC (flip-flop circuit), 21
...-CPU (processor), 22-・Fist・RAM
(variable memory), 23... φ ROM (fixed memory), 31... spc (serial parallel converter), 37...
-・PSC (parallel-serial converter), 40...SSC (sending circuit), 41, 44° 48...AND gate, 4
2...Fun OR gate, 45◆Fist-Φ inverter, 46
- Shoken Fung delay circuit, 4γ...EXOR (exclusive OR) gate, 53... transmission right request code, 54...
・・Priority code, SR・・Reception number, S8・・・・
・Transmission No. 4, SO...---Transmission output, RI...
Reception input, SW...◆ is also a switch.

Claims (1)

[Claims] Consisting of a plurality of communication devices connected in a loop, a signal received from one transmission path is relayed and transmitted to the other transmission path, and the communication device requesting the transmission right sends the transmission right request signal. a delay element that transmits the received signal with a time delay of at least approximately 1 bit; and an output of the delay element to its own transmission output; Each communication device is provided with a switching device that switches to connect to the other transmission path, and compares the received priority in response to reception of the transmission right request signal with its own transmission right request priority, and A transmission right characterized in that when the priority is high, the switching device is controlled to transmit a code indicating its own priority instead of the received code indicating the priority, and the transmission right thereafter performs the transmission from itself. Request signal transmission method.