JPS63229914A - Level converting circuit - Google Patents

Abstract

PURPOSE:To convert the logic level signal of a positive ECL or CML to the logic level signal of TTL only with a positive single voltage source by applying conduction control to bipolar transistors connected in totempole shape between a positive voltage source and a ground potential. CONSTITUTION:In giving a high level ECL logic level signal to an input terminal A and a low level signal opposite to the said signal level to an input terminal, the inverse of A, an NPN transistor (TR) Q6 is conductive and an NPN TR Q7 is nonconductive. The collector potential of an NPN TR Q19 is clamped by a clamping circuit provided on the NPN TR Q19 and NPN TRs Q21, Q16 are nonconductive. The the NPN TR Q15 is conductive, the potential at an output terminal F is the subtraction of the base potential of the VBE of the NPN TR Q15 and the VBE of the NPN TR Q17 from the base potential of the NPN TR Q15 to obtain a TTL logic level signal.

Description

[Detailed description of the invention] [Object of the invention] (Industrial application field) This invention
TTL (T
transistor T transistor
The present invention relates to a level conversion circuit that converts a logic level signal into a logic level signal (Logic).

(Prior Art) As a level conversion circuit for converting an ECL logic level signal to a TTL logic level signal, there is one shown in FIG. 3, for example. This is G, literature FD, △, Ho
Des, et al.; ``Analysis and Design of Digital Integrated Circuits (A
Analysis and analysis of
D 1g1tal Integrated C1r
cuit)”, 7th edition.

It is described in Chapter 7, ・P, P, 294°.

This level conversion circuit uses a voltage source Vc of +5.0 (V).
c,! Knee 5.2 (V) Two positive and negative voltage sources with chisel pressure 'ffAVEE are used, and input terminals A and B power\
Conduction is controlled by a negative ECL logic level signal given from NPN bipolar transistors (hereinafter referred to as rNPNJ) Ql and Q2 connected in parallel, and high and low levels of signals given to input terminals A and B. N is in a conductive state due to the negative comparison voltage VR that determines
NPNQ4, which has a differential pair configured with PNQ3, is connected in a totem pole shape, and the connection point is the output terminal F.
It has an output stage constituted by ゜Q5.

In such a configuration, NPNQl, Q2 .
The current flowing through the emitter terminal of Q3 is controlled to cause the NPN Q4 to Q5 forming the output stage to perform a switching operation.

As a result, the logical sum output of the signals applied to input terminals A and B is converted to a TTL logic level and output from output terminal F. Moreover, in this level conversion circuit, NP
If NQ2 is removed, the ECL logic level signal applied to input terminal A is converted to TTL logic level and output from output terminal F.

(Problem to be solved by the invention) A digital signal obtained by A/D converting an analog signal in a high-speed A/D converter (sampling frequency of about 3OMH2) that is currently being used for digital signals, etc. There is a demand for processing by a processor with a 0MO8 configuration. In such a case, the internal operation of the A/D converter uses a positive voltage source to convert the output signal from the load of the differential pair to 1 le 7 cML (Current Mod
A positive voltage source is used to obtain an output signal from an emitter follower circuit connected to the above CML.The output level is TT.
It is most efficient to use the L logic level or the 0MO8 logic level.

Therefore, in the circuit configuration shown in FIG.
．． O(V) -5,2(V) (7)2tsu17) Since it requires a voltage source, it is usually used in TTL or 0MO8 configuration circuits that operate with a single +5.0 (V, ) power supply. The problem was that I couldn't do it.

Furthermore, the circuit configuration shown in FIG. 3 cannot be operated for positive input signals;
This caused the problem that it was not compatible with seudo E CL or plus CML.

Therefore, this invention was made in view of the above, and its purpose is to generate pseudo E CL or positive CML using only a single positive voltage source.
An object of the present invention is to provide a level conversion circuit that converts a TTL logic level signal into a TTL logic level signal.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a differential input with a positive ECL logic level or CML logic level applied as a voltage level to each input terminal. signal,
A voltage-current conversion circuit extracts the collector current of a PNP-type bipolar transistor according to each signal, a load circuit that serves as a load for this voltage-current conversion circuit, and a current path flowing from a constant current source into one of the PNP-type bipolar transistors. An output circuit comprising a circuit selected by the collector current of the transistor, and a bipolar transistor connected in a totem pole shape between a positive voltage source and ground potential with the connection point as an output terminal, and whose conduction is controlled according to the current path. It consists of

(Function) In this level conversion circuit, a differential input signal of ECL logic level or CML logic level given as a positive voltage level is converted into a current corresponding to each input signal, and an output circuit is output according to this current. The bipolar transistors constituting the circuit are operated to switch, and an input signal at a positive ECL logic level or CML logic level is converted into a signal at a TTL logic level.

(Example) The present invention will be described in detail below using the drawings.

FIG. 1 is a circuit diagram showing the configuration of a level conversion circuit according to an embodiment of the present invention. The level conversion circuit shown in the figure is
+5.0 (V) cD mono-M m V ccwo,
A positive ECL logic level signal applied to input terminal A is converted into a TTL logic level signal and output from output terminal F.

In Figure 1, an NPNQ6 whose base terminal receives a signal applied to input terminal A, and an NPNQ7 whose base terminal receives a signal of a level opposite to that of the signal applied to input terminal A, which is applied to input terminal A. A pair is configured, and this differential pair and a PNP type bipolar transistor (rPN
(I call it PJ) Q8. Emitter terminal of Q9 and voltage source Vcc
The resistors R1 and R2 connected between the two constitute a Hall Derad cascode circuit. This Hall Derad cascode circuit converts a differential input given as a voltage to input terminals A and A into a current corresponding to this differential input.

PNPQ8 of this Hall Dirad cascode circuit. Q9
whose base terminal is PNPQlo.

Qll is connected to the base terminal of PNPQ8゜Q9. Q
10. Ql 1 constitutes a current mirror circuit. PNPQlo constitutes a differential pair through resistors R3 and R4 whose collector terminals are connected in series.
6. It is connected to the base terminal and collector terminal of NPNQl2, which is a constant current source of Q7, and NPNQl3, which forms a current mirror circuit. A resistor R3 connected in series,
R4 has its connection point C connected to the base terminal of PNPQ14, and the potential of this connection point C is 3.95 (V) due to the collector current of NPNQl3 and resistors R3 and R4.
It is set to about.

NPNQl4 has its emitter terminal connected to the base terminal of NPNQl5. This NPNQl5 is a totem pole NPN between the voltage source Vcc and ground.
It is connected to Ql6 to form an output stage, and NPNQl
The collector terminal of No. 6 is used as the output terminal F. Also, NP
Between the emitter terminal of NQl5 and the output terminal F, an NPNQI 7 whose base terminal and collector terminal are connected and a resistor R8 are inserted. This NPNQI 7 acts as a diode, and when the output terminal F is at a low level, NPNQI7 acts as a diode.
This causes PNQl 5 to become non-conductive.

On the other hand, the PNP constituting the Holderad cascode circuit
Q8. Q9 has its collector terminal PNPQ8. NPNQl8 that constitutes a current mirror circuit that becomes the load of Q9
．． Ql9 is connected to the collector terminal of each PNP Q8. The current flowing out of Q9 is controlled by the level of the signal applied to input terminals A and A.

NPNQl9 of the current mirror circuit has N, , pN
A clamp circuit consisting of Q20 and resistor R5 is connected. This clamp circuit lowers the collector potential of NPNQl9 by 0.3 (V
). Also, NPNQl9
has its collector terminal connected to the base terminal of NPNQ21, and the emitter terminal of NPNQ21 is connected to the base terminal of NPNQ16 via resistor R7. These NPNQl6 and NPNQ21 include NPNQ
Similar to l9, NPNQ22 and resistor R7, NPNQ2
3 and a clamp circuit consisting of a resistor R6 is connected.

As explained above, this embodiment is constructed, and the operation of this embodiment will be explained next.

First, when a high-level soot ECL logic level signal is applied to input terminal A, and a low-level signal opposite to this signal is applied to input terminal A, NPNQ6 becomes conductive.
NPNQ7 becomes non-conductive, part of the current flowing through resistor R2 flows into NPNQ6, and the collector current of PNPQ9 decreases. At this time, the collector potential of NPNQl9 is changed by the clamp circuit provided in NPNQl9.
It is clamped to about 0.3 (V) to prevent NPNQl9 from becoming saturated.

As a result, NPNQ21 becomes non-conductive, and NPNQ21 becomes non-conductive.
Ql6 becomes non-conductive. Furthermore, as NPNQ21 becomes non-conductive, the emitter potential of PNPQ14 becomes lower than the base potential of PNPQ14 (approximately 3.95 (V) i
) NiPN PQ 14 Vs E (base-emitter voltage) is added to the potential, which is about 4.7 (V).

Therefore, NPNQ15 becomes conductive, and the output terminal F
The potential of NPNQ15 is from the base potential of NPNQ15 to
The VBE of NPNQ17 is subtracted from the VBE of NPNQ17.
It will be about 3.3 (V).

Therefore, the high level soot ECL logic level signal applied to the input terminal A is converted to the high level TTL logic level signal.

Next, when a low-level soot ECL logic level signal is applied to input terminal A, and a high-level signal opposite to this signal is applied to input terminal A, NPNQ6 becomes non-conductive, NPNQ7 becomes conductive, and the resistance A portion of the current flowing through R1 flows into NPNQ7, and the collector current of F'NPQ8 is significantly reduced compared to the collector current of PNPQ9.

Therefore, most of the collector current of PNPQ9 is NPN
It flows into the base terminal of Q21 and the collector terminal of NPNQ23, and NPNQ21 becomes conductive. As a result, the NPNQ16 becomes conductive, and if the potential across the resistor R7 is set to about 0.3 (V), the potential at the output terminal F becomes about 0.3 (V).

At this time, since NPNQ21 becomes conductive, the base potential of NPNQ15 drops to about 1.3 (V). Furthermore, the emitter potential of NPNQ17 is 0.3
It is V. Therefore, when NPNQ16 becomes conductive, NPNQ15 and Ql7 become non-conductive, so that no current flows from voltage @Vcc to ground.

Therefore, the low level soot ECL logic level signal applied to the input terminal is converted to the low level TTL logic level signal.

By the way, in the differential type Hall Derad cascode circuit described above, when converting the voltage applied to the input terminals A and A into a current, in order to perform this conversion operation at low current and high speed, PNPQ8°Q9. Q10 is V-PNP
(Vertical PNP) type transistor is required.

As explained above, in the above embodiment, +5.0
A single (V) power supply can be used to convert a soot ECL logic level signal to a TTL logic level signal at relatively low current and high speed.

As a result, the level conversion circuit of the above embodiment has a +5.0
It can be used for an A/D converter whose digital output signal is at TTL logic level with a single (V) power supply, and a prescaler whose output signal is at TTL logic level with a single +5.0 (V) power supply. It can be used by directly connecting to a CMOS processor.

In addition, in the above embodiment, NPNQ16°Ql9. Q
In order to avoid saturating 21, each NPN
is provided with a clamp circuit, but instead of providing a clamp circuit, as shown in FIG. Ql
9. Q21 is replaced by a Schottky barrier transistor Q24.
Q25. It may be composed of Q26. In addition, input terminal A,
Of course, the level of the signal applied to A may be a positive CML logic level.

[Effects of the Invention] As explained above, according to the present invention, differential input signals given as positive voltage levels are converted into currents corresponding to the respective input signals, and a positive voltage source is generated according to the currents. Since the conduction of the bipolar transistors connected in a totem pole configuration between the ground potential and the ground potential is controlled, a positive ECL or CML logic level signal can be converted to a TTL logic level using only a positive single voltage source. A level conversion circuit that converts the signal into a signal can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a level conversion circuit showing one embodiment of the present invention, FIG. 2 is a circuit diagram of a level conversion circuit showing another embodiment of the invention, and FIG. 3 is a configuration of a conventional level conversion circuit. FIG. (Explanation of symbols representing main parts of the diagram) Q6. Q7. Q
l5. Ql6...NPN type bipolar transistor Q8. Q9. Ql 1. Ql 4...PNP type bipolar transistor

Claims (1)

[Claims] A voltage current that extracts a differential input signal at a positive ECL logic level or CML logic level applied as a voltage level to each input terminal as a collector current of a PNP type bipolar transistor corresponding to each signal. A conversion circuit, a load circuit serving as a load of this voltage-current conversion circuit, and a current path flowing from a constant current source are connected to one of the P
A circuit that selects based on the collector current of an NP-type bipolar transistor, and a bipolar transistor that is connected in a totem pole configuration between a positive voltage source and a ground potential with the connection point as an output terminal, and whose conduction is controlled according to the current path. A level conversion circuit comprising: an output circuit comprising; and a level conversion circuit comprising: