JPS63229579A - Image coincidence detector - Google Patents

Abstract

PURPOSE:To enable fast image detection by simple constitution by detecting and storing the degree of the correlation of the binarization image data of a two-dimensional image with reference data and the position coordinates of its position. CONSTITUTION:The binarization image data of the two-dimensional image is outputted by an image data output circuit C1. The output image data is compared with the reference data outputted by a reference data output circuit C3 and a coincident bit detecting circuit C4 detects the number of coincident bits between both data. A coincident bit measuring circuit C5 measures the number of detected coincident bits and at least the maximum value among the number of coincident bits on respective scanning lines is stored in a coincidence position storage circuit C6 together with the coordinates of its position outputted by the coordinate output circuit C2. Therefore, at least the maximum value of the correlation of the binarization image data with the reference data and the position coordinates of its position are detected and stored.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an image-number construction device, and more particularly to an image-number construction device for detecting matching of images in two-dimensional images. .

[Prior Art] Various detection devices have been proposed for detecting specific patterns in two-dimensional images for image processing. In such devices, a two-dimensional image captured by an imaging means such as a television camera is binarized and stored in an image memo or the like.
This data is read out and a location matching a reference image of a specific pattern is searched. That is, the detection device is configured as an arithmetic and logic operation circuit, and software repeatedly compares this data stored in the image memory with the data of the reference image to search for matching patterns.

[Problems to be Solved by the Invention] However, in these conventional image detection devices, since the amount of image information is large, it is difficult to perform a simple process of sequentially reading out the data from the image memory and comparing it with reference data. The problem was that it had to be repeated many times. For example, if a two-dimensional image has a size of 512 x 495 dots, there are about 250,000 pixels, so if you try to search for the part closest to the reference data of about 100 dots in each horizontal scanning line, , data reading, comparison, and updating of maximum matching data must be repeated approximately 200,000 times. Therefore, if it were attempted to implement all of the pattern machining processing using software, the problem would arise that it would take an extremely long time since it is sequential processing.

As a result, not only is it impossible to perform image processing in real time, but also the number of man-hours required for the entire image processing increases, making it impractical for practical use.

The present invention has been made with the aim of solving the above problems and realizing high-speed image detection with a simple configuration.

The structure of the present invention that achieves the above object will be described below.

[Means for solving the problem] A book that compares binarized image data of a two-dimensional image with reference data and detects the positional coordinates of a part of the image data that most closely matches the reference data. As illustrated in FIG. 1, the image number construction device of the invention, in scanning one line of the two-dimensional image in a predetermined direction, sequentially parallelizes image data of continuous predetermined bits in the one scanning line. An image data output circuit C1 that outputs as data, a coordinate output circuit C2 that outputs position coordinates specifying the part of the image data to be read, and reference data that outputs reference data of a predetermined number of bits as parallel data. an output circuit C3; a matching bit detection circuit C4 that compares the output image data and the output reference data and detects matching bits; and a matching bit number measuring circuit C that measures the number of matching bits.
5, and a coincidence position storage circuit C6 that stores at least the maximum value of the measured number of coincidence bits in each line together with the position coordinates of the part of the image data that gives the maximum value.

Here, the image data output circuit C1 is a circuit that sequentially outputs binarized image data of continuous predetermined bits in one scanning line as parallel data, and is, for example, a converter that converts serial manual input into parallel data. , a gate array, a ROM, or the like. Scanning one line of a two-dimensional image in a predetermined direction may be along a normal horizontal scanning line, or if the data of the two-dimensional image is once stored in an image memory or the like, The address data for reading may be devised to read not only in the vertical direction but also in the diagonal direction.

The coordinate output circuit C2 outputs position coordinates that specify the part of the image data read out by the image data output circuit C1, and if it outputs the scanning position in response to scanning of a two-dimensional image, It can be configured in any way. For example, a counter that outputs the start address of the image data read out from the image data output means C1, R
OM.

It can be configured by a gate array, a programmable logic array, or the like.

The reference data output means C3 is a circuit that outputs reference data of a predetermined number of bits as parallel data, for example, a DIP switch of a predetermined number of bits, RO
M, a gate array, a latch, or the like.

The matching bit detection circuit C4 is the image data output circuit C1.
This circuit compares the image data outputted by the reference data output circuit C3 with the reference data outputted by the reference data output circuit C3 and detects matching bits, and the circuit calculates the exclusive OR of the image data and the reference data manually. It can be configured with a plurality of gates, a programmable logic array, etc.

The matching bit number measuring circuit C5 is the matching bit detecting circuit C.
This circuit inputs the detection result of 4 and detects the number of bits, and is configured as an addition circuit such as a full adder. If the output of the coincidence bit detection circuit C4 can be made into a time-series signal, it can also be realized by a counter or the like.

- The number position storage circuit C6 stores at least the maximum value in each line among the number of matching bits measured by the number of matching bits measuring circuit C5, and the positional coordinates (coordinate output) of the part of the image data that gives this maximum value. (given by circuit C2), and is provided integrally or separately with means for extracting at least the maximum value in the line and means for storing or recording the value and coordinates. It is. The means for extracting the maximum value is, for example, a latch that holds the previous maximum value, a magnitude comparator that compares the output of this latch with the current number of matching bits, and a new latch based on the judgment result of the comparator. A configuration consisting of a circuit for writing data can be considered. Note that a certain lower limit value may be set for a maximum of one shift. Further, the means for storing or recording the maximum value and coordinates may be, for example, a volatile or nonvolatile RAM, a magnetic recording means, an optical memory, or a means for outputting and recording on paper or a display.

[Operation] The image coincidence detection device of the present invention having the above-mentioned configuration distinguishes the binarized image data of the two-dimensional image output by the image data output circuit C1 from the reference data output from the reference data output circuit C3. The data are compared, and the number of matching bits of both data is detected by the matching bit detection circuit C4. The number of detected matching bits is further calculated by matching bit measuring circuit C5.
At least the maximum number of matching bits in each scanning line is stored in the minus number position storage means C6 together with the coordinates of that position output by the coordinate output circuit C2.

Therefore, the image coincidence detection device of the present invention detects and stores the degree of correlation with the reference data (at least the above-mentioned maximum value) and the position coordinates of this part from among the binarized image data of the two-dimensional image. .

[Embodiments] In order to further clarify the configuration and operation of the present invention described above, preferred embodiments of the image matching detection device of the present invention will be described below. FIG. 2 is a schematic configuration diagram of this image matching detection device.

As shown in the figure, this image detection device manually receives a signal from a television camera 1 as an imaging means, searches for a region in the captured image that has a good correlation with a reference pattern, (also referred to as coordinates) and the degree of correlation are displayed and output on the terminal 2.

Inside it, a synchronization separation circuit 3, an image data extraction circuit 5
, a binarization circuit 6, a vertical coordinate counter 7, a horizontal coordinate counter 8, a correlator 10, a latch 12, a comparator 15, a correlation data memory 1B, and a logic operation circuit 20.

The television camera 1 uses a solid-state image sensor such as a CCD, and has 512 horizontal dots per frame.
It has a resolution of 495 lines in the vertical direction. The image signal from the television camera 1 is first input manually to a synchronization separation circuit 3 and an image data extraction circuit 5.

The image data extraction circuit 5 is a circuit that extracts image data from a manually inputted image signal, and is well known as an essential circuit for television receivers, so a description of its internal configuration will be omitted. The image data extraction circuit 5 extracts 5 -horizontal scanning lines.
The data is separated and extracted into 12 dots, and an analog signal corresponding to the density of each dot is output to the binarization circuit 6. The binarization circuit 6 compares this analog signal containing density information with a predetermined darkness value and converts it into a binarized signal. In this embodiment, the darkness value for binarization is a preset value, but the binarization may be performed using the optimum darkness value for each sampling area. The output of this binarization circuit 6 is sent as image data to a serial input terminal Sin of an image data S/P converter 22, which will be described later, in the correlator 10.
It is connected to the. Further, the image data extraction circuit 5 includes 5
One pulse signal for each data of 12 dots is output to the count input terminal Cin of the horizontal coordinate counter 8 and the clock terminal CLK of the image data S/P converter 22.

The synchronization separation circuit 3 separates a vertical synchronization signal (image start signal) and a horizontal synchronization signal included in the image signal from the image data, and since the configuration of this circuit is well known, a description thereof will be omitted. An image start signal is sent from the synchronization separation circuit 3 to the reset terminal RESE of the vertical coordinate counter 7.
On the other hand, the horizontal comrade signal is output to the count input terminal Cin of the vertical coordinate carantuff, the reset terminal RESET of the horizontal coordinate counter 8, and the reset terminal RE of the latch 12.
It is output to SET.

Therefore, the vertical coordinate counter 7 is reset by the image start signal output from the same gate separation circuit 3 and starts counting, and is incremented by 495 per frame by the horizontal synchronization signal output from the synchronization separation circuit 3. On the other hand, the horizontal coordinate counter 8 is reset by the horizontal synchronization signal output from the synchronization separation circuit 3 and starts counting, and is incremented by 512 in one horizontal scan by the pulse signal output from the image data extraction circuit 5. .

The output of this vertical coordinate carantuff is memory 1 for correlation data.
It is manually operated as an address AD on the day of the day. On the other hand, the count output of the horizontal coordinate counter 8 is stored as coordinate data DX in the lower 9 bits of one day's data in the memory for correlation data. This memory for correlation data is configured as a rewritable dual-port memory, and the upper 8 bits of the data input are the output of the correlation data OR and the input output data Dout. The common bus of the logical operation circuit 20 is connected to the other address Ad. Therefore, in the correlation data memory 1st, the output of the vertical coordinate carantuff, that is, the address corresponding to the designation of the line of the two-dimensional image, the coordinate data DX, which is the output of the horizontal coordinate counter, and the correlation data, which is the output of the latch 12. Data DR is written. The horizontal coordinate counter 8 is provided with an output that becomes active high when the count value exceeds 128, and this output is manually input to the latch enable terminal LE of the latch 12.

Next, the internal configuration and function of the correlator 10 will be explained. The correlator 10, as shown in FIG.
/P converter 22. Reference data S/P converter 24. Mask data S/P converter 26, 128 exclusive OR gates (gates for - number configuration) ENOR1 to ENOR12
B, 128 AND gates AND1 to AND12
8. Consists of 16 counters PLAI to PLA16 and an adder 27.

The image data S/P converter 22 sequentially converts the image data, which is a serial signal output from the binarization circuit 6, into 128-bit parallel data and outputs it.
It is configured as a 2B phase shift register. Since the clock terminal CLK of the image data S/P converter 22 is manually supplied with a pulse signal which is the output of the image data extraction circuit 5, the image data is In synchronization with the horizontal scanning of the two-dimensional image by the television camera 1, 128 dots out of the 512 dots of image data appear on the parallel output of the S/P converter 22, shifted by -dots.

The reference data S/P converter 24 converts the reference data outputted as a serial signal from the logic operation circuit 20 into 128-bit parallel data, and is configured almost similarly to the image data S/P converter 22. ing. Reference data is written into the reference data S/P converter 24 by the logical operation circuit 20, and when the writing is completed, 128-bit reference data is outputted to its parallel output and held as is.

The 128-bit parallel outputs of both converters 22 and 24 described above are ENORl to ENOR
12.8 performs mutual exclusive OR and outputs the inverted value.

That is, the nth bit of the image data S/P converter 22 (n=
1.2-. 12B) matches the n-th bit of the reference data S/P converter 24, -Number composition game)ENOR
The output of n becomes the value 1 (high level).

The outputs of these negative number generation games ENORI to 128 are connected to one input terminal of AND gates ANDI to 128. A mask data S/P converter 2 configured in the same manner as the reference data S/P converter 24 is connected to the other input terminal of the ANDI to 128.
6 parallel outputs are connected. Mask data S
Mask data is transferred from the logic operation circuit 20 to the /P converter 26, and for bits whose value is 0,
The output from ANDI to 12th is masked and forced to the value 0 (low level). anime)
ANDI or 12th output is 8 tree count machine PL
It is powered by AI or 16 people.

Counters PLAI to 16 are configured by a programmable logic array, and count how many bits are at a high level (fil) among the eight inputs,
Output as 4-bit data. A total of 64 signal lines in 16 sets from the 16 counters PLAI to 16 are manually input to the adder 27.

The adder 27 adds 16 data of 4 bits each to produce an 8-bit output, and is constituted by a programmable logic array.

Further, the internal logic of the adder 27 is configured not to output data if the data after addition is less than or equal to the value 64. Therefore, the adder 27 outputs data when there are 64 or more matching bits, and outputs the value 128 when all bits match.

The output of the adder 27 is connected to one data input A of the comparator 15 together with the data output of the latch 12 described above. The output Q of the latch 12 is input as correlation data DR to the upper 8 bits of the correlation data memory for one day, and is also connected to the other data input B of the comparator 15.

As a result, in the comparator 15, the output of the adder 27 and the output of the latch 12 are closely compared, and when the output of the adder 27 becomes larger, the comparison output A>B becomes active high. . Since the comparison output A>B is connected to the enable terminal EN of the latch 12, the output of the adder 27 has already been set in the latch 12 (when it is larger than
Data output from the adder 27 is newly written into the latch 12, and this value is stored as correlation data DR in the correlation data memory 1st.

In addition, another latch enable terminal L of the latch 12
Since a signal indicating that the count value of the number of dots in the - line has become 128 or more is connected to E from the horizontal coordinate counter 8, 1 after the horizontal synchronization signal is detected.
The output data of the adder 27 is not falsified until 28 dots are counted.

Next, we will discuss the configuration of the logical operation circuit 20 which accesses the correlation data memory 1 day through its dual ports, and accesses the reference data S/P converter 24 and mask data S/P converter 26 by serial signals. I will explain its function. The logic operation circuit 20 includes a well-known CPU 31. R
OM32. RAM33. Serial I10 boat (hereinafter referred to as S
(referred to as IO) 34 and a human output boat 35 are interconnected by a common bus 36. CPU31
reads the reference data, etc. to be searched from the keyboard of the terminal device 2 connected via the input/output boat 35, and also calculates the X coordinate of the part that most closely matches the reference data within each horizontal scanning line. and the degree of matching are displayed on the display of the terminal device 2. In addition, the CPU 31 has 5IO3
4 to both converters 24, 26.

Next, the processing performed by the image-number construction apparatus of this embodiment will be explained. FIG. 3 is a flowchart showing the processing performed by the logical operation circuit 20. As shown in the figure, after startup, the image matching detection device of this embodiment first executes step 100 of the correlation data display routine, performs a process of manually inputting reference data via the terminal s2, and further displays mask data in the same manner. manually from the terminal 2 (step 110).

The reference data, for example, as shown in FIG. 4, is selected as a representative value of the final matching pattern and is given as a dot configuration of the pattern in the - line. In this embodiment, the maximum length is 128 bits, but if necessary, the bit length inside the correlator 10 may be increased. The CPU 31 stores the input reference data in a predetermined area of the RAM 33 as data with a value of 1 for the part where the image exists and a value of 0 for the part where the image does not exist. After that, C.P.
U31 uses human-generated standard data and mask data as 5I.
034 to the respective converters 24, 26 (step 120).

As a result, the reference data S/P converter 24. Reference data and mask data are set in the mask data S/P converter 26, and as the two-dimensional image captured by the television camera 1 is scanned, detection and counting of matching bits between the image data and the reference data is started. .

The number of matching bits is measured as follows.

Incidentally, FIG. 5 is an explanatory diagram showing the state of this detection.

(1) When scanning of the horizontal scanning line is started, the vertical coordinate counter 7 is incremented by 1, and the horizontal coordinate counter 8 and latch 12 are reset.

(2) The image data extracted by the image data extraction circuit 5 and binarized by the binarization circuit 6 is inputted line by line to the image data S/P converter 22 of the correlator 10. The above-mentioned correlator 10 detects the number of matching bits between the image data and the reference data within the range masked by the mask data, and applies this matching data (see FIG. 5) to the adder 27 of the correlator 10. Output from.

(3) The maximum value of the matching data outputted by the adder 27 is set in the latch 12 as correlation data DR,
Together with the count value of the horizontal coordinate counter 8 at that time (coordinate data DX), it is stored in the correlation data memory for one day. The stored address is the count value of the vertical coordinate counter 7, ie, the address corresponding to the number of the vertical line of the two-dimensional image.

(4) The above-described processing is repeated 495 times until the end of the two-dimensional image. During this time, the logic operation circuit 20
is not equally involved in the processing, and waits until the completion of the -number output (step 130 in FIG. 3).

Thereafter, the logical operation circuit 20 reads out the correlation data DR and the corresponding coordinate data DX from the correlation data memory 1 (step 140), and displays them on the display of the terminal 2 (step 140).

Through the above processing, the coordinate data DX of the part showing the best correlation with the reference data in one line of the two-dimensional image (however, in this example, the part showing the correlation of 64 bits or more) and the correlation indicating the degree of correlation are obtained. Data DR is terminal 2
displayed above. Therefore, in an extremely short time required to scan one frame of a two-dimensional image, a portion showing a good correlation with the reference data determined corresponding to the reference pattern can be detected from the two-dimensional image. As a result, subsequent image processing can be performed mainly on parts that show good correlation, and pattern recognition can be performed extremely easily and in a short time.

Furthermore, since the image matching detection device of this embodiment has locally optimized hardware, the configuration is extremely simple while achieving high speed.

In this example, the processing after image matching detection is not particularly explained, but it is used for positioning machine tools, recognizing parts, etc.
If applied to selection, etc., it will become possible to search for patterns in real time, which was extremely difficult in the past, thereby speeding up work, and the ripple effects of this image matching detection device will be extremely large.

Although one embodiment of the present invention has been described above, the present invention is not equally limited to such an embodiment. It goes without saying that the present invention can be implemented in various ways without departing from the spirit of the present invention, such as a configuration in which a tilted pattern is detected by counting matching bits while rotating the image data (method of rotating image data).

As described in detail above, according to the image matching detection device of the present invention, although the device and configuration are simple, it is possible to determine the positional coordinates of a region that closely matches the reference data in each line of a two-dimensional image. This provides an excellent effect in that the number of matching bits can be detected and stored at extremely high speed. As a result,
By using reference data that suitably represents the characteristics of an image, the image can be processed extremely quickly, and the workability of image recognition can be significantly improved. In addition, since the equipment and configuration do not become unnecessarily complicated, manufacturing man-hours and costs can be reduced, and reliability and
It is possible to improve maintainability.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the basic configuration of the present invention, FIG. 2 is a schematic configuration diagram of an image matching detection device as an embodiment of the present invention, and FIG. 3 is a logic operation circuit 2 in the device of the embodiment.
FIG. 4 is an explanatory diagram showing an example of selection of reference data for pattern matching, and FIG. 5 is an explanatory diagram illustrating the process until correlation data is obtained. be. 1 ... Television camera 2 ... Terminal 3 ... Synchronization separation circuit 5 ... Image data extraction circuit 6 ... Binarization circuit 7 ... Vertical coordinate counter 8 ... Horizontal coordinate counter 10 ... Correlator 12 ... Latch 15 ... Comparator 1 day ... Correlation data memory 20 ... Logical operation circuit 22 ... Image data S/P converter 24 ...
Reference data S/P converter 26...Mask data S
/P converter 27 ... Adder ANDI to AND 128 ... -AND gate ENOR1 to 128 ... Exclusive OR gate (gate for - number construction)

Claims (1)

[Claims] An image matching detection device that compares binarized image data of a two-dimensional image with reference data and detects the positional coordinates of a part of the image data that most closely matches the reference data. an image data output circuit that sequentially outputs image data of consecutive predetermined bits in the one scanning line as parallel data when scanning one line in a predetermined direction of the two-dimensional image; a coordinate output circuit that outputs position coordinates for specifying a body part; a reference data output circuit that outputs reference data of a predetermined number of bits as parallel data; and the output image data and the output reference data. a matching bit detection circuit that compares and detects matching bits; a matching bit number measuring circuit that measures the number of matching bits; and a matching bit number measuring circuit that measures the number of matching bits in each line. , and a matching position storage circuit that stores the positional coordinates of the portion of the image data giving the maximum value.