JPS63228676A - Manufacture of thin film semiconductor device - Google Patents
Manufacture of thin film semiconductor deviceInfo
- Publication number
- JPS63228676A JPS63228676A JP62061193A JP6119387A JPS63228676A JP S63228676 A JPS63228676 A JP S63228676A JP 62061193 A JP62061193 A JP 62061193A JP 6119387 A JP6119387 A JP 6119387A JP S63228676 A JPS63228676 A JP S63228676A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- substrate
- semiconductor device
- amorphous silicon
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000010409 thin film Substances 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 26
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 17
- 239000010408 film Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 238000000354 decomposition reaction Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000004804 winding Methods 0.000 abstract description 4
- 238000005513 bias potential Methods 0.000 abstract description 3
- 238000009751 slip forming Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 25
- 239000007789 gas Substances 0.000 description 6
- 230000002411 adverse Effects 0.000 description 5
- 238000010924 continuous production Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229910001256 stainless steel alloy Inorganic materials 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
く技術分野〉
本発明は化学的気相分解によるプラズマ雰囲気中で搬送
される基板上に、単層または複数層の薄膜半導体層を成
膜してなる薄膜半導体装置の製造方法に関し、特に非晶
質シリコン太陽電池の製造に好適な薄膜半導体装置の製
造方法に関する。[Detailed Description of the Invention] Technical Field> The present invention relates to a thin film semiconductor device in which a single layer or multiple thin film semiconductor layers are formed on a substrate that is transported in a plasma atmosphere by chemical vapor phase decomposition. The present invention relates to a manufacturing method, and particularly to a manufacturing method of a thin film semiconductor device suitable for manufacturing an amorphous silicon solar cell.
〈従来技術〉
化学的気相分解(以降CVDと記す)によるプラズマ雰
囲気中で基板上に単層または複数層の薄膜半導体層を成
膜して半導体装置を製造する方法は、例えばシラン(S
t H4)ガスを放電分解して非晶質シリコン太陽電池
を製造する方法として、広〈実施されている公知の技術
である。かかる製造方法において、効率よく薄膜半導体
層を成膜する、即ち大量生産に適した製造方法の一つと
して、基板を連続的に搬送させながらCvDプラズマ放
電雰囲気中を通過させる方法が公知である。<Prior art> A method of manufacturing a semiconductor device by forming a single layer or multiple thin film semiconductor layers on a substrate in a plasma atmosphere by chemical vapor phase decomposition (hereinafter referred to as CVD) uses, for example, silane (S).
t H4) This is a well-known technique that is widely practiced as a method for manufacturing an amorphous silicon solar cell by discharging and decomposing gas. Among such manufacturing methods, a method of continuously transporting a substrate through a CvD plasma discharge atmosphere is known as one of the manufacturing methods suitable for efficiently forming a thin film semiconductor layer, that is, suitable for mass production.
この方法は大別して次の2種類に分けられる。This method can be roughly divided into the following two types.
1つは、基板の仕込み室と取り出し室の間にプラズマ放
電を行なうための完全に分離・独立した単室、必要に応
じて複数室からなる反応室を設置し、枚葉の基板を移動
台車等に乗せて各室を順次移送させながら成膜を行なう
ロードロック方式である。One is to install a completely separate and independent single chamber for plasma discharge between the substrate loading chamber and the unloading chamber, and a reaction chamber consisting of multiple chambers as necessary, and a trolley for moving single substrates. This is a load-lock method in which film formation is performed while sequentially transporting the film from one chamber to another.
他の1つは、特開昭58−216475号公報、特開昭
59−34668号公報等の如く基板自体を長尺の巻き
物にして、巻出し室と巻取り室の間に、基板通路で連絡
した、単室、必要に応じて複数室からなる反応室を設置
し、連続的に搬送される薄膜状基板に成膜を行なうロー
ル・ツー・ロール方式である。Another method is to make the board itself into a long roll, such as in JP-A-58-216475 and JP-A-59-34668, and there is a board passage between the unwinding chamber and the winding chamber. This is a roll-to-roll method in which a single reaction chamber or multiple reaction chambers are installed as needed, and films are formed on thin film substrates that are continuously transported.
かかる製造方式で、更に生産効率を高めるために高速成
膜を行なう場合、従来技術においては、充分な原料ガス
を供給しながら放電電力を増加させてプラズマ雰囲気中
の活性種濃度を高める方法がとられてきた。しかしこの
ような方法では放電電力の増加とともにプラズマ雰囲気
中の荷電粒子の運動エネルギーも増大するため、成膜面
が荷電粒子の衝突で損傷する、云わゆるプラズマ損傷が
顕著になって半導体iJlの特性が損われ、半導体装置
としての特性に悪影響を及ぼす欠点があった。When performing high-speed film formation in order to further increase production efficiency using such a manufacturing method, the conventional technique is to increase the concentration of active species in the plasma atmosphere by increasing the discharge power while supplying sufficient raw material gas. I've been exposed to it. However, in such a method, as the discharge power increases, the kinetic energy of the charged particles in the plasma atmosphere also increases, so that so-called plasma damage, in which the film formation surface is damaged by collisions of charged particles, becomes noticeable and the characteristics of the semiconductor iJl are affected. There was a drawback that the characteristics of the semiconductor device were adversely affected.
基板上に半導体層が形成されており、更にこの上に別の
種類の半導体層を形成する場合、具体的には非晶質シリ
コン太陽電池の製造におけるp層又はn層を基板上に形
成後その上にi層を形成する場合には、この影響が顕著
であった。When a semiconductor layer is formed on a substrate and another type of semiconductor layer is formed on top of this, specifically, after forming a p layer or an n layer on the substrate in manufacturing an amorphous silicon solar cell. This effect was significant when an i-layer was formed thereon.
〈発明の目的〉
本発明は上記従来技術の欠点を解消し、半導体装置とし
ての特性に悪影響を及ぼすことなく放電電力を増加させ
て高速成膜ができる薄膜半導体装置の製造方法を第1の
目的とし、特に非晶質シリコン太陽電池の大量生産に適
した薄膜半導体装置の製造方法を第2の目的とする。<Objective of the Invention> The first object of the present invention is to provide a method for manufacturing a thin-film semiconductor device that eliminates the drawbacks of the above-mentioned conventional techniques and allows high-speed film formation by increasing discharge power without adversely affecting the characteristics of the semiconductor device. The second object of the present invention is to provide a method for manufacturing a thin film semiconductor device particularly suitable for mass production of amorphous silicon solar cells.
〈発明の構成〉 上述の目的は以下の本発明により達成される。<Structure of the invention> The above objects are achieved by the invention as follows.
すなわち、本発明は基板を移送しつつ化学的気相分解に
よるプラズマ雰囲気中で該基板上に所定の半導体層を形
成する薄膜半導体装置の製造方法において、対向した放
電電極の基板入側の所定範囲の中間に放電電極と平行に
多孔板からなる格子電極を少なくとも基板全巾以上に亘
って設け、該格子電極により半導体層形成開始時のプラ
ズマ衝撃を低下させて膜形成することを特徴とする薄膜
半導体装置製造方法である。That is, the present invention provides a method for manufacturing a thin film semiconductor device in which a predetermined semiconductor layer is formed on a substrate in a plasma atmosphere by chemical vapor phase decomposition while the substrate is being transferred. A thin film characterized in that a grid electrode made of a porous plate is provided between the discharge electrodes in parallel with the discharge electrode over at least the entire width of the substrate, and the film is formed by reducing plasma impact at the start of semiconductor layer formation by the grid electrode. This is a semiconductor device manufacturing method.
上述の本発明は以下のようにしてなされたものである。The above-mentioned present invention was made as follows.
すなわち、本発明者らは前述の特開昭59−34668
号公報開示のものと同様なj更続プラズマC■0装置で
非晶質シリコン太陽電池の連続大向生産について検討し
てきたが、生産性向上のため堆積速度を上げるために放
電電力を大きくするとその変換効率が下がる現象が観察
された。そして、その原因は真性非晶質シリコン層(i
層)の特性低下にあり、これはi層の形成初期の下層か
らの不純物混入に基づくもので、膜形成初期の下層のプ
ラズマ衝撃に基づくものであることを見出したそして、
この対策について種々検討の結果放電電極間の基板入側
のみに格子電極を設けることにより格子電極存在部及び
その近傍のみで効果的にプラズマエネルギーが低下し前
記プラズマ損傷が防止でき、且つ、格子電極部以外では
格子電極の影響を受けることなく高速膜形成ができるこ
とを見出し、なされたものである。That is, the present inventors disclosed the above-mentioned Japanese Patent Application Laid-Open No. 59-34668
Continuous Omukai production of amorphous silicon solar cells has been investigated using a continuous plasma C■0 apparatus similar to the one disclosed in the publication, but it has been found that increasing the discharge power to increase the deposition rate to improve productivity. A phenomenon in which the conversion efficiency decreased was observed. The cause of this is the intrinsic amorphous silicon layer (i
They found that this was due to the incorporation of impurities from the lower layer in the early stage of the formation of the i-layer, and that this was due to plasma bombardment of the lower layer in the early stage of film formation.
After various studies on this countermeasure, we found that by providing a grid electrode only on the substrate entry side between the discharge electrodes, the plasma energy can be effectively reduced only in the area where the grid electrode exists and its vicinity, and the plasma damage can be prevented. This discovery was made based on the discovery that high-speed film formation could be performed without being affected by the grid electrode in areas other than the lattice electrode.
以上の通り、本発明は非晶質シリコン太陽電池の連続製
造においてなされたものであるが、同様の薄膜半導体装
置の製造方法に広く適用できることは、その趣旨から明
らかである。As described above, although the present invention was made in the continuous production of amorphous silicon solar cells, it is clear from its purpose that it can be widely applied to similar methods of producing thin film semiconductor devices.
すなわち、上述したところより明らかな通り、本発明は
放電電力を増大させたときに生じる薄膜半導体装置の特
性に及ぼす悪影響は、主として半導体各層の界面に対す
るプラズマ損傷である事実に立脚している。従って本発
明は基板と半導体薄膜の界面及び導電形や構成元素の異
なる半導体薄膜同志の界面が高エネルギー粒子を含むプ
ラズマにさらされた場合にのみ薄膜半導体装置としての
特性に悪影響が現われ、一方、界面を離れた薄膜内部の
みが原料ガスの分解促進を目的とする程度の高エネルギ
ープラズマにざらされても半導体装置としての特性は顕
茗な悪影響を受けることがない半導体装置に広く適用で
きる。That is, as is clear from the above, the present invention is based on the fact that the adverse effect on the characteristics of a thin film semiconductor device that occurs when the discharge power is increased is mainly plasma damage to the interface between each semiconductor layer. Therefore, in the present invention, the characteristics of the thin film semiconductor device are adversely affected only when the interface between the substrate and the semiconductor thin film or the interface between semiconductor thin films of different conductivity types and constituent elements is exposed to plasma containing high-energy particles. Even if only the inside of the thin film away from the interface is exposed to high-energy plasma for the purpose of promoting decomposition of source gas, the characteristics of the semiconductor device will not be significantly adversely affected, and it can be widely applied to semiconductor devices.
又、本発明の格子電極は放電電極の基板入側のみに設け
る。その設ける領域は形成する半導体及び格子電極に印
加するバイアス電圧等に関係し、実験的に定める必要が
あるが膜形成速度を考慮すると基板入口から放電電極の
半分まで位の間で適宜選定するのが実用的である。格子
電極の形状は網状体、i状等多数の孔を全面に亘って有
する多孔板が使用される。その孔の大きさは、活性種の
通過を出来るだけ阻げない範囲でプラズマを閉じ込める
ことができる範囲で選定され、実際には実験的に定める
が網状の場合は50番メツシュ以下で選定するのが実用
的である。Further, the grid electrode of the present invention is provided only on the substrate entry side of the discharge electrode. The area to be provided needs to be determined experimentally, depending on the semiconductor to be formed and the bias voltage applied to the grid electrode, but considering the film formation rate, it should be selected appropriately between the substrate entrance and half of the discharge electrode. is practical. As for the shape of the grid electrode, a perforated plate having a large number of holes over the entire surface, such as a net-like shape or an i-like shape, is used. The size of the pores is selected within a range that can confine the plasma without blocking the passage of active species as much as possible.Actually, it is determined experimentally, but in the case of a mesh, it should be selected to be no larger than No. 50 mesh. is practical.
又、本発明は長尺基板上に必要な半導体層を連続的に順
次形成する場合に有利に適用できる。中でも基板上に既
に半導体層が形成され、その上にこれと別種の半導体層
を形成する場合に効果的である。特に非晶質シリコン半
導体層の形成、中でも前述の通り大きな問題を有する非
晶質シリコン太陽電池の連続製造におけるiliの形成
において大きな効果を奏する。Further, the present invention can be advantageously applied to the case where necessary semiconductor layers are continuously and sequentially formed on a long substrate. This method is especially effective when a semiconductor layer has already been formed on the substrate and a different type of semiconductor layer is to be formed thereon. It is particularly effective in forming an amorphous silicon semiconductor layer, especially in forming ili in the continuous production of amorphous silicon solar cells, which has a major problem as described above.
以下、本発明の詳細を非晶質シリコン太陽電池の連続製
造を例に説明する。Hereinafter, the details of the present invention will be explained using continuous production of amorphous silicon solar cells as an example.
〈実施例〉
第1図は上記実施例の非晶質シリコン太陽電池の連続製
造装置の構成図である。<Example> FIG. 1 is a block diagram of a continuous manufacturing apparatus for amorphous silicon solar cells according to the above example.
その基本構成は前述の特開昭58−216475号公報
。Its basic structure is disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 58-216475.
特開昭59−34668号公報開示のものと同じで、p
型。Same as that disclosed in Japanese Patent Application Laid-open No. 59-34668, p.
Type.
i型及びn型の各非晶質シリコン層を形成するCVDプ
ラズマ放電の各反応室1,2.3及び巻出室16並びに
巻取室17をガス隔離のための緩衝室18で連結し、巻
出しロール14から巻取りロール15へ基板13をロー
ル・ツー・ロール方式で移送しつつp、i、nの3層を
連続形成する構成となっている。なお、図の4〜9は放
電電極で、図の10は各放電電極に高周波電力を供給す
る高周波電源である。The reaction chambers 1, 2.3 of CVD plasma discharge forming each of the i-type and n-type amorphous silicon layers, the unwinding chamber 16, and the winding chamber 17 are connected by a buffer chamber 18 for gas isolation, The substrate 13 is transferred from the unwind roll 14 to the take-up roll 15 in a roll-to-roll manner, and three layers p, i, and n are successively formed. Note that 4 to 9 in the figure are discharge electrodes, and 10 in the figure is a high frequency power source that supplies high frequency power to each discharge electrode.
かかる反応室分離型ロール・ツー・ロール方式のCVD
プラズマ放電装置で、SiH4ガス等周知の所定の原料
ガスを各反応室1.2.3に供給してロール状に巻き上
げた長尺基板上にp、i。Such reaction chamber separated roll-to-roll type CVD
Using a plasma discharge device, a well-known predetermined raw material gas such as SiH4 gas is supplied to each reaction chamber 1.2.3, and p and i are applied onto a long substrate rolled up into a roll.
n形非晶質シリコン膜を順次積層して太陽電池を形成し
た。本例では前述の通り太陽電池の特性を左右するi正
非晶質シリコン層を形成する反応室2において、対向す
る放電電極6.7の中間に格子電極11を設置した。該
格子電極11は可撓性の長尺の基板13の進行方向に沿
って、放電電極6,7の前半1/3を覆うように設けで
ある。該格子電極11には電源12より所定バイアス電
位を印加するようになっている。格子電極11の材料は
ステンレス合金の金網とし、その網の粗さはプラズマを
閏じ込めるのに充分細かく、かつ、活性種の通過を阻げ
ない程度に粗いもの、本例では20番メツシュの網目と
した。A solar cell was formed by sequentially stacking n-type amorphous silicon films. In this example, as described above, in the reaction chamber 2 in which the i-positive amorphous silicon layer which influences the characteristics of the solar cell is formed, the grid electrode 11 was installed between the opposing discharge electrodes 6 and 7. The grid electrode 11 is provided along the traveling direction of the flexible elongated substrate 13 so as to cover the first third of the discharge electrodes 6 and 7. A predetermined bias potential is applied to the grid electrode 11 from a power source 12. The material of the grid electrode 11 is a stainless steel wire mesh, and the roughness of the mesh is fine enough to trap the plasma, but coarse enough not to block the passage of active species. It was meshed.
基板13として、本例では厚さ100μmのポリエチレ
ンテレフタレートのフィルム上に3000人のアルミ金
属と50人のステンレス合金を順次積層して用い、前述
の特開昭59−34668号公報同様にしp。As the substrate 13, in this example, 3000 aluminum metal and 50 stainless steel alloy were sequentially laminated on a polyethylene terephthalate film having a thickness of 100 μm, and the same procedure was used as in the above-mentioned Japanese Patent Application Laid-Open No. 59-34668.
i、n形の非晶質シリコン層を一定性で連続成膜した。I, N type amorphous silicon layers were continuously formed with constant consistency.
pおよびn形の非晶質シリコン膜の厚さは200〜30
0人、i正非晶質シリコン層の厚さは5ooo人程度と
なるように、放電電力、基板搬送速度9反応ガス圧力を
制御した。電極11は基板13から25m離して設置さ
れ(放電電極間距離は50醜)、+200〜−200■
の間の適当な値に直流電圧が設定できる電源12により
バイアスされている。The thickness of p- and n-type amorphous silicon films is 200 to 30
The discharge power, substrate transfer speed, and reaction gas pressure were controlled so that the thickness of the i-positive amorphous silicon layer was approximately 5 mm. The electrode 11 is installed 25 m away from the substrate 13 (the distance between the discharge electrodes is 50 m), and the voltage is +200 to -200 cm.
The DC voltage is biased by a power supply 12 whose DC voltage can be set to an appropriate value between the two.
第2図に格子電極11に負のバイアス電位(−20■)
を印加し、放電電極6.7に印加する高周波電力を変え
てi正非晶質シリコン層を成膜した場合の、太陽電池特
性(変換効率)と放電電力の関係を実線Aで示した。当
然のことながら、放電電力の増加は第2図に同時に示し
たように堆積速度を上昇させ、高速成膜に対応している
。本発明による製造方法では、第2図の実線Aに示すご
とく、放電電力が増加しても太陽電池の特性の悪化はほ
とんど見られない。Figure 2 shows a negative bias potential (-20■) applied to the grid electrode 11.
A solid line A shows the relationship between the solar cell characteristics (conversion efficiency) and the discharge power when the i-positive amorphous silicon layer was formed by changing the high-frequency power applied to the discharge electrode 6.7. Naturally, an increase in discharge power increases the deposition rate as shown in FIG. 2, which corresponds to high-speed film formation. In the manufacturing method according to the present invention, as shown by the solid line A in FIG. 2, there is almost no deterioration in the characteristics of the solar cell even when the discharge power increases.
一方、格子電極11を除いた上述の装置で全く同様にし
て形成した太陽電池の特性は、第2図に破線Bで示した
ごとく、放電電力の増加に伴って太陽電池特性が低下し
た。On the other hand, the characteristics of a solar cell formed in exactly the same manner using the above-mentioned apparatus except for the grid electrode 11 deteriorated as the discharge power increased, as shown by the broken line B in FIG.
また、格子電極11を対向する放電電極6.7の基板入
側のみならず全面を覆うように設けた場合には、第2図
に一点鎖線Cで示したごとく、放電電力を増加しても堆
積速度が上昇せず、高速成膜が達成できなかった。In addition, when the grid electrode 11 is provided so as to cover not only the substrate entrance side but also the entire surface of the opposing discharge electrode 6.7, as shown by the dashed line C in FIG. 2, even if the discharge power is increased, The deposition rate did not increase, and high-speed film formation could not be achieved.
第1図は本発明の実施例に係わる非晶質シリコン太陽電
池の連続製造装置の構成の説明図、第2図は実施例及び
比較例の結果を示すグラフである。
1.2,3 : CVD反応’!
4.5.6,7.8.9 :放電電極
11:格子電極 13:基板 18:緩′fJ
至特許出願人 帝 人 株 式 会 社
欣電電力 (W)
第21犯FIG. 1 is an explanatory diagram of the configuration of a continuous manufacturing apparatus for amorphous silicon solar cells according to an example of the present invention, and FIG. 2 is a graph showing the results of the example and comparative example. 1.2,3: CVD reaction'! 4.5.6, 7.8.9: Discharge electrode 11: Grid electrode 13: Substrate 18: Loose 'fJ
Patent applicant: Teijin Co., Ltd. Shinden Power Co., Ltd. (W) 21st offender
Claims (1)
囲気中で該基板上に所定の半導体層を形成する薄膜半導
体装置の製造方法において、対向した放電電極の基板入
側の所定範囲の中間に放電電極と平行に多孔板からなる
格子電極を少なくとも基板全巾以上に亘って設け、該格
子電極により半導体層形成開始時のプラズマ衝撃を低下
させて膜形成することを特徴とする薄膜半導体装置の製
造方法。 2、基板が長尺の可撓性基板からなり、ロール・ツー・
ロールで連続的に移送される特許請求の範囲第1項記載
の薄膜半導体装置の製造方法。 3、基板が形成しようとする半導体と異なる半導体層が
すでに積層されている基板である特許請求の範囲第1項
若しくは第2項記載の薄膜半導体装置の製造方法。 4、半導体層が非晶質シリコン半導体層である特許請求
の範囲第1項〜第3項記載のいずれかの薄膜半導体装置
の製造方法。 5、薄膜半導体装置は非晶質シリコン太陽電池であり、
積層する半導体層が非晶質シリコン太陽電池の真性半導
体層である特許請求の範囲第4項記載の薄膜半導体装置
の製造方法。 6、非晶質シリコン太陽電池は、その構成要素の半導体
層を形成するガス隔離された各反応室を貫通して長尺の
基板を連続的にロール・ツー・ロール方式で移送して製
造する特許請求の範囲第5項記載の薄膜半導体装置の製
造方法。[Claims] 1. In a method for manufacturing a thin film semiconductor device in which a predetermined semiconductor layer is formed on a substrate in a plasma atmosphere by chemical vapor decomposition while the substrate is being transferred, the substrate entrance side of the opposing discharge electrodes is provided. A lattice electrode made of a porous plate is provided in parallel with the discharge electrode in the middle of a predetermined range, and extends over at least the entire width of the substrate, and the lattice electrode reduces plasma impact at the start of semiconductor layer formation to form a film. A method for manufacturing a thin film semiconductor device. 2. The board is made of a long flexible board and can be rolled to
2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the thin film semiconductor device is continuously transported by rolls. 3. The method of manufacturing a thin film semiconductor device according to claim 1 or 2, wherein the substrate is a substrate on which a semiconductor layer different from that of the semiconductor to be formed has already been laminated. 4. The method for manufacturing a thin film semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer is an amorphous silicon semiconductor layer. 5. The thin film semiconductor device is an amorphous silicon solar cell,
5. The method of manufacturing a thin film semiconductor device according to claim 4, wherein the semiconductor layers to be laminated are intrinsic semiconductor layers of an amorphous silicon solar cell. 6. Amorphous silicon solar cells are manufactured by continuously transporting a long substrate in a roll-to-roll manner through gas-isolated reaction chambers that form the component semiconductor layers. A method for manufacturing a thin film semiconductor device according to claim 5.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62061193A JPS63228676A (en) | 1987-03-18 | 1987-03-18 | Manufacture of thin film semiconductor device |
US07/166,689 US4920917A (en) | 1987-03-18 | 1988-03-11 | Reactor for depositing a layer on a moving substrate |
DE3808974A DE3808974A1 (en) | 1987-03-18 | 1988-03-17 | ARRANGEMENT FOR DEPOSITING A MATERIAL LAYER ON A MOVING CARRIER |
FR8803589A FR2613535B1 (en) | 1987-03-18 | 1988-03-18 | REACTOR FOR LAYING A LAYER ON A MOBILE SUBSTRATE FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62061193A JPS63228676A (en) | 1987-03-18 | 1987-03-18 | Manufacture of thin film semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63228676A true JPS63228676A (en) | 1988-09-22 |
JPH0529151B2 JPH0529151B2 (en) | 1993-04-28 |
Family
ID=13164087
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62061193A Granted JPS63228676A (en) | 1987-03-18 | 1987-03-18 | Manufacture of thin film semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63228676A (en) |
-
1987
- 1987-03-18 JP JP62061193A patent/JPS63228676A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0529151B2 (en) | 1993-04-28 |
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