JPS63228339A - Testing system for instruction process device - Google Patents

Abstract

PURPOSE:To easily detect whether a fault is the fault of a firmware or that of a software and to remarkably shorten a time for restoring from the fault by providing a means for reading an operating state including the program in an instruction process device in a central processing unit. CONSTITUTION:The titled system has an instruction accumulation means 1 and it is constituted of the instruction process device 2 which actuates with the control of accumulated program and the central processing unit 3 which positions in the high rank of the instruction process device 2 and controls the instruction process device 1 by issuing instructions. By providing the operating state read means for reading the operating state including the processor in the instruction process device in the central processing unit 3, the central processing unit 3 can decide the normality of the program in the instruction process device 2 and the normality of a hardware. Thus, the time for restoring from the fault can be shortened because whether the fault of the instruction process device 2 is the fault of the hardware or the fault of the firmware can be quickly recognized.

Description

[Detailed Description of the Invention] [Summary] In an instruction processing device that uses a program test method and operates under stored program control, when the contents of the program are destroyed due to program runaway, etc., the program of the instruction processing device is By reading the area, abnormalities in the firmware and hardware inside the instruction processing unit can be immediately detected.

[Industrial application field]

The present invention relates to a test method for an instruction processing device under storage program control that operates under the control of a central processing unit in a data communication system, for example.

Generally, when the instruction processing unit under the central processing unit is of the stored program control type, the contents of the program may be destroyed due to the program in the instruction processing unit going out of control for some reason.

In this case, it is desired to quickly deal with failure recovery.

[Conventional technology]

Conventionally, in order to test the normality of an instruction processing device,
A higher-level central processing unit issues an instruction to execute a predetermined function, and the instruction processing unit that receives this instruction executes the instruction.The central processing unit recognizes the result and determines whether or not the above-mentioned predetermined function has been executed. They only conducted functional tests to make judgments.

[Problem that the invention seeks to solve]

According to the conventional function test described above, it is possible to detect a functional failure of the instruction processing device, but it is not possible to distinguish between a hardware failure and a firmware failure. For this reason, there is a problem in that failures cannot be dealt with promptly and a large amount of time is required for normal recovery.

[Means for solving problems]

FIG. 1 is a block diagram showing the principle of the present invention.

In FIG. 1, the system to which the present invention is applied has an instruction storage means 1, an instruction processing device 2 that operates under storage program control, and an instruction processing device 2 located above the instruction processing device 2 that issues instructions. It consists of a central processing bag W3 which controls the instruction processing device 1 in some cases.

According to the present invention, since the central processing unit 3 is provided with the operating state reading means 4 for reading the operating state including the program inside the instruction processing unit 2, the normality of the program inside the instruction processing unit 2 and the normality of the hardware can be confirmed. can be determined by the central processing unit 3.

[For production]

By reading the operating status of the instruction processing unit 2, including the program, the central processing unit 3 can quickly recognize whether a failure in the instruction processing unit 2 is a hardware failure or a firmware failure, reducing the time required for failure recovery. be done.

〔Example〕

FIG. 2 is a block diagram showing a system applied to an embodiment of the present invention.

In FIG. 2, a plurality of instruction processing units 1121-1, 21-2, . . . are connected to the central processing unit 20.

The central processing unit 20 includes a main memory (MM) 22, a control device (CG) 23, and an external interface section 24.

Each of the instruction processing devices includes an external interface section 25, a microprocessor unit (MPU) 26, a control memory (CM) 27, and an instruction memory (IM) 2.
8, a buffer memory (BFR) 29, and an LC controller (LCTL) 30.

A buffer memory (BFR) 29 and an LC controller (LCTL) 30 are connected to line controllers (1, C) 31-1, 31-2, . . . via respective buses. Line controller (LC) 31-1
, 31-2, . . . are each connected to a line.

FIG. 3 is a block diagram showing the detailed configuration of the instruction processing device 21-1.

In FIG. 3, parts that are the same as those in FIG. Instruction address register (IAR)
) 263, a constant register (CNST) 264, and an instruction address counter (rcR) 265.

In addition, the instruction memory (IM) 28 is a ROM.
It consists of an instruction register (IR) 281 and a RAM.
It is connected to the.

The accumulator register (AR) 261 is used as an accumulator inside the microprocessor unit (MPU) 26 during instruction processing.

The instruction address register (TAR) 263 stores a jump destination address when a jump instruction is executed.

A constant register (CNST) 264 is a register for storing a fixed address when a program is executed from a fixed address.

An instruction address counter (ICR) 265 specifies the next instruction address of a non-jump instruction.

The instruction register (IR) 281 stores instructions read from the instruction memory (rM) 28.

Control memory (CM) 27, buffer memory (BFR)
29 and the output of the instruction memory (IM) 28 are connected to the lower bit data bus (DBL) inside the instruction processing device.
211 and an upper pit data bus (DBU) 212. Microprocessor unit (MPU)
26 inputs and outputs, LC controller (L(:TL)
30 and the output of the instruction register (IR) 281 are connected to a lower pit data bus (DBL) 211.

In a system where multiple instruction processing units operate according to instructions from one central processing unit, if each detailed operation of the instruction processing units is all controlled by the central processing unit, the load on the central processing unit will be reduced. becomes excessive, and as a result, the processing capacity of the entire system decreases.

Therefore, by providing a microprocessor in the instruction processing unit and having each instruction processing unit perform storage program control,
The configuration shown in FIGS. 2 and 3 is generally employed. In the configurations shown in FIGS. 2 and 3, the central processing unit 2
Instruction processing devices 21-1, 21-
2, ... interprets and executes processing.

The instruction processing devices 2L1, 21-2, . . . have an instruction memory (IM) in order to execute the above processing.
The microprocessor unit l-(MPtl) 26 reads the program from the instruction memory (IM) 28 in response to an instruction from the central processing unit 20, and executes processing according to this program.

However, if there is a bug in the program of the central processing unit 20 or if there is a hardware failure in the instruction memory (IM) 28, etc., the instruction processing units 21-1, 21-2, . . . The program in the instruction processing device may be destroyed due to the program running out of control or performing an abnormal operation.

Conventionally, these abnormalities are notified to the central processing unit as a failure of the instruction processing unit, and the central processing unit only performs a functional test on the instruction processing unit, which determines whether the abnormality in the instruction processing unit is due to a hardware failure. It was not possible to determine whether this was due to a firmware failure.

According to the embodiment of the present invention, when the central processing unit 20 detects an abnormality in the instruction processing unit 21-1, the contents of the instruction memory (IM) 28 or the contents of the control memory (CM) 27 are transferred to the central processing unit. The program is read out to the main memory (MM) 22 in the processing unit 20, and the contents of successive programs are checked against each other, and the normality of instructions given from the central processing unit 20 and the normality of various data are checked.

There are the following two means for confirming the normality of the instruction processing unit read by the central processing unit 20.

■The correct data of the contents of the instruction memory (IM) 28 is transferred to the main memory (MM) 22 inside the central processing unit.
The content of the read program is prepared in advance and checked by comparing it with the correct answer data.

■Simulation data is prepared in advance in the main memory (MM) 22 inside the central processing unit, and the contents of the instruction memory (IM) 28 are stored in the main memory (MM) 22.
M) 22 and main memory (Ml'1) 22
The normality of the program in the instruction memory (IM) 28 is determined based on the results of the above simulation operation.

The above-mentioned check of the normality of the program is performed by means for instructing the address of the instruction memory (IM) 28 inside the instruction processing unit from the central processing unit 20, which did not exist in the past.
8 to data bus (DBL) 211 and (DBυ)
This was made possible by providing means 31 and 32 for outputting to 212.

To explain in more detail, in the embodiment of the present invention, addresses from address O to the final address of the instruction memory (IM) 2B are automatically generated according to instructions from the central processing unit 20, and instructions are transferred to the instruction memory (IM) by DMA transfer. IM) 28 is transferred to the central processing unit 20.

The program transfer procedure is described below.

(1) The central processing unit 20 detects an abnormality in the instruction processing unit 21-1.

(2) The central processing unit 20 instructs the instruction processing unit 2 to read the contents of the instruction memory (IM) 28.
Issued on 1-1.

(3) The external interface unit 24 generates addresses for the instruction memory (IM) 28 from address O to the final address.

(4) From the external interface unit 24, the instruction processing unit? t
21 Reads the contents of the instruction memory (IM) 28 from the address transmitted via the external interface section 25 and address bus (AD) 30 in 1 and outputs it onto the data bus (DBL) 211 and (DBU) 212 .

(5) DM on the main memory (MM) 22 of the central processing unit 20 via the external interface units 25 and 24
Transfer the program by A.

(6) Check inside the central processing unit 20.

As is clear from the above description, according to the embodiment of the present invention, the normality of the program stored in the instruction memory (IM) 2B can be checked.

The control memory (CM) 27 stores control contents according to commands from the central processing unit 2o, and the contents of the control memory (CM) 27 are also stored in the main memory of the central processing unit 20 using the same procedure as above. (MM) 22, it is also possible to check the hardware of the instruction processing device.

Note that in the above-described embodiment, when the following hardware failure occurs, the program in the instruction processing device cannot be read out, and the hardware failure must be detected by other means.

(1) When data cannot be transferred between the central processing unit and the instruction processing unit due to a failure in the external interface section.

(2) Failure of the IM address generator.

(3) Failure of the IM address switching unit.

However, hardware failures other than those mentioned above can be detected by the above-mentioned program health check.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by providing a means for causing the central processing unit to read the operating state including the program inside the instruction processing unit, the normality of the program inside the instruction processing unit can be improved. Since the normality of operation can be detected, it is possible to easily detect whether a firmware failure or software failure is occurring, and the failure recovery time can be significantly shortened.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing a system applied to an embodiment of the invention, and Fig. 3 is a block diagram showing in detail the configuration of the instruction processing device of Fig. 2. It is a diagram. 27... Control memory, 28... Instruction memory, 29... Buffer memory, 30... LC controller, 31-1, 31-2... Line controller.

Claims (1)

[Claims] An instruction processing device (2) having an instruction storage means (1) and operating under storage program control, and the instruction processing device (2).
In a data communication system, the central processing unit (3) is provided with an operating state reading means (4) for reading the operating state including the internal program of the instruction processing unit (2). ), the instruction processing device (2)
A test method for an instruction processing device, characterized in that the central processing unit (3) can determine the normality of the internal program and the normality of the hardware.