JPS63227277A - Compression/expansion processor - Google Patents

Abstract

PURPOSE:To compress image data at high speed in a compression/expansion processing mode, by making the update of generation pointer data unnecessary in a second operation when the generation of code data is performed for two times. CONSTITUTION:When selected data is runlength data, the code data for a color designated by a second control data is generated according to generation address data from a generation address generating means. An encoder means 18 that is a means to generate the code data according to the generation address data from the generation address generating means when the selected data is a first control data, and which outputs the code data by separating outputting in two times when generated code data exceeds length decided in advance and outputs the code data of length decided at second time is provided. In such a way, it is possible to compress the image data at high speed in the compression/expansion processing mode.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a compression/decompression processing device that decompresses code data into image data and compresses image data into code data, and particularly relates to a compression/decompression processing device that decompresses code data into image data and compresses image data into code data. The present invention also relates to a compression/decompression processing device that can pipeline compression processing in parallel and reduce the chip area when integrated into an LSI.

(Prior Art) As a method for compressing and decompressing binary data, the CCITT (International Telegraph and Telephone Consultative Committee) recommends the use of MH, MR, and MMRMR codes for facsimile. , internationally standardized,
Widely recognized.

Binary data compression/decompression processing devices using these methods are:
Conventionally, this has generally been performed by sequential software processing using a general-purpose microcomputer. In such processing, there is no problem in using it as a facsimile machine whose data transmission speed is limited. However, when attempting to use the above-described method to display image data on a computer system workstation, the operating speed is significantly reduced and a good man-machine interface cannot be achieved. Parallel processing, proactive processing, and vibe line processing are commonly used methods to solve these problems.

However, the desired speed has not yet been reached.

(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a compression/expansion processing device that can compress image data at high speed in a compression/expansion processing mode.

[Structure of the Invention] (Means and Effects for Solving the Problem) A compression/expansion processing device according to the present invention selects one of input run length data and input first control data, and a generated address generating means for generating and outputting generated address data from the selected data and input second control data; and when the selected data is run-length data, the generated address generating means Generate code data for the color specified by the second control data according to the generated address data, and when the selected data is the first control data, generate the code data according to the generated address data from the generated address generation means. When the code data to be generated exceeds a predetermined length, the code data is divided into two outputs, and the code data is output for the predetermined length in the second time. and encoder means for outputting code data. Thereby, image data can be compressed at high speed in the compression/expansion processing mode.

(Example) Below, a compression/expansion processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

First, with reference to FIGS. 1 to 10, the configuration of an embodiment of the compression/expansion processing apparatus according to the present invention will be described.

First, with reference to FIG. 1, a circuit block of a compression/decompression processing apparatus according to an embodiment of the present invention will be described.

The embodiment includes a compression/expansion processing section 2, a compression/expansion processing control section 4, and its LSI built into an integrated circuit (LSI).
It is connected to the SI and consists of a reference line buffer 7 and a memory 6 for storing reference line data.

The compression/expansion processing unit 2 performs pipeline processing on input binary data to perform compression processing or expansion processing.

The compression/decompression processing unit 2 includes a decoding processing unit 12 and a generation processing unit 1.
4, and a buffer memory control section 16.

The decoding processing unit 12 decodes the input code data in the decompression processing mode, and decodes the input code data in the compression processing mode.
Works to detect points. The generation processing section 14 generates image data based on the decoding result of the decoding processing section 12 in the decompression processing mode, and generates code data based on the detected aO point in the compression processing mode. The buffer memory control unit 16 accesses the reference line buffer memory 6 to write or read reference line data 1, and determines whether the generation process has progressed to the end of the line.

The generation processing unit 14 includes a generation combination unit 18 and a b1 detection unit 9. The generation and combination section 18 includes a counter section 30, a conversion section 32, and a combination section 34. Counter section 30
holds the run length data decoded by the decoding processing unit 12 in the decompression processing mode, and counts the run length in the compression processing mode. The converter 32 generates image data or code data as combined data in accordance with run length data from the counter 30 or the run length calculator 38 . Joint part 34
combines the generated combined data one after another to generate the desired binary data.

The b1 detection section 19 includes a color change point detection section 36 and a run length calculation section 38. The color change point detection unit 36 detects point b1 in the reference line data based on the reference line data read from the reference line buffer memory 6. The run-length calculation unit 38 calculates the length of image data to be generated for run-length data other than run-length data of 1 byte or more with respect to one-dimensional code data in the decompression processing mode, and calculates the length of image data to be generated for run-length data other than run-length data with a length of 1 byte or more for one-dimensional code data, and in the compression processing mode, the run-length calculation unit 38 calculates the length of image data to be generated. Data corresponding to the difference between b1 point and 81 point at the time of b is calculated.

The buffer memory control section 16 also includes an address section 40, a data input/output section 42, and a line end detection section 44.
It consists of Prior to processing, the line end detection unit 44
It receives and holds run-length data for a line, and detects the byte position where the generation process is currently progressing. In this way, the end of the line is detected. The address unit 40 determines the address of the reference line buffer 7 memory 6 in which image data related to the byte block of interest is stored, based on the byte position detected by the line end detection unit 44 and where the current generation process has progressed. Also, an address for storing reference line data for the next processing line is determined based on the detected byte position. The determined address is output to the reference line buffer memory 6. This address section 40 is a reference line buffer memory 6
This is necessary when static RAM is used. When first-in-first-out (FIFO) memory is used, address section 40 is no longer needed;
The compression/expansion processing control section 4 requires a circuit section for controlling the read/write mode. The data input/output section 42 inputs image data from the generation/combination section 18 in the decompression processing mode, and inputs image data from the wl reading processing section 12 in the compression processing mode to the reference line buffer memory 6 specified by the address section 40. The reference line data of the current processing line is read from the address of the reference line buffer memory 6 specified by the address section 40.

The compression/expansion processing control section 4 includes a main sequencer 7, a decoding processing section subsequencer 8, and a generation processing section subsequencer 9. The main sequencer 7 controls all of the internal components of the LSI, and also exchanges commands/status with an external control device (not shown). Inside it, whether the line being processed is one-dimensional or two-dimensional
Tag flip 70 tubes (TA
G flip-flop (not shown) and a color control flip 70 (FBLK) to indicate whether the color of the run being processed is white or black.
It has a built-in flip-flop such as a D flip-flop (not shown). The decoding processing section subsequencer 8 controls the operation of the decoding processing section 12. Further, the generation processing section sub-sequencer 9 controls the operation of the generation processing section 14.

The configuration of each part will be explained in detail below.

First, the configuration of the decoding processing section 12 will be explained in detail with reference to FIG.

Binary data RDINOO-07 is input in byte units to the decoding processing unit 12 as data A1. This data RD
I N 00-07 is code data in the expansion processing mode, and is image data in the non-compression processing mode and the compression processing mode. Register RDT1102 is a register having a data length of 3 bytes. Register RD
T1102 converts the held data into data RD T I 08-1 according to the *1m signal from the control unit 4.
5 becomes data RDTI 00-07, and data RDTI 16-23 becomes data RDTI0.
Shift in the LSB direction (left direction) in byte units so that the number becomes 8-15. After that, data R[) I N0O-
07 is latched as data RD T I 16-23. In compression processing mode, the retained data RD
T I 00-07 is stored as data A2 in the reference line buffer 7 memory 6 via the buffer memory control unit 16 in order to be used as reference line data for the next compression processing line. Data RDTI09-23
is output to the funnel shifter 104.

The funnel shifter 104 receives decoding pointer data RBPPO2- from the decoding pointer register RBPP116.
00 is output. Funnel shifter 104 outputs 1 byte of data SHTDOO-07 selected according to decoding pointer data RB P PO2-00.

For example, decryption pointer data RB from register 116
When P PO2-00 is “3” (011), data input to Huhsnel shifter 104 RD T I
The 12-19 bit portion of 09-23 is selected and output as data 5HTDOO-07.

Register RD T I 102 and Hunnel shifter 104
The circuit functions as a selection circuit for processing data.

Data 5HTDO output from Huhnel shifter 104
O-07 is supplied to the color inversion circuit 106. Color inversion circuit 106 consists of eight exclusive or gates (not shown). Color control data M1 from the control section 4 is supplied to one input terminal of each exclusive OR gate. Bit data of data SHT D 00-07 from the Huhsnel shifter 104 is supplied to the other input terminals, respectively. In this manner, the color inversion circuit 108 passes the input data 5HTDOO-07 directly in the decompression processing mode and the non-compression processing mode, and passes the input data 5HTDOO-07 in the compression processing mode according to the color control signal M1 from the control unit 4. Inverts the colors of the image data so that the direction of color change is uniform from white to black. Data DT (S 00-0
7 is supplied to the converter 32 as data A3, and is also supplied to the selector 110 and mask gate 108.

The mask gate 108 receives input data DTISOO-01.
Generate mask data according to the following. mask gate 10
8 generates a predetermined number of bit data in meaningless portions of the decoded data in order to reduce the storage area used in the decoder ROM 112.

Mask data is supplied to selector 110.

Data RD S OO4-02 is supplied to the selector 110 from the control section 4 as data M3. This data RDSQO4-02 is control data for specifying the table to be referenced next in the decoder ROM 112 in the decompression processing mode and the non-compression processing mode, and is (111) in the compression processing mode. Selector 11
0, the control unit 4 also receives data D N D POO=
07 is supplied as data M2. This data D
ND POO-07 is usually [00]. At the end of the processing line in the compression processing mode, data D N D P is added to the right side of the end run to compensate for the virtual change point.
In OO-07, only one bit on the right side of the terminal run is 1''.

In the decompression processing mode, data 0 from the color inversion circuit 106
Data synthesized from TISOO-07 and mask data from mask gate 108 and data R[)3QO4
-02 to address data DRM A 10-00
is formed and supplied to the decoder ROM 112.

In the compression processing mode, the synthesized data is further logically summed with the data DND POO-07, and the data R
Address data DRM A along with DSQO4-02
It is supplied to the decoder ROM 112 as 10-00. Mask gate 108 and selector 110 function as a decoding address generation circuit.

The decoder ROM 112 has a plurality of tables, and input address data DRM A 1O-OO
Accordingly, 12-bit data DROMII-00 is output. The table included in the decoder ROM 112 is
One-dimensional mortar 1 code table (white A) and one-dimensional mortar 2 code table (white B) for decoding the white run one-dimensional code
, a one-dimensional black 1-code table (black A), a one-dimensional black 2-code table (black B), a one-dimensional black 3-code table (black C), and a vertical mode code for decoding the black run one-dimensional code. a two-dimensional code table for decoding pass mode codes and horizontal mode identification codes, an uncompressed mode code table for decoding uncompressed mode codes and fill skip codes including uncompressed mode end codes, and decompression Decipher the EOL code in processing mode,
This is a special code table for decoding image data in compression processing mode.

The uncompressed mode start code and the fill skip code can also be decoded using table white A, white B, or two-dimensional code table and table black B. A special code table is also used to decode the EOL code at the beginning of the page.

In data DROMO5-00, the run length of the decoded code data is output as data A5 in decompression processing mode and non-compression processing mode, and the run length of less than 1 byte of input image data is output in compression mode. Ru. Data DROMO5-00 is output to the counter section 30 in the decompression mode and uncompressed mode, and is output to the run length calculation section 38 in the compression mode.

Data indicating [(decoded code data) - 1) in the expansion processing mode and non-compression processing mode is output as data A7 to the data DROMO8-06, and in the compression processing mode ((processed image data) -1) is output. Data D ROM 08-06
C. The adder 122 outputs the output to the color change point detection section 36 in the compression processing mode.

In the data DROM 11-09, next state data for specifying the next state is output as data A4. Data DROM11-09 and bit DROM05 are not used in the compression processing mode.

Data M4 is supplied to the register RP1L119 from the control unit 4 via the selector 118.

In the compression processing mode, for example, when the 81 point is not detected and the bl point is detected, the device enters the bus test. At that time, data M4 corresponding to (bl-aO) is input to the selector 108 and is subtracted by -4. The calculation result is held in register RP1L118.

This register RP1L119 is used in the compression processing mode and is not used in the decompression processing mode and the non-compression processing mode. The data RPI LO2-00 held in the register RPI L118 is sent to the selector 120.
supplied to

The selector 120 is also supplied with data RB P POO-02 from the register RB P P 116 . In accordance with the control signal from the control unit 10, the selector 120
Select RB P PO2-00 in decompression processing mode,
When a bus test is executed in compression processing mode, data RP 1102-00 is selected. The selected data RBI LO2-00 is output to the adder 122.

The adder 112 receives data DROMOB-08 from the decoder ROM 112 and data R from the selector 120.
B 1 LO2-00 is being supplied and their data is added. 1 is further added to the addition result,
The final addition result AB P PO3-00 is entered. That is, the following formula % formula % is obtained by the adder 122. Addition result ABPP02
-00 is supplied to selector 114. Also, if one-dimensional encoding is to be performed as a result of bus test execution in compression processing mode, data A B P PO
2-00 is supplied to the conversion unit 32 as data 86. 3rd bit ABP of data A B P PO3-00
When PO3 is 41'', it means that the decoding process of 1 byte of binary data has been completed, and this is notified to the control unit 4 by data A6.
The data held in T1102 is shifted byte by byte, and the new byte data A1 is RD T I 1
It is latched as 6-23.

The selector 114 receives data ABP from the adder 122.
Outside of PO2-00, data DBPA as data E3
O2-00 is being supplied. The selector 114 selects the data ABPPO2-00 in the decompression processing mode and selects the data DBPAO2-00 in the compression processing mode in accordance with the control signal from the I control section 4. However, even in decompression processing mode, when setting the initial value, use the data DBPAO.
Select 2-00. The output from selector 114 is input to and held in register RBPP116. The register RBPP116 stores the held data RBPP
O2-00 is output to the selector 120 and also output to the barrel shifter 104 as decoding pointer data. Selector 114, register RBPP116, and adder 1
The circuit consisting of 22 functions as a decoding pointer data holding circuit.

Next, the configuration of the counter section 30 will be explained with reference to FIG.

The selector 124 receives data A5 from the decoder ROM 112 and output data ANLCO from the adder 130.
8-00 and a part of the output from the counter RN L C126, RN L CO2-00, are input. Also,
Data "2556" is set in advance. According to a control signal from the control unit 4, output data DNLC11-00 is selected from these input data.

That is, in decompression processing mode, when the makeup code is decoded, data DROMO5-00 is set in the 11-06 bit part, and data DNLC11-00 with "O" set in the os-oo bit part is selected. be done. When the termination code is decoded, data "i On" is set in the 11-06 bit part, and data DROM05-00 is set in the os-oo bit part.
Data DNLC11-00 in which is set is selected. When image data is generated according to the decoding result, the output A of the adder 130 is added to the 11-03 bit part.
NL 008-00 is set, and data DNLC11-00 in which data RN L CO2-00 is set in the 02-XX bit portion is selected. Roughly speaking, in compression processing mode, data “2556” (1000111
111100) is selected as data DNLC11-00.

Data DNLC11-00 is latched into register RNLC126. Of the data RN L C11-00, data RN L CO3-00 is output to the run length calculation unit 38 as data B3. Of the data B3, data RN L CO2-00 is returned to the selector 124.

When 1 byte worth of image data is generated, data RNLC11-03 is generated according to the control signal from the control unit 4.
is output to the adder 130 and added to the delta "-1", that is, "1" is subtracted.

The addition result A N L C08-00 is sent to the selector 124
At the same time, it is returned to the selector 146 as data B2.
is output to. Data RNLC11-03 is output to comparator 128. Data "0" (000000000) is input to the other terminal of the comparator 128, and the data RNLC11-03 is compared with the data "0". Thereby, in the decompression processing mode, it is determined whether or not the image data generation processing in units of bytes has been completed. Data RNLC11-03 is “0”
When it becomes equal to , the control unit 4 is notified of this by data B4. Selector 124 and register 126
The circuit consisting of the adder 130 and the adder 130 functions as a counter circuit.

The circuit consisting of the selector 132, register 134, adder 13G, selector 138, register 140, subtracter 142, and comparator 144 is used only in the compression processing mode. When horizontal mode encoding is performed, the selector 132 selects preset data (000) according to the control signal from the control unit 4 and stores it in the register RN.
Output to UC134. When the run length as a result of counting the runs of the same color is longer than 2560 bits, that is, when data B4 is output from the comparator 128 to the control unit 4, the data RNUCO2-00 held in the register RNUC134 is set to 1 by the adder 136. will be added. The addition result is again selected by the selector 132 and held in the register RNUC134. When the same color run is completed, data RNU CO2-00 is provided to selector 138.

The selector 138 selects the input data RNUCO2-00.
is selected and output to register RNUG140.

Register RNUG140 stores data R[7G every time a code for a run length of 2560 bits is generated.
Outputs 02-00. Data RNIJGO2-00 is decremented by 1 by subtracter 142, selected by selector 138, and held in register 140 again. The data RN U CO2-00 output from the register RN U G 140 is also output to a comparator 144 to check whether it is 0'' or not.

If the data RN tJ CO2-00 is 0, it means that the makeup code generation process has been completed.

Next, the configuration of the converter 32 will be explained with reference to FIG. 4.

The circuit consisting of selector 14G, register RNLG 148, comparator 150, and selector 156 is for generating a one-dimensional code in compression processing mode, and the circuit consisting of selector 152, register 154, and selector 156 is for generating two-dimensional code in compression processing mode. Works as a generation address generation circuit for generating dimensional codes.

The 11-03 bit portion of the selector 146 contains data 8.
Data A N L C08-00 is input as 2,
Further, data A B P PO 2-00 is input to the 02-00 bit portion as data 86. Those data are stored in register RNLG148 as data RNLG11.
Latched as -00. Data RNLG11-06
is output to the comparator 150. Comparator 1
50 Niha, Mata, 7'-9 (100111) is supplied. Data RNLGII-06 is data “”100
111'', the controller 4 is notified by data C2. This means that the counted run length is 64.
This means that the code to be generated is a terminated code. Data RNLG11-06 and data RNLG05-00 are supplied from register RNLG148 to selector 156.

The selector 152 has data ADLT as data F2.
O2-00 is supplied from the run length calculation unit 38, and data EGCDO3-00 is supplied as data M5.
is supplied from the control section 4. Data EGCDO3-
For 00, data (1) is used as the 4th bit data.
is set, and data (01) is set as the fourth and third bit data for data ADLT02-00. When a vertical mode code is to be generated in compression processing mode, data (01) ADLTO
2-00 is selected, and when a special code such as a horizontal mode identification code or an EOL code is to be generated, data (1) EGCDO3-00 is selected. The selected data is output to register RG CD 154 as data DG CD 04-00. register RG
The CD 154 holds the input data DGCDO4-00 and sends it to the selector 15 as data RGCDO4-00.
Output to G.

The selector 156 includes a flip-flop FB of the control unit 4.
Got data DBL from LKD for specifying color
K is supplied as data M6, and data F2NG indicating the number of times of compression processing is supplied as data M8. Data DBLK is (0) when specifying white, and (1) when specifying black. Data F2NG is (0) in the first processing step of the code to be generated, and becomes (1) in the second processing step.

For input data RNLGGO5-00, (0) is set as the 7th bit data, and for input data RNLG11-06, (1) is set as the 7th bit data. There is.

Furthermore, for the input data RG CD 04-00, (11
) is set.

Therefore, in the makeup code generation processing step, data (DB LK) (1) RN LGll-O6
(F2NG) is selected. In the termination code generation processing step, data (DBLK) (0) RNLGO
5-00 (F2NG) is selected. Also, when other codes should be generated, data (DBLK) (1
1) RGCDO4-00 (F2NG) is selected. The selected data is 9-bit address data ERMA
It is output to the encoder ROM 158 as O8-00.

The encoder ROM 158 stores address data ERMA.
08-00 is input Lr, and data EROM10-00 is output. An encoded code is output to the data FROM 7-00 portion, and is supplied to the selector 160.

The data FROM10-08 part contains data FROM0.
The length of the encoded code output as 7-00 is -1
” is output as data C3.

Register RPAT162 has a data length of 8 bits,
Data A2 is input from the decoding processing unit 12 and the selector 16
Output to 0. This register 162 is used in the non-compression processing mode and in the bit shift mode.

The selector 160 receives data RPATO7-00 from the register RPAT162, data DREN10-03 from the color change point detection unit 36, and (7)7'-ta EROMO7- from the encoder RoM158.
00 is supplied. Also, data (1111111
1) and data (00000000) are set.

In the decompression processing mode, the flip-flop FB of the control unit 4
Data (11111111) or Data (0000000) according to the color currently specified by LKD.
0) is selected. In compression processing mode, data ERO
MO7-00 is selected. In the uncompressed processing mode and bit shift mode, data RPATO7-00 is selected. In error handling mode, data DRENIO
-03 is selected. The selector 160 selects III[1
Data ECD selected according to the control signal from section 4
Output PO7-00 as data C1.

Next, the configuration of the coupling portion 34 will be explained with reference to FIG. 5.

Data ECDPO7-〇〇 output from the selector 160 is input to the barrel shifter SHTG 164.

The barrel shifter 5HTG164 receives generated pointer data R-BPQ from the generated pointer register RBPQ176.
O2-00 is being output. The barrel shifter 164 is
According to the generated pointer data RBPQO2-00,
Rotate and shift input data.

In the decompression processing mode in the MH method, MR method, and MMR method, all input data is (0).
(1) is the byte data, and is the same whether or not it is rotationally shifted. However, in compressed processing mode, uncompressed processing mode, bit shift mode, and error processing mode, the input data can be rotationally shifted to
Combinations of binary data up to 2 bytes = 1) in length can be processed in one generation processing step.

For example, the generated pointer data is "3" (011), and the data input to the barrel shifter 5HTG164 is (
01001110), the output data 5HTGO
7-00 becomes (11001001). The output 5HTGO7-00 from the barrel shifter 5t-ITG164 is supplied to the 15-08 bit portion of the register RODT 168 and the coupling selector EPCK166.

The selector 170 selects the data RODTO7-00 and RODTO1 held in the register RODTO168.
5-08 is selectively output according to a control signal from the control section 4. Data RODT15-08 is selected when the binary data whose generation was completed in the previous generation process step is 1 byte or more, and data RODT15-08 is selected when the binary data whose generation was completed is less than 1 byte long. RODTO8-00 is selected. The selected byte data is sent to selector 1 as data EP310-07.
66.

The selector 166 is a barrel shifter SHTG 164
The output 5HTGO7-00 from the selector 170 and the output data EPSLO-07 from the selector 170 are input. Also, like the barrel shifter 164, the same generated pointer data is supplied from the register RBPQ176.

According to the generated pointer data, the selector 166
Combine input data and create combined 8-bit data EP
CK00-07 to register RODT16817)07-
Output to the 00 bit part.

Register ROD T 168 stores data RODTO7-
-OO data RODT15-08 collector 1701
．． :,Output. In the data ROD TO7-00, 2
When the generation of value data is complete, the data ROD
TO7-〇〇 is output to the buffer memory control 16 as data D1 in order to be used as the next reference line data in the decompression processing mode. Also, data R
ODTO7-00 is outputted to the outside as data D2 via the output register ROtJT112.

Barrel shifter S HT G 164 and selector EPCK
166, register RoDT 168, and selector 170 function as a hold loop circuit.

The data C3 from the encoder ROM 158 and the generated pointer data RBPQO2-00 of the register RBPQ176 are input to the adder 178. In the compression processing mode, the data FROM10-08 outputs a code length that is 1 smaller than the actual length of the encoded code, so the addition result in the adder 178 is A B P QO3
-00 is calculated as follows = A B PQO
3-00-F R0M1O-08+RBPQO2-00
+1 Lower 3 bits A of this addition result ABPQO3-00
BPQO2-00 is output to selector 174. Further, when the third bit is (1), it means that the generation process for one byte has been completed, and this is notified to the control unit 4 by data D3.

The selector 174 receives data E from the color change point detection section 36.
3, data DBPAO2-00 and data ABPQO2-00 from the adder 178 are input. Further, data "0" is set in advance.

In the decompression processing mode and the bit shift mode, data DBPA02-00 are selected according to a control signal from the control section 4. Also, when in compression processing mode, data A
BPQO2-00 is selected. Further, in the initial state and in the error processing mode, data "0" is selected.The selected data is output to the register RBpQ176.

Register RBP0176 holds data from selector 174 and outputs it as generated pointer data to barrel shifter 5HTG164 and selector EPCK166 in accordance with a control signal from control unit 4.

The adder 178, selector 174, and register 176 are
Works as a generation pointer data holding circuit.

Next, the configuration of the color change point detection section 36 will be explained with reference to FIG.

The register RREF180 contains the buffer memory control unit 1.
Reference line data is supplied as data G4 from the reference line buffer memory 6 via G.

There is. Register RREF 180 has a data length of 27 bits. According to the control signal from the control unit 4, the register RREF 180 changes the data RRE (RRE) so that the data RREFO8-10 becomes the data RREFOO-02.
”, data RREF19-26 become data RREF1 so that 11-18 becomes data RRE FO3-10.
Shift the data in bytes so that it becomes 1-18,
Thereafter, data G4 is input into the 19-26 bit portion. Data RRE FOO-2 of data RRE FOO-26 held in register RRE F 180
1 is output to the 77 channel shifter 182.

Funnel shifter 182 inputs data RRE FOO-21 and outputs 15-bit data 5HTPOO-14 selected according to aO pointer data RBPAO2-00 from register RBPA200. For example, aO
When pointer data RBPAO2-00 is 5",
Data 5HTPOO-14 is data RREF05-1
Corresponds to 9. That is, 15 bits of data from the 6th bit of data RREFOO-21 are selected. A circuit consisting of register RREF 180 and Huhsnel shifter 182 functions as a reference line data selection circuit.

The color inversion circuit 184 receives data 5HTPOO-14 from the barrel shifter 182 and data M from the control section 4.
9 has been input. In compression processing mode, color inversion circuit 1
84 works to unify the direction of color change of pixels from white to black. Therefore, when detecting a color change point from a white run to a black run, the color inversion circuit 184 outputs the input data as is. When detecting a color change point from a black run to a white run, the color inversion circuit 184 inverts the input data and outputs the inverted data. In error processing mode, the input data is output in the same color as it was input. Color inversion circuit 1
84 outputs the color standardized data DRENOO-14 to the change point detector 186. In addition, data DREN03-
10 is output to the converter 32 as data E1.

The change point detector 186 receives data DRENOO-14 from the color inversion circuit 184 and data DNDPO from the control unit 4.
O-10, the first data of the run, and the first data of the line are input as control data M7, and a color change point is detected. Since the direction of color change is unified, the color change point is set as bit data (0). Detected color change point data D
RE C01-14 is priority encoder 188
is output to.

The priority encoder 188 is connected to the change point detector 18
Input the color change point data DRECO1-14 from 6. The bit position of the color change point closest to the LSB position of the input data DRECO1-14 is converted into a binary number, and the converted data B 1 t) TO3-00 is output. Therefore, when the fifth bit of data DRECO1-14 is set as a color change point, data B1D T03-0
0ha "5n (0101) tonal. The position of the color change point is the data in register RODT168 RODT 00-08
In relation to this, this fifth bit is the bit data ROD
Compatible with TOI. In this way, the detected color change point data is “+4” with respect to the bit position within the block of interest.
It is shaped like this.

The detected data BID TO3-00 is data E
Output as 2.

A circuit including the color inversion circuit 184, change point detector 186, and priority encoder 188 functions as a b1 point detection circuit.

The selector 192 is supplied with data RBPAO2-00 from the register RBPA200. Also, data (111) is set. According to the control signal from the control unit 4, data RBPAO2-00 is selected in compression processing mode, decompression processing mode, bit shift mode, non-compression processing mode, and error processing mode, and data (111) is selected in the initial state. selected. The selected data is output to adder 196. The selector 194 receives data DRO from the decoding processing unit 12 as data A7.
MO8-06 and data 5TATO2-00 are also input from the control unit 4 as data M10. Also,
Data “0” is set. The selector 194 is
In accordance with the control signal from the control unit 4, data DROMO8-06 is selected in the compression processing mode. At the beginning of the line in compression processing mode, data 5TATO2-00
Select. Data "0" is selected at the beginning of the line in decompression processing mode, bit shift mode, non-compression processing mode, and error processing mode. The selected data is output to adder 196.

The adder 196 adds the data input from the selectors 192 and 194, and further adds 0" or "1" to the addition result according to instructions from the control unit 4. At the beginning of a line in compression processing mode, "0" is added. At the beginning of a line in bit shift mode and error processing mode, data "1" is added. Also, in order to update the aO pointer data in the compression processing mode, If 1 ++
Add. The final addition result A10MO2-00 is output to the selector 198.

The selector 198 receives data A1CM from the adder 196.
O2-00 and data F from the run length calculation unit 38
Input data AB1AO2-00 as 1.

In accordance with the control signal from the control unit 4, the selector 198
In the compression processing mode, data A 10MO2-00 is selected, and in the decompression processing mode and non-compression processing mode, data AB1AO2-00 is selected. Selected data DB
PAO2-00 is output to the register RBPA 200 and is used as new aO pointer data.

In addition, data DBPAO2-00 is data E3,
In the decompression processing mode, the data is output to the conversion section 34, and in the compression processing mode, it is output to the decoding processing section 12.

Register RBPA200 inputs and holds data DBPAO2-00 from selector 198, and stores data RBP
AO2-00 is output to the funnel shifter 182 as aO pointer data. It is also output to the run length calculation unit 38 as data E5. register RBPA200,
A circuit consisting of selectors 192 and 194, adder 196, and selector 198 functions as an aO pointer data holding circuit.

Next, the configuration of the run length calculation section 38 will be explained with reference to FIG.

The third bit of the selector 201 receives data M from the control section 4.
11 are supplied. Data RN L CO2-00 is supplied from the counter section 30 to the Oth to second bits. Data ``0'' is set in the third bit of the selector 202.Data RBP A 02-00 is supplied as data E5 to the Oth to second bits.The outputs of the selector 201 and the selector 202 are It is output to the adder 204 in the decompression processing mode.

Adder 204 adds the outputs of selector 201 and selector 202. At this time, for the leftmost byte of the line at ° in the one-dimensional decompression processing mode and the non-compression processing mode,
According to instructions from the control unit 4, 1' is roughly added. The final addition result AOPL 03-00 is output to the selector 206.

The selector 206 connects the adder 20 to the 03-00 bit portion.
Input data A OP LO3-00 from 4th
Data M12 is input from the control unit 4 to the bit and held.

The held data is output to adder 210.

Data B 1 D TO3-00 is supplied to the selector 208 from the color change point detection unit 36 as data E2. Further, data (11111) is set in advance. According to the control signal from the control unit 4, data (
11111) is selected, and in the two-dimensional code expansion mode, data (0)+data B1DTO3-00 is selected. The selected data is output to adder 210.

Adder 210 adds the data from selectors 206 and 208. In the one-dimensional code decompression processing mode and non-compression processing mode, data ``1'' is further added to the addition result.In addition, in the final step of the non-compression processing mode, the further added data is ``O''. be. Also, 2
In the dimensional code decompression mode, data "0" is added. In the 1-dimensional code decompression processing mode and non-compression processing mode, the 4th and 3rd bits of the final addition result AB1LO4-00 are (01). When , it indicates that the synthesis of one byte of binary data has been completed in the coupling section 34, and when it is 0'', it indicates that the synthesis process has been completed during the byte currently being synthesized. This is notified to the control unit 4 by data F1. The final addition result A31LO4-00 is output to the color change point detection section 36 as data F1.

The selector 212 selects data RNLCO as data B3.
3-00 and data DROM03-0 as data A5
Enter 0. According to the control signal from the control unit 4, data RNLCO3-00 is selected in the decompression processing mode, and data DROM 03-00 is selected in the compression processing mode. The selected data is output to adder 216.

The inversion circuit 214 outputs the color change point detection unit 3 as data E2.
Data B1D Ta2-00 from 6 and M2S are input as control data from the control unit 4. In the two-dimensional expansion processing mode, the data B 1 D Ta2-00 is passed through as is, and in the compression processing mode, the data B 1 DT 0 is passed through.
3-00 is inverted. That is, "0" becomes 1", "1n
is changed to "0". Data from inversion circuit 214 is output to adder 216.

Adder 216 inputs the inverted data from inverting circuit 214 and the data from selector 212, and adds them. In two-dimensional decompression processing mode, the addition result is data A
Output as L Ta2-00. In the compression processing mode, data "1" is further added to the result of the addition. That is, as a result, B1 input to the inverting circuit 214
This means that the two's complement of DTO3-00 has been found. In compression processing mode, the result of this addition is data A D L T
Output as a2-00.

If the third pit of this data A31A is "1", in the coupling section 34, 1 byte of 21i! Indicates that the data synthesis has been completed, and if O'', it indicates that the synthesis process has been completed during the byte currently being synthesized. This is notified to the control unit 4 by data F1. Data F2 is also supplied to the converter 32.

Next, referring to FIG. 8, the buffer memory ti control section 1
The configuration of No. 6 will be explained.

The selector 224 has the output A8FA10 of the adder 228.
- (10 is input to the selector 224. Furthermore, data "-4" is preset in the selector. According to the control signal from the control section 4, "
-4''' is selected. Also, in order to access the reference line buffer 7 memory 6, data A 8 F A
10-00 is selected. The selected data is output to register RBFA 226. register 226
holds the input data and outputs it to the adder 228.

The selector 230 contains data “1” and “4” (<100)
is set in advance. According to the control signal of the control unit 4, data "1" is selected when storing image data in the reference line buffer memory 6, and data "4" is selected when reading image data as reference line data.
'' is selected. The selected data is output to adder 228.

Adder 228 adds data from register RBFA 226 and data from selector 230. Addition result A
BFAIO-00 is output to selector 224, comparator 220, and selector 232.

The register END 8218 contains one line of run length data as data M14.
It is given in advance from Section 4. Register E N D 8
Among the data held in 218, data E N
D B 13-03 is output to comparator 220.

Comparator 220 receives data AB from adder 228.
FA10-00 is also supplied. The two data are compared, and when they match, data G1 is output to the control section 10. In other words, it can thereby be confirmed that the processing of binary data has progressed to the final byte position of the line. Data EN D BO2-00 held in register END 8218 is output to comparator 222 . Data RBPAO2-00 is supplied to the comparator 222 as data E5. These data are compared, and when they match, the control unit 4 is notified by data G2. This confirms that processing has proceeded to the complete end of the line following confirmation of the final byte position.

The above-described circuit portion of the buffer memory control section 16 constitutes a line end detection section 44.

Selector 232 receives data ABF from adder 228.
A Enter 10-00 into the 10-00 part. Further, reference line data WD 07-00 is supplied.

IIJ11N data M15 is input from the υllm1 unit 4 to the 11th pit. This control data M15 is for specifying the area of the reference line buffer memory 6, and for the reference line buffer 7 memory 6, the signal RAH
is output as The selector 232 selects data AB when the static RAM is connected as the reference line buffer memory 6 according to a control signal from the control unit 4.
When FA10-00 is selected and the FIFO memory is connected as the reference line buffer memory 6, the data W
Select D 07-00.

The output of selector 232 is output to register RADR234.

The register RADR 234 holds input data and outputs it to the reference line buffer memory 6 via the off-chip driver 236. A circuit consisting of a selector 232, a register 234, and an off-chip driver 236 functions as an address section.

The selector 238 has data RDT as data A2.
I 00-07 is also data RO as data D1
DTOO-07 is input. Also, data (oooo
oooo> is set in advance. According to the control signal from the control unit 4, in the decompression processing mode, the data RO
DTOO-07 is selected and RD in compression processing mode.
T I 00-07 is selected. In the initial state, data (0) is used to clear the reference line buffer memory 6.
0000000) is selected. The selected data is
It is output to the reference line buffer memory 6 via the off-chip driver 240. Further, the reference line data read from the reference line buffer memory 6 is sent to the receiver 24.
2, it is output to the color change point detection section 36 as data G4.

Next, with reference to FIG. 9, the configuration of the change detector 186 of the color change point detection section 36 will be described.

Basically, in order to find the point of change from white (0) to black (1), the data DRENOO from the color inversion circuit 184 is
-14 and each bit of DRENOO-14 inverted and shifted to the right one bit at a time, and then in the line end processing,
Data D N to supplement the virtual change point on the right side of the terminal point
The configuration is such that the negative sum with DPOO-10 is calculated. In addition to this basic configuration, special circuitry is added to accommodate processing in the first step of the line and processing in the first step of the run. Processing in the first step of a line refers to processing the first byte of the line. As shown in FIG. 25a, the byte boundary may not coincide with the left end of the line depending on how input data is provided. Then, the b1 point may be directly above the 80 point. In such a case, in order for point b1 to be detected as a changing point, the previous bit must be (0). This process is carried out by DRENO2 and Ill II.
NA that takes the negative tank with the I signal “inversion (first line)”
This is the ND gate 81-2. In the processing of the first step of the line, the tlIIIll signal "inverted (first of the line)"
becomes (0). Therefore, this NAND gate 81-2
Therefore, in the processing at the first step of the line, D
RENO2 is always treated as (0). In other words, D.R.
ECO3 can be detected as b1 point.

In the first step of a run, after a change point is detected, a new run is processed, and the first byte is processed. In the processing at the first step of the run, as shown in FIG. 25, since point b1 is to the right of point 80, no change point to the left of point 80 should be detected.

This type of processing is performed using the control signal “inversion (first run
)". This control signal "inversion (first run)" becomes (0) in the first step of the run. Therefore, this control signal is combined with the inversion signal of DRENOO and the inversion signal of DRENOO.
By inputting the data to the NAND gate 81-1 which forms a negative tank with 1, the output data DRECO1 always becomes (1). Similarly, this control signal is the inverted signal of DRENOl and D
NAND gate that takes a negative tank with RENO2, 91-2
By inputting , the output data DRECO2 will always be (1).

Furthermore, in the case of processing at the first step of a line, it is also processing at the first step of a run. In such a case, D
RECO3 must be detected as point b1. However, in the case of processing not in the first step of a line but simply in the first step of a run, DRECO3 should not be detected as a change point. This process is performed by the NOVOR gate 16 that inverts the IIJ m signal "inversion (first line)" and the logical OR of the output of the NOTOR gate 16 and the control signal "inversion (first line)".
This is the R gate 83. The output of OR gate 83 is DREC
It is input to a NAND gate 81-3 which outputs 03.

processing in the first step of the line and the first step of the run
In the case of step processing, the output of the OR gate 83 becomes (1), and DRECO3 can be detected as the b1 point. On the other hand, in the case of processing simply in the first step of a run, rather than processing in the first step of a line, OR
The output of the gate 83 becomes (0), and DRECO3 is not detected as a changing point.

Data DNDPOO-10 is data that supplements a virtual change point one bit to the right of the termination point, as described above, and normally each bit of DNDPOO-10 is (0). When processing the last data of the line, the data DNDPOO-
Among the 10 bits, only the bit located one bit to the right of the termination point becomes (1). Therefore, by calculating the negative sum of each hit data output from the AND gate and each bit of DNDPOO-10, a virtual change point is supplemented one bit to the right of the terminal point.

In the data DRENOO-14, change point candidates are detected through such a circuit. Data DREC01-14
In , the change point candidate is (0), and the others are (1
). Data DREC (N-14
is input to the priority encoder 188. Priority encoder 188 is DRE Cot-14
The leftmost change point candidate is detected, and data B1DTO3-00 indicating this bit position is output.

Next, referring to FIG. 10, a safety circuit for preventing a code for a run from being mistaken as an EOL code due to bit grouping will be described. This circuit is included in the main sequencer of the control section 4.

This safety circuit consists of an AND gate 75, an OR gate 76, and an AND gate 78. AAND gate 75
is supplied with a signal MCHDEC and a signal 5AFTY. Signal MCHDEC is output to decode the next code when two EOL codes are read in the MH system and the MR system, and one EOL code is read in the MMR system. Signal 5AFTY is EO in MH system and MR system.
This is a gate that switches between returning control (RTC) when two L codes are detected consecutively (one in the MMR system) or RTC when three L codes are detected consecutively (two in the MMR system). If there are 2 EOL codes, signal 5
AFTY is (0), and if there are 2 EOL codes, signal 5
AFTY is (1).

Signal 5AFTY sets a value in a register (not shown) in the main sequencer shown in FIG.

When the signal 5AFTY is set to (1), write it into this register before inputting the code data.

The output of AND gate 75 is supplied to OR gate 76.

OR gate 76 is also supplied with signal MDECOD. The signal MDECOD is output when the first EOL code is decoded using the MH or MR method. OR gate 1
The output of 6 is output to AND gate 78.

The AND gate 78 is also supplied with an inverted signal of the signal DECID, which is logically multiplied with the output from the OR gate 7G and output as the signal DECODE. This faith,
The inverted signal of the code DECID is a signal indicating that the decoding processing section 12 is in operation, and the signal DECODE is not output when the decoding processing section 12 is in operation.

Next, the connection relationship between the reference line buffer memory 6 and the compression/expansion processing device 11 will be explained with reference to FIGS.

First, with reference to FIG. N, an example will be described in which a high-speed static memory SRAM (for example, 7MM2018D manufactured by Toshiba) 6-1 is used as the reference line buffer 7 memory 6. The reference line data address is the compression/expansion processing device 1.
It is output from RA 09-00 of No. 1 to SRAM 61. When this SRAM6-1 is 7MM2018D,
The 7MM2018D has a capacity of 16 bits or 2 bytes.

Therefore, the first address bus on the compression/decompression processing device side
Zero bit lines are not used. Instead, f! A 4-area switching signal RAH is connected to the 10th bit line of the address bus.

Reference line data is exchanged between the reference line data bus RD 07-00 of the compression/expansion processing device 1 and the I10 port 01-08 of the SRAM 4-1. In addition, from the compression/expansion processing bag [1], the memory write signal MWR is
A write enable terminal WE of RAM 4-1 is supplied, and a memory read signal MRD is supplied to an output enable terminal OE. Furthermore, the chip select terminal O8 of the SRAM 6-1 is grounded.

FIG. 8 shows a first-in-first-out (FIFO) type memory 6 as a reference line buffer 7 memory 6.
This is an example when -2 is used in single buffer 7 mode. As this FIFO memory, for example, NEC's μ
PO41101G can be used. The compression/expansion processing device 1 outputs reference line data from a line for outputting a reference line data address when the SRAM is connected. The output reference line data is F
It is input to terminal DI NO7-00 of IFO metlJ6-2. FIFO memory 6-2 terminal DOLJTO7
The reference line data read from -00 is input to the compression/expansion processing bag M1 via the reference line data bus line RD 07-00.

The compression/expansion processing device 1 supplies the FIFO memory 6-2 with a memory write signal MWR to a write enable terminal WE, a memory read signal MRD to a read enable terminal RE, and a memory reset signal MR8T to a reset write terminal R3TW and a reset read terminal R3TR. supply to. F
Clock terminals WCLK and RCLK of IFO memory 6-2
0x2-CLK is supplied. However, F
Since the IFO memory 6-2 is used in single buffer mode, the area switching signal RAH is first-in-first-out (F I FO) as the compression/expansion 6.
This is an example when the type memory 6-2 is used in double buffer mode. As for this FIFO memory, for example, μPO41101G manufactured by NEC Corporation is used in the same manner as described above.
can be used. From the compression/expansion processing device 1,
Reference line data is output from a data line for outputting a reference line data address when the SRAM is connected. The output reference line data is stored in FIFO memory IJ6-3,! =6-4 (7) Terminal DIN
07-00d are respectively input. FIFO memory 6-
The reference line data read from terminals 2 and 6-4 of DOLI 07-00 is connected to the reference line data bus line RD.
It is input to the compression/expansion processing device 1 via O7-00.

Memory write signal MWR from compression/expansion processing device 1 is supplied to inverter 5-1. Also, memory read signal J
jMRD is supplied to the inverter 5-2. Area switching signal RA H is supplied to NAND gates 5-5 and 5-6 and inverter 5-3. The output of inverter 5-1 is supplied to NAND gates 5-4 and 5-6. The output of inverter 5-2 is supplied to NAND gates 5-5 and 5-7. NAND good 5-4.5-5.5-
The outputs of 6 and 5-1 are respectively FIFO6-3
Light eple terminals WE and IJ-Toine 7jL,
Terminal RE 1. :, is supplied to the write enable terminal WE and the read enable terminal RE of the FIFO 6-4.

In addition, the reset signal MR8T of the compression/expansion processing bag H1 is as follows.
It is supplied to the reset write terminal R8TW and reset read terminal R8TR of FIFO 6-3, and to the reset write terminal R8TW and reset read terminal R3TR of PIFO 6-4. Clock signal 20 L K 4. t,
F I PO6-3 Draw 4 (7) Clock terminal WC
Supplied to LK and RCLK.

By configuring as described above, in double buffer mode, PIFO
When reference line data is read from 6-3,
Written to PIFO6-4.

Further, when reference line data is read from PIFO 6-4, it is written to PIFO 6-3.

When the FIFO memory is used as a double buffer, it can be used even when the line length is set to double by using two storage areas as one. At that time, the area switching signal RAH is not switched line by line, but specifies one of the FIFO memories for reading reference line data, and specifies the other FIFO memory for writing reference line data.

Next, the operation of the compression/expansion processing apparatus according to the present invention will be explained.

Solution 1 first! The operation of the processing unit 12 will be explained.

Binary data to be processed is input into register 102 . At this time, the data already held in the register 102 is shifted leftward in byte units. Regisia R
Among the data held in DT1102, RDT
109-23 is input to the 77 channel shifter 104. Funnel shifter 104 selects data SHTD00 according to the decode pointer data from register 116.
-07 is output.

Data SHTD 00-07 is the color inversion circuit 106
is supplied to the selector 110 without passing through. Selector 1
10 receives control data RDSQO4-0 from the control unit 4.
2 is supplied. Mask data is also supplied from the mask gate 108. The selector 110 creates address data DRMA10-00 from these input data according to the control signal from the control unit 4, and supplies it to the decoder ROM 112. The address format at that time is shown in FIG.

The decoder ROM 112 outputs data having the output format shown in FIG. data DR
OM11-09 is next state data and is sent to the control unit 4. This next state data is used, for example, to specify the table to be referenced next. Data DROMO
Data indicating (code length - 1) is output at 8-06. This code length data is supplied to the adder 122 and the color change point detection section 36. Data DROMO5-00
The run length data of the decoded code is output.

The decoding pointer data holding circuit constituted by adder 122 and register RB P P 116 operates as follows. Here, it is assumed that the previous instruction value from the register RBPP 116 is "3" (011).

In the decompression processing mode, when the length of the code data decoded this time is 7 (-111), the decoded food length is a value decremented by 1, so y': I-ta ROM1
12 outputs 6(-110>. Therefore, the addition result ABPP 03-00 in the adder 122 is ABPPO3-G.

-RB P PO2-00+ D R0MO8-06+
It becomes 1-001 +110+1. Of this addition result RBPPO3-00, RB
PPO2-00 becomes a new instruction value of register RBPP116 via selector 114. Furthermore, the third bit data of the addition result ABPPO3-00 is supplied to the control section 4 as data A6. This means that the decoding process for one byte has been completed, and the new code data is stored as A1 at 16-1 of register RDT■102.
It is latched to the 23 part.

The run length data as data A5 from the decoder ROM is sent to the register RNLC1 via the selector 124.
26. At this time, run length data for the makeup code is latched in the 11-06 bit part, and run length data for the termination code and two-dimensional code is latched in the os-oo bit part.

The run length data held in the register RNLC12B is decremented by "1" from the 11-03 bit portion every time one byte of image data is generated. The decremented value is compared with 0'' to determine whether generation of byte-by-byte image data for the run-length data has been completed.Data RN
When L C11-03 becomes equal to "O", the control unit 4 is notified by data B4. data DNLC
Of 11-00, data RN L CO2-00 is returned to the selector 124 as data B3. Also, 1
In order to generate image data for a run length of less than a byte, data RNLCO3-00 is output to the run length calculation unit 38 as data B3.

Next, the table of the decoder ROM 112 will be explained.

The decoder ROM 112 has various tables for decoding the target decoding processing unit of input address data. These tables are, with reference to FIG. A table, a two-dimensional code table, an uncompressed mode code table, and a special code table.

As shown in Figure 11 a to c, the one-dimensional mortar 1 code table decodes a white run make-up code or a white run terminated code of 8 bits or less as a unit of decoding processing, and a run length of 1728 or less and a code of 9 bits or more. Of the white run makeup codes, the code part up to the 8th bit is decoded as a unit of decoding processing, and 7 of the white run makeup codes with a run length of 1792 or more and 9 bits or more are decoded.
The code part up to bit bit is decoded as a unit of decoding process, the 8 bits from the beginning of the EOL code are decoded as a unit of decoding process, and the 7 bits from the beginning of the uncompressed mode start code and fill skip code are decoded as a unit of decoding process. This is a table for

As shown in Figure 11a, the one-dimensional mill 2 code table is used to decode the code part after the 3rd bit of the white run makeup code with a run length of 1728 or less and 9 bits or more as a unit of decoding processing. It's a table.

The one-dimensional black 1 code table is shown in Figures 12a and b.

As shown in and d, a black run terminated code of 7 bits or less is decoded as a unit of decoding processing, and a black run make-up code of 7 bits or more or 7 bits from the first bit of a black run terminated code are decoded as a unit of decoding processing. However, this is a table for decoding the 7 bits from the beginning of the uncompressed mode start code and fill skip code as a unit of decoding processing.

The one-dimensional black 2 code table is shown in Figures 12a and b.

As shown in and d, when 0'' continues for 6 or more bits from the first bit of a black run make-up code or black run termination code of 7 bits or more, the code part after the 7th bit is decoded as a unit of decoding processing. death,
This is a table for decoding the uncompressed mode start code, EOL code, and fill-skip code after the 7th bit as a unit of decoding processing.

The one-dimensional thermal three-code table is shown in Figures 12a and b.

As shown in and d, when "O" continues for 5 bits or less from the first bit of a black run make-up code or black run termination code of 7 bits or more, the code part after the 5th bit is decoded as a unit of decoding processing. It is a table for

The 2D code table is a table for decoding 2D code data using the 2D code, horizontal mode identification code, and 6 consecutive bits of "0" from the beginning as units of decoding processing. .

The uncompressed mode code table is a table for decoding uncompressed mode codes.

The special code table is set to EO at the beginning of the page in decompression mode in order to decode special code data in decompression mode and image data in compression mode.
The first 8 bits "O" of the L code and the code part after the 9th bit are decoded as a decoding processing unit, the tag pit following the EOL code is decoded as a decoding processing unit, the fill skip code is decoded, and the compression processing mode is set. If "1" exists in the 8 bits of image data, the first "1"
” is decoded as a unit of decoding processing, and “1” is decoded in 8 bits.
This is a table for decoding using an 8-bit "O" as a unit of decoding processing when there is no par.

At this time, the mask gate 108 is connected to the data DTIS00-
07 and data RDSQO4-02, mask data is generated as shown in FIG. That is,
In the one-dimensional black one code table, the data DT I 300
When -01 is not (00), data DT) 303-
O6 becomes (1111). In the two-dimensional food table, when the data DT I 800-01 is not (00), the data DTIS03-06 is (1111).

In the uncompressed mode code table, data DTIS03-
When 04 is not (00), data DTISOO-〇2
becomes (111). Data D in the special code table
When T I S 00-01 is not (00), data DTIS03-07 is (11111), and when data D T I 800-05 is not (00), data DTISO6-07 is (11). In this way, the decode ROM is stored in the compression/expansion processing device fLSI.
112 chip area can be reduced.

The output format when the above table is referred to is shown in FIG. The data DROM 11-09 is next state data, and is data as shown in FIG. 14a.

(000) indicates the occurrence of an error, and (001) indicates the decoding of a fill skip. (010) is used when detecting an EOL code or when code decoding is incomplete (from white A to white B).
, from black A to black B). (011) and (100) indicate completion of decoding the make-up code and termination code, respectively, and (101) indicates entering the non-compression mode. (110) indicates a transition from black A to black C. (111) indicates compression processing, etc.

The output format of run length data is shown in FIG. Here, run length data for the vertical mode code is output in the form of "-4". Details are 14th
Shown in Figure C.

Further, the decoding states of the uncompressed mode code table and the special code table in the case of decompression processing are shown in FIG. 14d.

The one-dimensional mortar 1 code table includes next state data for white run make-up codes or white run terminating codes of 8 bits or less, code length data that is decremented by 1" from the length of the decoding processing unit, and , outputs the run length data for the code block, and outputs the next state data and the code length data of "2" for the code part up to the 8th bit of the white run makeup code with a run length of 1728 or less and 9 bits or more. , and outputs the run length data of "O", and outputs the next state data and "6" for the code part up to the 7th bit of the white run makeup code with a run length of 1792 or more and 9 bits or more. ″ length data, and
o'' run length data is output.

The 1-dimensional mill 2 code table is 9 with a run length of 1728 or less.
For the code part after the 3rd bit of the white run make-up code of bits or more, the next state data, the code length data that is decremented by 1" from the length of the decoding processing unit, and the run length for the code block. Output data.

The one-dimensional black 1 code table contains the next state data for a black run terminated code of 7 bits or less, the food length data decremented by "1" from the length of the decoding processing unit, and the run length for the code block. Output data, and for the code part of 7 bits from the first bit of the black run make-up code or black run terminate code of 7 bits or more, if "O" continues for 5 bits or less from the first bit, it is considered as next state data. ,
It outputs code length data of “4n” and run length data of “0”, and when 6 or more bits of “0” continue from the first bit, it outputs the next state data, code length data of “6”, and run length data of “OI+”. Run length data is output, and next state data and 6n are output for the first 7 bits of the uncompressed mode start code and fill skip code.
The code length data of 'O' and the run length data of 'O' are output.

The one-dimensional black 2 code table is as follows for the code part after the 7th bit when "O" continues for 6 or more bits from the first bit of a black run make-up code or black run termination code of 7 bits or more. Outputs state data, code length data decremented by 1 from the decoding processing unit length, and code block run length data, and outputs the uncompressed mode start code, EOL code, and the 7th bit of the fill skip code. For subsequent code portions, next state data, code length data decremented by "1" from the length of the decoding processing unit, and run length data of "0" are output.

The one-dimensional black 3 code table is a black run make-up code of 7 bits or more or a black run termination code of 6 when 5 bits or less of "0" continues from the first bit.
For the code part after the bit, the next state data,
Code length data decremented by 1'' from the length of the decoding processing unit and run length data of the code block are output.

The two-dimensional code table contains the next state data for the vertical mode code among the two-dimensional codes, the code length data decremented by 1'' from the length of the decoding processing unit, and the run length data of the code block. The corresponding data is output, and for the bus mode code among the two-dimensional codes, the next state data, code length data decremented by "1" from the length of the decoding processing unit, and a predetermined code are output. Outputs the horizontal mode identification code and the next 7-bit ri On that is continuous with the next state data and “1” from the length of the decoding processing unit.
Outputs code length data decremented by 0 and run length data of "0".

For uncompressed mode data, the uncompressed mode code table contains the next state data and the length of the decoding processing unit.
Outputs the code length data decremented by ``, and the length data of the decoding processing unit as run length data, and outputs the next state data and the length of the decoding processing unit for the uncompressed mode end code by 1'' from the length of the decoding processing unit. The decremented code length data and the run length data of "0" are output.

The special code table contains the first 8 bits of the EOL code at the beginning of the page in decompression processing mode, and the next state data for the code part after the 9th bit, and only 1 from the length of the decoding processing unit. Outputs the decremented code length data and run length data of "On", and outputs next state data, code length data of '0', and run length data of 'O' for the tag pit following the EOL code. For the fill-skip code, output the next state data, the code length data decremented by "1" from the length of the decoding processing unit, and the run length data of 'Opa,
For image data in the compression processing mode, food length data that is decremented by "1" from the length of the decoding processing unit and length data of the decoding processing unit are output.

Next, the operation of the decoding processing section subsequencer 8 will be explained with reference to FIG. Here, the number attached to the arrow indicates the next state data that is output when the table is referenced.

A special code table is referred to to decode the EOL code at the beginning of the page in decompression processing mode.

When the EOL code at the top of the page is decoded, in the MH expansion processing mode, the one-dimensional die 1 code table is referenced at the top of the line.

White run makeup code of 8 bits or less is one-dimensional mortar 1
When decoded as a unit of decoding processing in the code table, and when the run length is 1728 or less in the one-dimensional mortar 2 code table, 9
When the code part after the 3rd bit of the white run make-up code of bits or more is decoded as a decoding processing unit, and when the black run termination code of 7 bits or less is decoded as a decoding processing unit in a one-dimensional black 1 code table. and when "o°" continues for 6 or more bits from the first bit of the black run make-up code of 7 bits or more or the black run terminating code in the one-dimensional black 2 code table, and the white run make-up of 8 bits or more. When 6 or more bits of "0" continue from the first bit in the code, when the code part after the 7th bit is decoded as a unit of decoding processing, and when there is a black run makeup code of 7 bits or more in the one-dimensional black 3 code table. Alternatively, when five bits or less of "0"s continue from the first bit in the black run terminated code, when the code portion after the fifth bit is decoded as a unit of W1 reading processing, the one-dimensional mortar 1 code table is referred to.

When the code part up to the 7th bit of a white run makeup code with a run length of 1792 or more and 9 bits or more is decoded as a unit of decoding processing in the 1-dimensional 1-dimensional code table, the 1-dimensional 2-code table is referred to. .

When a white run make-up code or a white run terminate code is decoded in the 1-dimensional mill 1 code table and the 1-dimensional mill 1 code table, the 1-dimensional black 1 code table, the 1-dimensional black 2 code table, and the 1-dimensional black 3 code When the black run makeup code is decoded in the table, the one-dimensional black 1 code table is referred to.

When a white run make-up code with a run length of 1792 or more is decoded in the 1-dimensional mortar 1 code table, and 1
In the dimensional black 1 code table, when the code length is 8 bits or more and the 7 bits from the beginning of the black run make-up code or the black run terminated code with 6 or more bits (0) from the beginning are decoded as a unit of decoding processing. When the first "7" bit "O" of the EOL code, fill-skip code, and uncompressed mode start code is decoded in the 1-dimensional mortar 1 code table and the 1-dimensional black 1 code table, the 1-dimensional black 2 code is decoded. A table is referenced.

In a one-dimensional black 1 code table, when the black run make-up code and the black run termination code are followed by ``5'' bits or less (0) from the beginning, when ``7'' bits from the beginning are decoded as a unit of decoding processing, the 1-dimensional The Black 3 code table is referenced.

When the uncompressed mode start code is referred to in the one-dimensional black 2 code table, the uncompressed mode code table is referred to.

When the non-compressed mode end code is decoded in the non-compressed mode code table, the one-dimensional mortar 1 code table or the one-dimensional black 1 code table is referred to according to the tag pit.

In the MR and MMR decompression processing modes, the two-dimensional code table is referenced at the beginning of the line. The two-dimensional code table is also referred to when a two-dimensional code is decoded as a unit of decoding processing and when a black run terminated code is decoded.

When the horizontal mode identification code is decoded using the two-dimensional code table, the one-dimensional mortar 1 code table is subsequently referred to. For horizontal mode codes, horizontal mode identification code,
A white run make-up code, a white run terminate code, a black run make-up code, and a black run terminate code are arranged in order. Therefore, MR method and MM
When decoding a horizontal mode code using the R method, there is a difference compared to the MH method. For example, when a white run makeup code is decoded, the one-dimensional black 1 code table is not referenced. Further, after the black run terminate code is decoded, the two-dimensional code table is referred to.

Next, the operation of the generation processing section 14 in the decompression processing mode will be explained.

The reference line data from the reference line buffer memory 2 is stored in the register RREF 180.
6 to the 19-26 bit part as data G4.
Each byte is input. Register RRE F 18
0 means that the control section 4 is used when inputting reference line data.
The reference line data held is shifted in byte units to the left, that is, in the LSB direction, according to a control signal from the controller. That is, data REF08-10 is data R
Data REF11-18 to become EFOO-02
are shifted so that they become data REF03-10, and data REF19-26 become data REFII-18.

After that, new reference line data is set to data RRE1”1.
Enter as 9-26.

The funnel shifter 182 receives data RRE FOO-21 from the register RREF180. centre? The channel shifter 182 is supplied with the aO pointer data RBPAO2-00 from the register RBPA200, and selects 15 bits of data in the MSB direction from the bit position indicated by the pointer data RBPAO2-00 from the input data RRE FOO-21. and data 5H
Output as TPOO-14. In the case shown in FIG. 26, conventionally, bl in the reference line has been detected in byte units. Therefore, two processing steps were required to detect the b1 point.

However, in this embodiment, when point b1 is detected within 1 byte length from the bit position of 80 points, only one processing step is required. The currently focused reference line byte data corresponds to data RRE FO4-11 held in register RREFOO-26.

Here, the data RRE FOO-14 is selected in consideration of the color change point in the vertical mode.

Data 5HTPOO-14 is input to color inversion circuit 184. The color inversion circuit 184 is also supplied with data M9 from the Ill 111 section 4 to unify the direction of color change of the pixels. That is, in this embodiment, since the detection direction of color change is from white to black, the direction of color change is unified by the internal exclusive OR gate. Therefore, when detecting a color change from white to black, "0" is supplied as the control data M9, and when detecting a color change from black to white, "1" is supplied. Data 5HTP00-14 in which the direction of color change is unified is output as data DRENOO-14.

The change point detector 186 receives the data DRENOO-14 from the color inversion circuit 184 and converts the color change point into data “O”.
The data is output as data DRECO1-14 shown in FIG. In addition, in Fig. 16, * is “0”
or 1''. Here, the data DRECOI-14
is -3-10 of the target block of the current decompression processing line
corresponds to That is, the data DRECO1-14 are
At the bit position of the block of interest in the current decompression line, “
4” added.Data DRECO1-14
FIG. 16 also shows the correspondence between this and the bit position of the block of interest in the current processing line.

Data DRECO1-14 are input to a priority encoder 188, and color change points are detected.

That is, in the case of a fine checkered pattern, a plurality of color change points may be detected, and in that case, the leftmost color change point, that is, the color change point in the LSB direction is detected. The bit position of the detected color change point is shown in Figure 16 as data B1DTO3-0.
It is converted into a binary number and output as shown by 0.

Next, the case of two-dimensional expansion processing will be explained.

In the two-dimensional code expansion processing mode, data RNLC03-00 is supplied from the decoding processing unit 12 to the selectors 201 and 212 as data B3. Further, data M11 is supplied to the selector 201 from the 1111111 section 4. This data M11 is 1-bit data indicating whether the mode is a two-dimensional code decompression processing mode or a one-dimensional code decompression processing mode, and is (1) in the case of the two-dimensional code decompression processing mode.

The filter 204 receives data RNL from the selector 201.
Data RBPAO from CO2-00 and selector 202
2-00 is supplied, and the sum of these data is calculated to obtain data AOPLO3-00.

Since we are currently explaining the two-dimensional code decompression mode, data AOPLO3-00 is AOPLO3-00.
3-00 -(0) RBPAO2-00+ (1) RN LC
O2−00−aO+(δ−4)・−δ−4+aO. Data A OP LO3-00 is selector 20
6 to an adder 210. Adder 210
Also, the data BIDTO3 is sent via the selector 208.
−〇〇 is also supplied. Those data are added and
The addition result ADL TO3-00 is obtained. Data ADLTO3-00 is A B 1 AO3-00 -BI 0T03-00+AOPLO3-00-(bl
+4-ao) + (δ-4+ao)-b1+δ. This data A B 1 AO3-00 is sent to register RBPAO2-00 and register RBP0176 via selector 198. At the same time as the above processing, the generation and combination unit 22 completes generation of image data for the run length.

On the other hand, the adder 216 is supplied with data RN L CO3-00 via the selector 212 and data B 1 D TO3-00 via the inversion circuit 214 . Here, the inversion circuit 214 passes the input data B 1 D TO3-00 in the decompression processing mode. Adder 2
16 is the addition result ADL TO from these data.
Get 3-00. Data ADLTO3-00 is ADLTO3-00 -B 1 D TO3-00+RN L CO3-00
-(b1+4-aO) + (δ-4)-b1+δ-a
It becomes O -at -aO. When ADLTO3-00 is 8 or more, data F2 is output to the 111111 section 10, and it is notified that the generation of image data has been completed in the byte block of interest.

Next, a description will be given of decompression processing for a one-dimensional code and an uncompressed code with a run length of less than 1 byte.

The run length data of less than 1 byte of the one-dimensional code is transferred from the register RNLC126 to the selector 2 as data B3.
01 is input. Data M1 from 611111 part 4
1 is (0) in this case, as described above. Data from this selector 201 is supplied to an adder 204. Adder 204 is also supplied with data RBPAO2-00 from register RBPA200. The addition result of these data AOPL03-00 is AOPLO3-00 - (0) RBPAO2-00+ (0) RNLCO2-
00-ao+RL. Here, "aO" indicates a hit position of 80 points, and "RL" indicates a run length of 1 byte or less.

This data AOPLO3-00 is supplied to the adder 210 via the selector 206. The adder 210 is supplied with data (11111) selected by the control signal from the control unit 4 from the selector 208.

Therefore, the addition result AB1AO4-00 is ABIAO4
-00 m 11111 + “0” AOPLO3-00+
1- “O” AOPLO3-00 -ao+ RL. Here, the adder 210 further adds "1" to the result of addition between input data.

AB1AO2- of this addition result AB1AO4-Go
〇〇 is the register RBPA20 via the selector 198
0 and further via selector 174, register RBP
0176.

The above description of the one-dimensional code decompression process can be directly applied to uncompressed codes.

As described above, the length of the image data to be generated and the position of the generated pit in the byte block of interest are determined.

Next, the operation of the generation and combination unit 22 during decompression processing will be explained.

First, the decompression process for one-dimensional codes and two-dimensional codes will be explained.

In the image data generation process for run length data of 1 byte or more, the selector 160 selects the data ( 11111111) or (00000000) is selected and the data ECDPO
It is output as O-07. Selected data E CO
POO-07 is input to barrel shifter 164. Data RBP QO2-00 is output to the barrel shifter 164 from the register RBP Q 176. This data indicates the next bit position of the bit position in the byte block of interest whose generation has been completed in the immediately previous generation step. In the barrel shifter 164, the data ECD
PO7-00 is rotationally shifted according to pointer data RBPQO2-00 and output as data 5HTGOO-07.

Data S HT GOO-07 is supplied to the 08-15 bit portion of the selector 166 and register 168 for data combination. The selector 168 is supplied with the remaining part of the image data already generated from the selector 170. When image data generation processing is executed in byte units and data ADI T 03-0
When the third bit of 0 is 1, the 0 of register 168 is
Data in the 8-15 bit portion is selected; otherwise, data in the 00-07 bit portion is selected.

The selector 168 also includes a pointer register RepQ1.
Data RBPQO2-00 is supplied from 76,
Input data selected according to data RBPQO2-00 is combined. That is, the data from the selector 170 is selected as the bit data from the first bit position to just before the bit position specified by the data RBPQO2-00, and the data from the bit position specified by the data RBPQO2-00 to the last bit is selected by the barrel shifter 164. data from is selected.

For example, if generation processing is performed in bytes, data RBPQO2-00 is "3", and data 5HTGO
Assume that O-07 is (1111111111') and data RODTO8-15 is (10000000). At this time, the output EPCKOO-07 from the selector 166
becomes (10111111). The data EPCKOO-07 obtained in this way is stored in the register 168 at 00-
It is stored in the 07 bit part.

When image data generation processing is being executed in byte units and when the third bit of data ADL TO3-00 is 1, it is assumed that the image data generation processing for 1 byte has been completed, and control is executed. According to the control signal from unit 4, data RODTOO-07 is stored in register 172.
It is output to the outside (image memory) via. Also,
Data RODTOO-07 is stored in reference line buffer 7 memory 2 via selector 238 as data D1.

While the image data generation processing operation described above is being performed, data RBPQO2-00 cannot be changed. This is because processing is done in bytes, so there is no need to change it.

Next, image data generation processing for run length data of less than 1 byte of a one-dimensional code will be described.

Image data is generated in register 168 in exactly the same manner as described above. The difference from the byte-by-byte processing described above is that when the image data combined by the selector 16G is stored in the register 168, the data RBP
This means that QO2-00 is updated based on data DBPAO2-00.

Next, image data generation processing for run length data of a two-dimensional code will be described.

If point b1 is not detected, byte-by-byte processing is performed in the same manner as described above until point b1 is detected. b1
When a point is detected, the image data generation process for the vertical mode code is performed in the same way as the image data generation process for run length data of less than 1 byte.

The image data generation process for the pass mode code is similar to the image data generation process for the vertical mode, but the color of the image data selected by the selector 160 is changed before and after the bus mode code. Selected not to.

Next, the decompression process of the uncompressed mode code will be explained.

Data SHT D output from Huhnel shifter 104
00-07 are connected to the register R via the color inversion circuit 106.
It is latched in the PAT 162 as data RPATO7-00. This data RPATO7-00 is selected by selector 160 and supplied to barrel shifter 164. The subsequent generation process is similar to the image data generation process for run length data of less than 1 byte.

Next, the compression processing mode will be explained.

In the compression process, 81 points and b1 points are detected. The detection processing of the 81 points is performed by the decoding processing section 12. The b1 point detection process is performed by the color change point detection section 36. The corresponding code is then generated using the detected 81 points and the b1 point.

First, the detection process for 81 points will be explained.

In the compression processing mode, the register RBPP 116 receives data DBP from the control unit 10 via the selector 114.
AO2-00 is supplied and set to the initial value "7" (111). Therefore, the Huhner shifter 104 converts the data RD T I 16-23 into the data 5HTD 00-0
Output as 7. Control data M1 is supplied from the control section 4 to the color inversion circuit 106 in order to unify the direction of color change. As a result, in this embodiment, the direction of color change of pixels is unified from white to black. Color inversion circuit 106
The output DTISOO-07 is supplied to the selector 110 in the same way as the mask gate 108.

Data RDSQO4-00 is supplied to the selector 110 from the control unit 10 as data M3. This data RDSQO4-00 is (111) in the case of compression processing. The selector 110 is also supplied with data DND POO-07 as data M2 from the ilJ'11 unit 10. This data DND POO-07
is data for supplementing a virtual change point 1 bit to the right of the end point of the line. Normally, this data DNDPO
Each bit of O-07 is (0), and when processing the end of the line, only the bit position to the right of the end point of data DND POO-07 is (1). This data DND POO-07 and data DTIS00-0
The data logically summed with 7 is combined with the mask data from the mask gate 108 to generate data DRMA.
Output as 10-00.

Address data DRMA10-00 is decoder ROM1
12. supplied to The decoder ROM 112 decodes this data DRM A 10-00 and stores it in the data DROM.
Outputs 11-00. The decoding result at this time is shown in FIG. 14e. In FIG. 14e, M indicates mask data, and x is (0) or "1".

In the case of compression processing, bits 11.10.09.05 of data DROM 11-00 are not used. data DR
OMO8-06 includes adder 122 and run length calculation unit 3
bit data DROMO4 is output to the control unit 4, and data DROMO3-00 is output to the counter unit 30.
is output to. With reference to FIG. 14e, the data DROM
In O8-O6, a value obtained by subtracting 1 from the length of the decoded image data (run length - 1) is shown. The bit data DROMO4 includes a selector 114, a register 116,
In the decoding pointer circuit consisting of the adder 122, it is used as data for determining whether to count or not. When 81 points are detected, bit data DROM
O4 becomes (0), and when 81 points are not detected, it becomes (1).

In the adder 122, as in the decompression process, the data R
8P PO2-00 and data DROMO8-06 are added, and data "1" is added. As a result of this addition, when bit data ABPPO3 becomes “1”,
This is notified to the 11110 section 4 as data 86. The control unit 4 receives new byte image data into the register 102 according to the data 86. When bit data ABPPO3 is (0), processing continues as is.

On the other hand, the color change point detection section 36 detects point b1.

Register 180, Huhnel shifter 182, color inversion circuit 1
84, the change point detection circuit 186, and the priority encoder 188 operate in the same way as in the decompression process. The data of the detected b1 point is output as BIDTO3-〇〇.

In the compression processing mode, the same is true except that the selector 114 selects the data DBPAO2-00 from the village change point detection unit 36. However, if point b1 is found within 1 byte from point 80 during the compression process, a pass test starts, data corresponding to (bl-ao) is latched into register RP1L118, and the aO pointer data becomes b
Advances to one bit position. Then, the runs of the same color are counted in bytes. When the bus test results in one-dimensional encoding, the latched data RPi 102-00 is selected by the selector 120 and output to the adder 122. The adder 122 receives data DRO from the decoder ROM 112, which is less than 1 byte and whose run length is decremented by "1".
M 08-06 is supplied. "1" is further added to this addition result. Final addition result ASPPO
2-00 is output to the generation unit 32 and used for one-dimensional encoding.

When encoding is completed, the aO pointer data is updated as follows. Data RBPAO2-00 indicating 80 points held in register RBPA200 is selected by selector 192 and supplied to adder 196. The adder 196 receives data DR via the selector 194.
MO8-06 is also supplied.

The adder 196 performs the following calculation, and the data A
I0MO2-00 is obtained.

A 10MO2-00 -RBPAO2-00+DROMO8-06+1=aO
+ (al-aO-1) + 1 That is, data A1CM 02-00 indicating 31 points is obtained in this way. Data A I 0MO2-00 is register RB
P A is set to 200, and the decoding processing unit 12
is supplied to the selector 114 of. In this way, in the compression processing mode, 80 points are updated in the color change point detection section 36.

When two-dimensional encoding is to be performed, the run length is determined as follows. In the run length calculation unit 38, the data B 1 D TO3-00 is supplied to the adder 216 via the inversion circuit 214.

In the selector 212, the data DR from the decoding processing unit 12
OMO3-00 is selected and provided to adder 216. The adder 216 performs the following calculation to obtain data ADL TO3-00.

A D L TO3-00 One inversion (B 1 DTO3-00) +DROMO3-
00+ 1=inversion (b1+ 4-aO) + (al-
ao) + 1- al -bl -4 - δ-4 In other words, in the inverting circuit 214, input data B1D
Inverting T03-00 and adding 1" in the adder 216 is the same as calculating the two's complement of data B1DTO3-00. Data A obtained in this way
Data ADLT 02- of D L TO3-00
00 is output to the generation unit 22.

In the counter unit 30, each time image data is encoded, the selector 124 receives data “2556”.
”(100111111100) is selected and set in the register RNLC126.This data RN L
Of C11-00, data RN L C11-03 is sent to the adder 130. In the adder 130, the data R
The NIC 11-03 is decremented by "1" and supplied to the selector 124 again. Also, data RNLC
II-03 is supplied to the comparator 128, and 'O゛(
ooooooooooo) is checked.

When the data RNLC11-03 is equal to "0", the control unit 4 is informed by data B4. In this way, the run length counter circuit processes one byte at a time.

When “ON” is detected by the comparator 128 and the same color run continues, the data held in the register RNUC 134 is incremented by “1”. Selected.

The value of register RNUC 134 is latched into register 140 via selector 138. Run length “25”
1 every time the court data corresponding to 60 is generated.
” is decremented. The comparator 144 checks whether the decremented result matches “ON”.

The generation unit 32 receives data ANL00 from the counter unit 30.
8-00 from the decoding processing unit 12 as data ABPPO2-
〇〇 is input and supplied to the register RNLG148. Data RNL held in register RNLG148
Of G11-00, data RNLG11-06 and data RNLGO5-00 are supplied to the selector 156.

Further, 6-bit data RNLGII-06 is supplied to the comparator 150. The comparator 150 is used in the one-dimensional code compression processing mode, determines whether the input data RNLG11-06 matches the data (100111), and notifies the control unit 4 of the result using data C2. The control unit 4 determines that the code word to be generated is a make-up code when they match, and determines that the code word to be generated is a termination code when they do not match.

The selector 152 is supplied with data ADL TO2-00 from the run length calculation section 38 and data EGCDO3-00 from the control section 4. Selector 152
For data EG CDn3-00, data (
1) and data (01) are supplied for data ADL TO2-00. 2D code compression 51
1! In the mode, data ADL TO2-00 is selected, and in the case of a horizontal mode identification code or pass mode code, data EGCDO3-00 is selected.

The selected data DGCDO4-00 is stored in register 15.
Selector 1 as data RGCDO4-00 via 4
56.

As shown in FIG. 17a, the selector 156 is supplied with bit data DBLJG from the control unit 10 indicating whether a code word of either white or black color is to be generated. This bit data DBLK is used when generating a one-dimensional code, and is “0” for white and “0” for black.
1''.The selector 156 also contains bit data F.
2NG is supplied. Bit data F, 2 N
G is data for distinguishing between the first access and the second access when the decoder ROM 158 is accessed twice when the code to be generated is 9 bits or more. Data F2NG is 1 when accessed for the second time.
”.

The selector 156 sets data ERMAO8-00, and in the case of makeup code generation, data RNLG1.
1-00, data RN L GO5-00 is selected when generating a termination code, and data including data RGCDO4-00 is selected when generating a special code.

Data ERMAO8-00 is encoder ROM158
added to. Data FROMII-00 is output from the encoder ROM 158. Data FROM11
The output format of -00 is shown in FIG. Here, the bit data EROM11 is data for indicating whether or not the generation step is the final step; (1) indicates the final step, and (0) indicates the next generation step to generate the corresponding code data. Indicates that a step is required.

Data indicating the length of the generated code portion (-1) is output in the 10-08 bit portion. This data ERO
MIO-08 is provided to adder 178. Data FR
The code generated by OMO7-00 is output.

Data FROMO7-00 is supplied to barrel shifter 164 via selector 160. The subsequent processing in the hold loop circuit is the same as the decompression processing. The difference is the operation of the generated pointer data holding circuit.

The generation pointer data holding circuit stores data FR from the encoder ROM 158 in parallel with the generation of code data.
Generated pointer data is updated according to OM10-08. That is, in addition B178, the held generated pointer data and data EROM 10-08 are added. #1re is further added to the addition result.

Final addition result A B P AB out of QO3-00
PQO2-00 is sent to register RB via selector 174.
It is held in P017B and becomes new generated pointer data. When data ABPQO3 is (1), it is assumed that 1 byte worth of copy data has been generated, and data D is sent to control unit 4.
You will be informed at 3. As a result, the code data held in the 00-07 bit portion of register RDT1168 is output.

As described above, in the compression processing mode, the generated pointer data is updated based on the data EROM 10-08. Therefore, as shown in Figure 17, if 8-bit code data is output in the second generation step, there is no need to update the generated pointer data, and the compression process can be sped up. .

Next, the operation of the generation processing section subsequencer 9 will be explained with reference to FIG.

When encoding using the MH method, a one-dimensional code is generated by transitioning from the H code state to the makeup state, 2560 code state, or termination state. When the generation of the one-dimensional code is completed, the H code state is executed again. Thereafter, the above operations are repeated until the line ends. When the end of the line is reached, the termination state is changed to a special state, and an EOL code or fill-skip code is generated. After that, it returns to the reset standby state.

In the MR to MMRMR dimension generation processing mode, 81 points and b are set at the beginning of the line from the reset standby state.
Detect the position of one point. When 81 points are detected but b1 point is not detected, a special state is entered and a horizontal mode identification code is generated. Thereafter, a white run make-up code and a white run terminate code are generated in the same manner as in the MH method. Subsequently, a black run make-up code and a black run terminate code are generated again from the H code state.

After that, the 81st point and the b1 point are searched again.

b1 point is detected but 81 points are not detected,
Enter the bus test. If 81 points are not detected, it moves to a special state. A bus code will be generated.

When point 81 is detected at a location 3 bits or more away from point b1, a one-dimensional code is generated in the same manner as described above.

When the 81st point is detected within 3 bits from the b1 point, the state shifts to the (2) code state and a two-dimensional code is generated.

In the MR method, like the MH method, when the end of the line is reached, a special state is entered and an EOL code or fill-skip code is generated.

Also, at the end of the page, a special state is entered in order to generate a predetermined number of EOL codes.

Next, the decompression process in the uncompressed mode will be explained using the flowcharts shown in FIGS. 19 to 21.

In this example, the process starts with decompression processing of MH encoded code data, and changes to uncompressed mode decompression processing midway through. Note that the register RMPC (not shown) is an instruction register, and instructions latched therein are written in each step.

The compression/decompression processing device draws a loop in steps S2 and 84 corresponding to clocks #0 to #3, and waits for data input in an initialized state immediately after power is turned on. This state continues as long as no data is input. Note that the initialized values of each register are shown in clock #O. In this state, the decoding processing unit subsequencer 8 is also in a reset state.

In step S6, when data is input, page control is initialized. The first data sent is control data, which indicates whether the mode is compression processing mode or decompression processing mode, and whether the encoding method is MH or M.
It includes data indicating whether it is Rl or MMR, run length data per line, and the like. Here, it is assumed that the decompression processing mode is selected using the MH method. Further, run length data per line is set in register END8218.

Further, inside the compression/expansion processing device 1, initialization of page control is performed, such as setting a register FBLKD for specifying a color to white. Clock #4 of step S6
Then, set “00” (oooooooooo) as data A1.
) is set in register RDIN (not shown).

In step S8, it is determined whether the mode is compression processing mode. When the compression processing mode is designated, the compression processing is executed, and when the decompression processing mode is designated, the process advances to step S10.

Currently, the decompression processing mode for code data encoded by the MH method is specified, so step 810
Proceed to.

At step $10, at clock #5, register R
The data held inside the DT 1102 is shifted by 1 byte in the LSB direction. Thereafter, input data A1 is transferred from register RDIN to register RD T I 102. Here, since the input data is [00, the value inside the register RDT 1102 does not appear to change by 1.

In step S12, it is determined whether the MMR encoding method is used. If it is the MMR encoding method, the flow advances to step S22 and DLNLOOP is executed. Otherwise, flow continues to step 314. Since this operation description uses the MH encoding method as an example, the flow advances to step S14.

In step S14, at clock #6, the decoding processing section sub-sequencer 8 issues a startup instruction to the decoding processing section 12, and EOL search A is executed.

Therefore, input data is skipped up to the EOL code. At the same time, the value of register RBPP116 is updated to "7", and the next input data [OC
] (00001100) is set.

Since the decoding processing unit subsequence 8 is in the EOL search A state, in step 816, the input data [Q Q 3 (00000000) is decoded by the decoder DROM 112 with reference to the special code table at clock #7. As a result, data DROM 11-0
9IC data (001) is data DROM 08-
For 06d, "7" (111) is output.

Based on this "7" data, register RBPP116
The decryption pointer data held in the decryption pointer data is updated. That is, the output ABPP of the adder A122 becomes ABPPO3-00-111+111 +1, and the decoding pointer data of the register RBPP116 becomes "7" again.
''. Furthermore, the control unit 4 is informed by data 80 that the third bit is (1).

As a result, at clock #8, the data held in the register RDT 1102 due to the overflow of the adder 122 is shifted by one byte in the LSB direction, and data [OC] is placed in the data RDT 116-23 portion.
(00001100) is input. Also, register R
DIN contains the following data [70] (01110000)
is input.

The decoding processing unit subsequencer 8 is a data DROM 11-0.
9 (001), the program moves to EOL search B and executes EOL code determination processing. The data held in register RDT1102 is [0000QC] (0000
00000000000000001100),
Since the 09-23 data part is input to the Huhnel shifter 104, the data (000000000001
100) is input to the Huhnel shifter 104. Since the value of register R8PP116 indicates "7", the decoding target is (00001100). This corresponds to [OC] in register RD T I 102. Output DROM 11-00 from decoder ROM 112 for this code data, [DO5] (1101
00001001) There are r. Therefore, the decoded code length is (100) for DROMO8-06, which is “1”
The EOL code is determined at the 5th bit from the bit position specified by the decoding pointer data RBPPO2-00. Also,
Data [OC] is output to register RPAT162.

At clock #9, the adder 122 outputs data R8.
“7” of P PO2-00 and data DROMO8-06
Data “12” is obtained from “4” in the same manner as above.
(1100) is obtained. The third bit "1" is notified to the control section 4. As a result, the data RD T I 0
0-23 is shifted by one byte in the LSB direction, and 16-
The 23-bit part contains data [70] (01110000
) is input. Also, decryption pointer data RBP
PO2-00 is updated to "4" based on the addition result. Currently, data RDTI08-23 is (0000110
001110000) and data RBPP02-0
Since 0 is "4", data 5HTDOO-07 is (10001110). As a result, the decoding result shows 1 bit, which means a tag pit.

The decoding processing unit sub-sequencer 8 is in the EOL fixed status, and the next data [OF] is in the register RDIN.
(00001111) is set. Register R
PAT162 receives data RB at clock #9.
Register RDT 1102 based on P PO2-00
The data retrieved from [0(,] is latched, but this value is not used since we are not in uncompressed processing mode.

In step 818, it is determined at clock #10 whether the MR encoding method is applied. M.H.
If the encoding method is not selected, then DLNLOOP is executed. In the case of the MR encoding method, step S20 is executed. Also, the register RPAT162 has a clock #.
9 decrypted pointer data RB P PO2-00
Data [8E] extracted based on "4" is latched, but this is also ignored. In step S20, a tag pit is taken in at clock #11 and set in a register TAG flip-flop (not shown). Flow then proceeds to DLNLOOP.

DLNLOOP begins at clock #12.

At clock #12 of step S22, an internal FF (flip-flop) is initialized for line control, and decoding pointer data RB P PO2-00 is updated to "5" upon completion of tag pit processing.

Furthermore, the area of the reference line buffer memory 6 is switched. As a result, the data M supplied to the selector 232
15 is switched. Also, line-by-line control begins.

At clock #13 of step S24, data RD
TIO&-23 (0000110001110
000) and data RB P PO2-00 “5” to data [1C] (00011100) are stored in register RPA.
It is latched to T162. Furthermore, the generated pointer data RBPQO2-00 held in the data output control pointer register RBP0176 is reset to "ON".

In step 826, the reference line buffer 7 memory 6
It is determined whether it is necessary to clear the contents of.

If clearing is not necessary, step S34 is subsequently executed. When clearing is necessary, the register 226 holding the reference line address is reset and
” is initially set.

Thereafter, step 828 is executed. Although not necessary in the current process, the operation will be explained.

In step 828, the data RBFA10-00 from the register RBFA226 is added to the data "4" from the selector 236, and the data RBFA10-00 from the register RBFA226 is added to the data "4" from the selector 236 as address data.
32 and a register 234 to the reference line buffer memory 6. The selector 238 selects data (000
00000) is selected and the reference line buffer memory 6
supplied to In this way, the location of address "0" is cleared. After that, the data RB F A
10-00 is incremented by "1" by adder 228. The incremented data is provided to selector 232 and used to clear the next location.

In step S30, it is determined whether the location in the reference line buffer memory 6 for one line has been cleared. If one line has not yet been completed, step 828 is executed again. If one line is completed,
Step 832 is executed and it is determined whether the decompression processing mode is in effect. In the compression processing mode, compression processing is executed.

In the decompression processing mode, step 834 is subsequently executed.

In step 334, RODTI68, which is an output data arrangement register, is initialized at clock #14. That is, it is set to [0000].

Furthermore, data RRE FOO-26 held in the reference line data register RRE F 180 is shifted in byte units. That is, data RREFO8-1
0 to data RREFOO-02, data RREF11
-18 is shifted to data RRE PO3-10, and data RRE F 19-26 is shifted to data RREF11-18. Thereafter, reference line data is read out from the reference line buffer memory 6 according to the reference line address from the buffer memory control unit 16.
It is latched into the 19-26 bit portion of register RREF 180. At the same time, the decoding processing section 12 is activated by the decoding processing section sub-sequencer 8, enters the one-dimensional white 1 code table (white A) state, and starts decoding processing. Further, the register RODTI88 is cleared to "0".

At step 836, at clock #15, data R
RE FOO-26 is shifted by one byte in the LS8 direction in the same manner as described above. Thereafter, the read next byte reference line data is input into the 19-26 pit portion. Also, at this time, the selector 192 selects the data (1
11) is selected and data (000) is selected by the selector 194.
are selected and added by adder 196. At this time, the adder 196 further adds "0", but the result remains unchanged. The data “7゛′” obtained in this way is
It is latched into register RBPQ176 as initial value data indicating the leftmost bit number of the block of interest. this is,
This is because the offset in the output data byte happens to be set to "7".

In step 538, the register RB P A 200 is set to the initial value "7" from the interface in check #16. That is, the register RB
It is set in the same way as data "7" is set in PQ176. Also, data RREFOO-26 is shifted by one byte in the LSB direction in the same manner as described above. Thereafter, the 19-26 bit portion Next byte reference line data is input.

Data RDT108-23 is “0C70” (00001
10001110000), but the data RBPP0
2-00 is "5", and the data DTIS00-07 whose decoding was started in step 834 is (00011100
). Of this data, (000111) is decoded as a white code (000111) with a run length of 1, and the decoder ROM 112 outputs [540] (010101000000) as data DROM 11-00. That is, since the decoded hood length is "6", "5" is output as the hood length data DROMO8-06. The data RB P PO2-00 is “5°”, therefore, the updated data RB P
PO2-00 becomes '3''. As a result, data RD
T100-23 are shifted byte by byte and placed in register R
Data [OF] in 16-23 bit part of DT1102
is latched. The next byte data [A4] is latched into register RDIN. Also, since the run length is “1”, it is “1” as data DROMO5-00.
(000001) is output to the generation processing unit 14.

After the decoding is completed, the next code is ``Fritsu'' and ``BufuOtsubu'' FBLKD, which is inverted based on the expectation that it will be a black code. As a result, the decoding processing section subsequencer 8 shifts to the state of a one-dimensional black 1 code table (black A).

In step S40, the main sequencer 7 enters an image generation step. Thereafter, the generation processing section 14 receives run-length data from the decoding processing section 12 and executes image data decompression processing until the processing of one line is completed.

At clock #17, the decoding processing section 12 decodes the next code data according to the decoding processing section sequencer 8. Now, data RD T 108-23 is (011
10000000011j1') and data RBP
Since P02-00 is “3”, the data (00000
000) becomes data SHTD 00-07, which is decoded by the decoder ROM 112. Since six or more "0"s continue, data (010) is output from the decoding processing unit sequencer 8 to the data DROM 11-09 so as to move to the one-dimensional black 2 code table (black B).

Furthermore, data "5" is output to the data DROMO8-06.

Subsequently, at clock #18, register RDT ■
102 executes a byte shift and inputs data [A4]. Furthermore, data [42] is input to the register RDIN. Data RB P PO2-00 becomes "1". Data RD T I 08-23 is (00001
11110100100) and data RBPP02
Since −00 is “1”, the next decoding processing unit (
001111) is found to be the latter half decoding processing unit of the uncompressed mode start code from the one-dimensional black 2 code table. This starts processing of the uncompressed code.

At clock #19, the decoder ROM 112 outputs -j' - T<101) from the DROM 11-09. Also, data RB P PO2-00 is 7
". Here, since the third bit of the output of the adder 122 is not "1 pass", the shift operation of the data RD T I 00-23 is not executed. Therefore, new byte data is also not input from register RDIN.

Data RB P PO2-00 has been updated to “7pa”, and at clock #19, data RDT11
6-23 [A4] is selected by the funnel shifter 104 and set in the register RPAT162. Since it is already in uncompressed mode, the register RPA
The data latched in T162 is transferred to the coupling unit 34 via the selector 160. In addition, at this time, data 5H
[A4] (10100100) of TDOO-07 is the address data silkworm [6A7 (
110101001-11>. Based on this address data, the decoder DROM 112 accesses the DROM 1l-OO as [9
46] (100101000110) is output. This is nothing but 6-bit batch processing of uncompressed mode data.

DROMO5-00 “6” registers RN at the next clock
Transferred to LC126. DROMO8-06"5°'
is originally a value that has been subtracted by “−1” and is supplied to the adder 122. That is, at the next clock, data RB
P PO2-00 becomes RBPPO2-00-7+5+1■13, (13
-8) becomes 5. This is register RB P P 1
This is because 16 is a 3-bit register. In this way, as the clocks are repeated, register RPAT16
2, [A4], [10], [08], [04], +I4→=: [08], [12], [2C] are latched. Further, the processing bit length defined by DROM 08-06 is similarly generated sequentially in register RNLC126.

This data RN L CO2-00 and aO pointer data RBPAO2-00 are added by an adder 204 to generate AOPLO3-00. This addition result AO
P L 03-00 is the selector 206 and the adder 210
, is fed back to register RBPA200 via selector 198. In this way, the data DBP
AO2-00 is updated. Further, the aO pointer data DBPAO2-00 is loaded into the selector 114 connected to the register RBPQ176. Therefore, registers RBPQ176 and RBPA200 have the same value. The generated pointer data RBPQO2-00 held in this register RBPQ174 serves as a pointer for the barrel shifter 164 and the selector 166 for data arrangement. After that, generated pointer data RBPQO2-0
Generation of image data will be explained based on 0.

Now, register ROD T 168 and ROUT17
Regarding the generation of image data in step 2, register R
The initial value of OD T 168 is set to [0000].

Since the aforementioned 1-bit white run is generated at clocks #17 to #19, at clock #20, the bits 00-07 of register RODT168 contain [000
0] is generated. Also, since the offset is 7, the generated pointer data RBPQO2-〇〇 has been updated from “7H” to “0”. Therefore, the register RoD
Data of bit 00-07 of T168 [0000]
is output as the completion of generation of 1 byte of image data. Further, data [A4] held in the register RPAT 162 is input to the coupling unit 34.

At clock #21, since data RBPQO2-00 is “OH”, data RODTOO-15 is “OH” and data [
A4A4] (1010010010100100)
becomes.

At the same time, data DROM 0 indicating the processed data length
8-06, data AB1AO4-00 is updated. Furthermore, the generated pointer data RBPQO2-00 is updated to "6".

Next, at clock #22, data RODToo-
Data in is [A4A4] Data RBP of (1010010010100100)
Bit point °゛6'' indicated by QO2-00
Position of Latte-9RPA TO7-00 (7) [10
] (00010000) is overwritten. As a result, data RODTOO-15 becomes [A440] (1
010010001000000).

Next, “4” of data RN L CO2-00 is added, and RBPQ-6+4-10 becomes 2. This is also due to the fact that register RBPQ 176 has 3 bits. Because an overflow occurred here, register ROD
Assuming that 1 byte of image data is completed in T168, [A4] of data RODTOO-07 is transferred to register Rot, 1T172. At this time, due to the external interface, the first completed data ``'oo''
Since there may be cases where this is not received, this proposal also uses an internal interlock to protect it, but this is omitted as it is not the main topic.

In this way, sequential processing continues, register ROU
At T 172, an uncompressed end code (00000010) is detected in the data [001, [A4], and the decoding unit changes the status to end of uncompressed mode.

In the manner described above, the image data shown in FIG. 22 is generated.

At clock #29, the non-compression mode processing is completed and an instruction from the main sequencer is awaited.

At clock #31, the process returns to the original code data processing.

At clock #32, the end code ends at "0", that is, the decoding sequencer moves to white A since the start is from the white code. However, since the input data is now an EOL code, the decoding processing unit control sequencer is white A.
- Black BF I LL Skip - Move to EOL detection. On the other hand, the main sequencer completes the processing of one line,
Repeat to process the next line.

When an image with the preset number of pits per line is generated, the flow starts at clock #38 in step S52.
Proceed to. Here, in the case of MH and MMR, the decoding processing unit 12
is decoding the EOL code. If EOL
If it is not a code, an error occurs in step 856. Then, in step 862, the decoding processing section 12 is restarted. At this time, the control signal MDECOD is output, and the 10th
As shown in the figure, the control signal DECO is sent to the decoding processing unit 12.
DE is input, and the decoding processing section 12 operates. If the code decoding result is not an EOL code, step 372
Then, the process returns to step S22, and the next line is expanded.

In addition, in the case of the MMR method, after the processing of one line is completed, if the next decoding result is not an EOL code, the process similarly moves to the next line. In this way, when the processing of one line ends and the processing moves on to the next line, step 866
Since the result of the decoding in step 868 is not an EOL code, the decoding processing unit 12 is in an operating state when the process moves to step 868. Therefore, Stellaf S68 Te II Jw signal MCH
The microinstruction DEC is output and the signal 5AFTY
- Even if it is "1", since the signal DECID is at level L, the control signal DECODE is not output.

In the MH and MR methods, in step 362, if an EOL code is detected as a result of restarting decoding (this is the second EOL detection), or in the MMR method, the EOL code is decoded after one line has been expanded. In this case, the control signal DECODE signal is present. When the I control signal 5AFTY is “0”,
Since the control signal DECODE is not output in step 868, it is assumed that an RTC (return control tIl) code is detected, and the process proceeds from step 872 to 384, and the decompression process for one page is completed. If the control signal @5AFTY is set to 1'', the control signal 0EDCODE is output in step 31 as shown in FIG.
The decoding processing unit 12 restarts. This decoding result is EO
If it is an L code, the RTC code is detected and the decompression process ends. If not an EOL code, step 374
876 is considered an error.

When the vtm signal 5AFTY is set as above,
In RTC code detection, one more EOL code than usual is detected. Therefore, if a 1-bit error occurs and a false EOL code is detected,
A restart can occur at step 868. Therefore, the decompression process will not be terminated due to a 1-bit error.

[Effects of the Invention] As described in detail above, according to the compression/decompression processing device of the present invention, when code data is generated twice, there is no need to update the generated pointer data in the second time.
Compression processing can be sped up.

[Brief explanation of the drawing]

The first factor is a block diagram showing the configuration of the compression/decompression processing device according to the present invention. FIG. 2 is a block diagram showing details of the decoding processing section shown in FIG. 1. FIG. 3 is a block diagram showing details of the counter section shown in FIG. 1. FIG. 4 is a block diagram showing details of the conversion section shown in FIG. 1. The fifth factor is a block diagram showing details of the coupling section shown in FIG. FIG. 6 is a block diagram showing details of the color change point detection section shown in FIG. 1. FIG. 7 is a block diagram showing details of the run length calculation section shown in FIG. 1. Figure 8 shows
2 is a block diagram showing details of the buffer memory control section shown in FIG. 1. FIG. FIG. 9 is a block diagram showing the detailed configuration of the change point detector. 10th
The figure is a block diagram showing the detailed configuration of the safety circuit within the main sequencer. FIG. 11 is a diagram showing the address format of the code table stored in the decoder ROM shown in FIG. 2. 1st
Figures 2a to 2d are diagrams showing which tables each include a make-up code and a termination code. 1st
FIG. 3 is a diagram showing the output format of the code table stored in the decoder ROM shown in FIG. 2. FIG. 14a is a diagram for explaining the meaning of the next state information in the output format of the code table shown in FIG. 13. FIG. 14 is a diagram for explaining the output format of run length data in the output format of the code table shown in FIG. 13. FIG. 14C is a diagram for explaining the output format of the vertical mode code shown in FIG. 14. Figure 14d is
12 is a diagram for explaining an uncompressed mode code table and a special code table shown in FIG. 11. FIG. Figure 14e
11 is a diagram for explaining the mask data shown in FIG. 11. FIG. FIG. 15 shows how the code table shown in FIG.
l]A letter to show what you want to do! ! ! It is a transition diagram. 16th
The figure is a factor for explaining the output of the color inverting circuit and the priority encoder. FIG. 11a is a diagram for explaining the operation of the selector shown in FIG. 4. FIG. 17 is a diagram for explaining the output of the encoder ROM. FIG. 18 is a state transition diagram showing how the generation processing section sub-sequencer controls the encoder ROM shown in FIG. 4. 19 to 21 are flowcharts for explaining the operation of the compression/expansion processing apparatus according to the present invention. FIG. 22 is a diagram showing how image data is generated according to the flowcharts shown in FIGS. 19 to 21. FIG. 23 shows the register R shown in FIG.
FIG. 3 is a diagram for explaining the function of PIL. Figure 24a
2A and 2B are diagrams illustrating an example of generation of image data in the first processing step of a line and the first processing step of a run. FIG. 25 is a diagram illustrating an example of run processing that spans byte boundaries. FIG. 26 is a connection diagram when static RAM is used as the reference line buffer memory. FIG. 21 is a connection diagram when a first-in-first-out (F I FO) memory is used in single buffer mode. Figure 28 shows FIF2
... Compression/expansion processing section, 4... Compression/expansion processing control section,
6...Reference line buffer memory, 12...Decoding processing unit, 14...Generation processing unit, 16...Buffer memory control unit Applicant's agent Patent attorney Takehiko Suzue Figure 3 [F] Nokuku MRD7 -0 Figure 6 Figure 8 1.
D+)≠(0,0)-(D3-D6.+) 1. -+4
)*Special Code Day Fool (DO, D+
)≠(0,0)−(D3.−,D7)=(1,−j
)(Do,-,Ds) l (0,-,0)-CD6.
07) = (L + )Figure 11 Figure 7, -1 Eye 2 Figure (b) Figure 24 (a) Figure 24 (b) Figure 25 Tortoise

Claims (1)

[Claims] One of input run length data and input first control data is selected, and generated address data is generated from the selected data and input second control data. generating address generating means for generating and outputting the generated address; and when the selected data is run-length data, generating code data for the color specified by the second control data according to the generated address data from the generated address generating means; When the generated and selected data is first control data, the means for generating code data according to the generated address data from the generated address generating means, wherein the code data to be generated is predetermined. When the length exceeds a predetermined length, the code data is divided into two outputs, and encoder means is configured to output the code data of a predetermined length in the second time. Device.