JPS63224518A - Majority decision circuit - Google Patents

Abstract

PURPOSE:To attain a high speed majority decision with a simple circuit by allowing each signal generating circuit to generate signals to be inputted to the circuit representing all 0s, the mixture of 0s and 1s or all 1s, adding them and comparing the result with a prescribed threshold level. CONSTITUTION:Inputs 1-6 being binary data a1-a6 are inputted to conversion circuits 7, 8 while forming one pair by every three-data. Outputs beta1, beta2 are signals representing all 0s, the mixture of 0s and 1s or all 1s. They are added by an adder 11 and its output S' is compared with a threshold level C'=2 by a comparator 13 to decide an output alpha', where the relation of a'=0 in the case of S'<=2 and alpha'=1 in the case of S'>2 is designated. Thus, the output of the majority decision is obtained at high speed with a simple constitution.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an electronic circuit that outputs "0" or "1" from a plurality of binary data using majority decision, and is used, for example, in error correction. This relates to a circuit used in the final processing section of a Vitabi decoder that performs the following steps.

[Conventional technology]

A Vitabi decoder, which is usually used in digital communication devices, is a device that receives convolutionally encoded data and decodes it using a maximum likelihood decoding method, and its circuit configuration is, for example, G, C, C1ark+Jr.

and J, B, Ca1a: “Error-Co
rrection Coding for Digital
l Communications”, P1e
nua+ Press (G, C.

Clark Jr. & J.B. Kane, Error Correction Coding for Digital Communications (Plenum Publishing) (
1981). The final processing section of the Viterbi decoder determines 1-bit decoded data from a plurality of binary data and outputs it.

In the process of this determination, a certain communication quality is guaranteed even if arbitrary data is selected from a plurality of binary data and used as decoded data. By the way, in order to achieve better communication quality without using a complicated circuit configuration, the above-mentioned document describes a method of determining decoded data from the plurality of binary data using majority decision. FIG. 4 shows a conventional majority decision circuit, which assumes six pieces of binary data. In the figure, al to a6 indicate six pieces of input binary data, 19a.

19b and 19c are 1-bit adders, 20a, 20b,
and 20C are 1-pint adders 19a, 19b, respectively.
and the output of 19C, 21 is the 2-bit adder, 22 is the output of the 2-bit adder 21, 23 is the 3-bit adder, 24 is the output of the 3-bit adder 23 (51) 3 is the comparator, 14a is the comparator 13 The threshold value C, 15a supplied to is the output data α of the majority decision result.

Next, the operation will be explained.

Binary data a1. ..., a6 inputs l, ..., 6 are connected to three 1-bit adders 19a, 1, each consisting of two adders.
It is input to 9b and 19c. 1-bit adder 19a, 1
The outputs 20a, 20b, 20c of the outputs 9b, 19c are 2-pin signals having a value of 0.1 or 2, respectively. next,
Output 20b of two 1-bit adders 19b, 19c,
20c is applied to a 2-bit adder 21 to produce a 3-bit output 22 having a value between 0 and 4. Output 20a of 1-bit adder 19a and output 2 of 2-bit adder 21
2 is supplied to a 3-bit adder 23 to produce a 3-bit signal 24 having a value of 0 to 6. In this way, the output 24 of the 3-bit adder 23 is the 6 input data al,...
・It is the sum of a6. Finally, this output 24 is judged by the comparator 13. The value of threshold 3 of the comparator is set to C-3, and if the output S of the 3-bit adder 23 is less than or equal to C, the value of the output data α (15a) from the comparator 13 is set to O, and so on. Otherwise, the value of α(15a'') is set to 1. That is, the majority decision result of . . . a6 is obtained as the output data α(15a) from the comparator 13.

[Problem that the invention seeks to solve]

Since the conventional majority decision circuit is configured as described above, it is necessary to use a large number of adders as circuit elements. For this reason, the circuit scale of the majority decision circuit becomes large, and a long processing time is required for the majority decision, which hinders high-speed operation of the circuit. This problem has the property of becoming particularly serious as the number of input data increases.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a majority decision circuit that can operate at high speed with a simple circuit configuration.

[Means for solving problems]

Each of the majority decision circuits according to the present invention has a plurality of two
decimal data is input, and all the data are “0”
or a mixture of “0” and “1”, or all “l”
a plurality of signal generation circuits that output signals indicating whether the A comparator that outputs .

[Effect]

In this invention, by having the above configuration, a signal is generated in each signal generation circuit to indicate whether the input data is all 10, a mixture of O and 1, or all 1. , by adding these multiple signals and comparing the result with a certain dark value, the output data of the majority decision is obtained, so there is no need to use many adders (therefore, the circuit configuration can be simplified). , capable of high-speed operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a majority decision circuit according to an embodiment of the present invention, and in the figure, al to β6 are six input 2
For each set of input data divided into 2 IIa sets, decimal data, 7.8 indicates whether the input data is a mixture of "01 cage 0" and "1", or whether it is all "1". A conversion circuit as a signal generation circuit that generates a signal, 9゜10 is the output β1, β of the conversion circuit 7.8
2.1) is a 2-bit adder that adds the output signals of the conversion circuit 7.8, 12 is the output S' of the 2-bit adder 1), 13
is a comparator 1 that compares the addition result S' of the adder 1) with a constant threshold value C' and outputs data of "0" or "1";
4 is a threshold value C' supplied to the comparator 13, and 15 is output data α' of the majority decision.

FIG. 2 shows one embodiment of the conversion circuit 7 in FIG.
6 is an AND gate, 17 is an OR gate, 18 is an exclusive OR (X-OR) gate, 9a, 9b are each bit β1 of the output β1 of the conversion circuit 7). This is an output terminal corresponding to β10.

Next, the operation will be explained.

Input of binary data al, . . . β6 1. . . 6 are input into two conversion circuits 7.8 in sets of three.

Output β1 of conversion circuits 7 and 8. β2 is 0, 1, respectively. or a signal with a value of 2. Now, suppose the 2-bit signal β1 is β1=(β1). β10), an example of the configuration of the conversion circuit 7 is shown in FIG.
It can be seen from FIG. 2 that if the number equal to "0" among a2+β3 is N, then β1 is given by the following equation.

Output β1 of conversion circuits 7 and 8. β2 is a 2-bit adder 1)
is added. The output S° of the 2-bit adder 1) is compared with a threshold value C'=2 in a comparator 13 to determine the output α'. Here, the truth table for this circuit operation is as shown in Figure 3.For example, (atta2, β3)
=001 means that only one of al, al β3 is “
1'', and FIG. 3 shows the output α (15) of the circuit of FIG. 1 according to the present invention and the output α' (15a) of the conventional circuit of FIG. 4. 3 (If!) to each conversion circuit 7, 8 as shown in FIG.
The two output data α' (15) and α(
15a) gives the same result.

By the way, considering the case where this majority decision circuit is applied to a Vitabi decoder, input data a1 +..., β6
A certain communication quality is theoretically guaranteed even if any one of them is selected. Therefore, even if the majority decision is incorrect with a small probability, the communication quality will hardly deteriorate.
This can be explained in more detail as follows. That is, input data a1. . . . Even if any value of +a6 is selected, a certain communication quality is guaranteed. This means that almost all of the input data is "θ" or "1".
This means that it is guaranteed that

This means that the probability of occurrence of an event in which the input data contains almost the same number of 0'' and 1) is sufficiently small.Therefore, the probability that the majority decision circuit of FIG. 1 according to the present invention will make an error is small. is small enough.

Finally, the circuit scale and maximum operating speed of the circuit shown in FIG. 1 according to the present invention and the conventional circuit shown in FIG. 4 will be considered. 1st
The circuit shown in the figure consists of four circuit elements: two conversion circuits, one adder, and one comparator, whereas the circuit shown in Fig. 4 consists of five adders and one comparator. It consists of six circuit elements called comparators. Therefore, assuming that all circuit elements are approximately equal in size, the circuit size of the circuit according to the present invention is approximately two-thirds that of the conventional circuit. Furthermore, the processing time of the circuit shown in FIG. 1 is given by the sum of the processing times of each of the three circuit elements: one conversion circuit, one adder, and one comparator, but the processing time of the circuit shown in FIG. The processing time of the circuit is given by the sum of the processing times of each of four circuit elements: three adders and one comparator. Therefore, assuming approximately equal processing times for all circuit elements, the maximum operating speed of the circuit according to the invention is approximately 4
/3 times.

In this embodiment, there is no need to use a large number of adders, and high-speed operation can be performed with a simple circuit configuration.

In the above embodiment, the number of input data is six, but it may be other than this, and the effect is particularly noticeable when the number of input data is large.

In addition, in the above embodiment, a plurality of input data is divided into two sets and inputted to the conversion circuit, but when there is a particularly large amount of input data, it is divided into two or more n sets. Each of them may be input to a conversion circuit. In this case, if the circuit configuration is such that the outputs of n conversion circuits are added and the addition result is input to a comparator and compared with a certain dark value, the same effect as in the above embodiment can be achieved. .

〔Effect of the invention〕

As described above, according to the majority decision circuit according to the present invention, for each divided set of a plurality of input data each indicating "O" or "1", whether all input data is "0" or "0" or "1" is determined.
A plurality of signal generating circuits that output signals indicating whether "0" and "1" are mixed or all "1", an adder that adds the outputs of the main circuit for the signals, and an addition of the adder Since a comparator that outputs output data of majority decision based on the result is provided, the circuit configuration can be simplified and high-speed operation can be performed.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram of a majority decision circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing an embodiment of a conversion circuit included in Fig. 1, and Fig. 3 is a circuit diagram showing an embodiment of a conversion circuit included in Fig. 1. FIG. 4 is a diagram showing truth tables representing the operations of the circuit of this embodiment and the conventional circuit, and FIG. 4 is a circuit diagram of a conventional majority decision circuit. In the figure, 1 to 6 are input binary data, 7°8 is a conversion circuit, 9 is an output β1.10 is an output β2.1) is a 2-bit adder, 12 is an output S', 13 is a comparator, and 14 is a Threshold C', 15 is majority decision output data α', 16 is AND
gate, 17 is an OR gate, 18 is an exclusive OR (X-
OR) gate. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a majority decision circuit that outputs a majority decision output for a plurality of input data each indicating "0" or "1", each predetermined piece of the plurality of input data is inputted,
a plurality of signal generating circuits that output signals indicating whether the predetermined pieces of data are all "0", a mixture of "0" and "1", or all "1"; and each of the above-mentioned signal generating circuits. 1. A majority decision circuit comprising: an adder that adds the outputs of the adder; and a comparator that compares the addition result of the adder with a constant value and outputs the comparison result. (2) The signal generation circuit includes an AND gate that generates a first signal that is the logical product of the input data, and an OR gate that generates a second signal that is the logical sum of the input data;
an exclusive OR gate that receives the first signal and the second signal as input and generates a third signal that is the exclusive OR of the first signal and the third signal; 2. The majority decision circuit according to claim 1, wherein the majority decision circuit outputs the following.