JPS63222469A - Laminated photosensor - Google Patents
Laminated photosensorInfo
- Publication number
- JPS63222469A JPS63222469A JP62055846A JP5584687A JPS63222469A JP S63222469 A JPS63222469 A JP S63222469A JP 62055846 A JP62055846 A JP 62055846A JP 5584687 A JP5584687 A JP 5584687A JP S63222469 A JPS63222469 A JP S63222469A
- Authority
- JP
- Japan
- Prior art keywords
- pin
- pin element
- photovoltaic device
- elements
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 25
- 229910045601 alloy Inorganic materials 0.000 claims 3
- 239000000956 alloy Substances 0.000 claims 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 3
- 239000002356 single layer Substances 0.000 claims 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000009751 slip forming Methods 0.000 claims 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims 1
- 229910001887 tin oxide Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 230000005611 electricity Effects 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010248 power generation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、太陽電池等の積層型光起電力素子に関し、
特にその高効率化に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a stacked photovoltaic device such as a solar cell,
In particular, it relates to increasing efficiency.
第４図は例えば特開昭５５−１２５６８０号公報に示さ
れた従来の積層型の光起電力素子である。図において１
は導！基板、２は最下層を形成する第１ｐｉｎ素子、３
は中間層を形成する第’ｌ、ｐｉｎ素子、４は表面層を
形成する第３ｐｉｎ素子、６は透明導電層、７は収集電
極である。FIG. 4 shows a conventional stacked photovoltaic device disclosed in, for example, Japanese Patent Laid-Open No. 55-125680. In the figure 1
Ha guide! A substrate, 2, a first pin element forming the bottom layer, 3
1 is a pin element forming an intermediate layer, 4 is a third pin element forming a surface layer, 6 is a transparent conductive layer, and 7 is a collecting electrode.
次に動作について説明する。Next, the operation will be explained.
例えば太陽光が表面層側から入射した場合、まず表面層
の第３ｐｉｎ素子４が光を吸収して発電し、次に第３ｐ
ｉｎ素子４で吸収されずに通過した光を中間層の第２ｐ
ｉｎ素子３が吸収して発電する。さらに、第２ｐｉｎ素
子３でも吸収されずに通過した光を最下層の第１ｐｉｎ
素子が吸収して発電し、全体で１対の光起電力素子とし
て機能している。For example, when sunlight enters from the surface layer side, first the third pin element 4 on the surface layer absorbs the light and generates electricity, then the third pin element 4
The light that has passed through the in element 4 without being absorbed is transferred to the second p of the intermediate layer.
The in element 3 absorbs and generates electricity. Furthermore, the light that has passed through the second pin element 3 without being absorbed is transferred to the first pin in the bottom layer.
The elements absorb electricity and generate electricity, functioning as a pair of photovoltaic elements as a whole.
従来の積層型の光起電力素子は以上のように構成されて
いるので、最下層の第１ｐｉｎ素子で吸収できる光量が
、上層の第２．第３ｐ ｉｎ素子により制限されている
。このため、第１ｐｉｎ素子の発電能力を十分に利用で
きず、第１ｐｉｎ素子が光起電力素子の光電変換効率を
大きく制約するという問題点があった。Since the conventional stacked photovoltaic element is constructed as described above, the amount of light that can be absorbed by the first pin element in the bottom layer is greater than the amount of light that can be absorbed by the second pin element in the upper layer. It is limited by the third pin element. Therefore, there was a problem in that the power generation capacity of the first pin element could not be fully utilized, and the first pin element greatly restricted the photoelectric conversion efficiency of the photovoltaic element.
この発明は、このよう、な問題点を解消するためになさ
れたもので、高い光電変換効率を有する積層型の光起電
力素子を得ることを目的とする。The present invention was made to solve these problems, and an object of the present invention is to obtain a stacked photovoltaic element having high photoelectric conversion efficiency.
この発明に係る積層型光起電力素子は、導電性基板と、
該基板上に光の入射方向に対して、３素子ともが重なる
部分を極力少なくするか、もしくは廃するように順次配
置形成された第１．第２および第３のｐｉｎ素子とを備
え、これら３つのｐｉｎ素子を電気的に直列に接続した
ものである。A stacked photovoltaic device according to the present invention includes a conductive substrate,
The first . A second pin element and a third pin element are provided, and these three pin elements are electrically connected in series.
この発明においては、導電性基板と、該基板上に光の入
射方向に対して、３素子ともが重なる部分を極力少なく
するか、もしくは廃するように順次配置形成された第１
．第２および第３のｐｉｎ素子とを備え、最下層となる
第１のｐｉｎ素子にも十分に光量を与えることができる
構成としたから、各ｐｉｎ素子の発電能力を十分に利用
できる。In the present invention, a conductive substrate and first elements are sequentially arranged and formed on the substrate in such a manner that the overlapping portion of all three elements is minimized or eliminated in the direction of incidence of light.
．． Since the second and third PIN elements are provided and a sufficient amount of light can be given to the first PIN element, which is the lowest layer, the power generation capacity of each PIN element can be fully utilized.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は、この発明の一実施例による積層型光起電力素
子を示す断面図であり、図において第４図と同一符号は
全く陶−のものであり、５は各ｐｉｎ素子の間に配置し
た透明絶縁層である。第１図は各ｐｉｎ素子が光の入射
方向に対して３素子とも交差する部分を完全に廃した場
合を示したものである。FIG. 1 is a sectional view showing a stacked photovoltaic device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. This is a transparent insulating layer. FIG. 1 shows a case where the portion where each pin element intersects the direction of incidence of light is completely eliminated.
次に動作について説明する。上記のように構成された積
層型光起電力素子においては、入射してきた光を第２の
ｐｉｎ素子３と第３のｐｉｎ素子４が同時に吸収して発
電し、それぞれの素子を通過した光を第１のｐｉｎ素子
２が吸収して発電している。上記においては、各ｐｉｎ
素子の間に配置した透明絶縁層により、第１．第２．第
３のｐｉｎ素子２．３．４は、電気的に並列に接続され
ることなく、直列に接続され、見かけ上、３層積層構造
の光起電力特性を示すことになる。Next, the operation will be explained. In the stacked photovoltaic device configured as described above, the second pin element 3 and the third pin element 4 simultaneously absorb incident light to generate electricity, and the light passing through each element is The first pin element 2 absorbs and generates power. In the above, each pin
The transparent insulating layer placed between the elements allows the first. Second. The third pin elements 2.3.4 are not electrically connected in parallel but are connected in series, and apparently exhibit photovoltaic characteristics of a three-layer laminated structure.
なお、上記実施例では、第１．第２．第３の各ｐｉｎ素
子２．３．４が、光の入射方向に対して、３１！に積層
される部分を完全に廃し、表面層として、第２．第３の
ｐｉｎ素子３．４を利用しているが、最下層として、第
１．第２のｐｉｎ素子２゜３を用いた構造、部分的に３
層を積層した構造においても同様にそれぞれのｐｉｎ素
子に十分な光量が与えられ、上記実施例と同様の効果を
奏する。Note that in the above embodiment, the first. Second. Each of the third pin elements 2.3.4 is 31! with respect to the light incident direction. The part that is laminated on the second layer is completely removed and the second layer is used as the surface layer. Although the third pin element 3.4 is used, the first pin element 3.4 is used as the bottom layer. Structure using second pin element 2゜3, partially 3
Even in a structure in which layers are laminated, a sufficient amount of light is similarly given to each pin element, and the same effect as in the above embodiment is achieved.
第２図は、中間層として、第２のｐｉｎ素子３を第１．
第３のｐｉｎ素子２，４の間で、部分的に形成した本発
明の他の実施例を示す断面図、また、第３図は、最下層
として、第１．第２のｐｉｎ素子２，３を交差すること
なく配置し、表面層として、第３のｐｉｎ素子４を形成
した本発明の他の実施例を示す断面図である。FIG. 2 shows a second pin element 3 as an intermediate layer and a first pin element 3 as an intermediate layer.
FIG. 3 is a sectional view showing another embodiment of the present invention partially formed between the third pin elements 2 and 4, and FIG. FIG. 7 is a cross-sectional view showing another embodiment of the present invention in which second pin elements 2 and 3 are arranged without crossing each other and a third pin element 4 is formed as a surface layer.
以上のように、この発明によれば、光の入射方向に対し
ては、構造を部分的に２層積層構造を用い、電気的には
、３層積層構造と同じ接続方法になるように構成したの
で、各ｐｉｎ素子とも十分な光量が吸収でき、積層型光
起電力素子として高い光電変換効率が得られるという効
果がある。As described above, according to the present invention, the structure is partially formed using a two-layer laminated structure in the direction of incidence of light, and the electrical connection method is the same as that of a three-layer laminated structure. Therefore, each pin element can absorb a sufficient amount of light, and a high photoelectric conversion efficiency can be obtained as a stacked photovoltaic element.
第１図はこの発明の一実施例を示す断面図、第２、第３
図はこの発明の他の実施例を示す断面図、第４図は従来
の積層型の光起電力素子を示す断面図である。
１は導電基板、２は第１のｐｉｎ素子、３は第２のｐｉ
ｎ素子、４は第３のｐｉｎ素子、５は透明絶縁層、６は
透明導電層、７は収集電極である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
The figure is a sectional view showing another embodiment of the present invention, and FIG. 4 is a sectional view showing a conventional stacked photovoltaic element. 1 is a conductive substrate, 2 is a first PIN element, 3 is a second PI
4 is a third pin element, 5 is a transparent insulating layer, 6 is a transparent conductive layer, and 7 is a collection electrode. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (12)
次形成された第１、第２および第３のｐｉｎ素子とを備
え、これら３つのｐｉｎ素子を電気的に直列に接続した
事を特徴とする積層型光起電力素子。(1) Comprising a conductive substrate and first, second and third pin elements formed in sequence on the substrate so as to have mutually overlapping parts, and electrically connecting these three pin elements. A stacked photovoltaic element characterized by being connected in series with.
に形成され、 上記第２のｐｉｎ素子は複数個に分割されて上記第１の
ｐｉｎ素子上に相互に所定の間隔をあけて形成され、 上記第３のｐｉｎ素子は複数個に分割されて上記第１の
ｐｉｎ素子上の上記第２のｐｉｎ素子の形成されていな
い部分に絶縁膜を介して形成されたものである事を特徴
とする特許請求の範囲第１項記載の積層型光起電力素子
。(2) The first PIN element is formed on the entire surface of the conductive substrate, and the second PIN element is divided into a plurality of pieces and placed on the first PIN element at a predetermined distance from each other. The third PIN element is divided into a plurality of pieces and formed on the first PIN element in a portion where the second PIN element is not formed, with an insulating film interposed therebetween. A stacked photovoltaic device according to claim 1.
に形成され、上記第２のｐｉｎ素子は複数個に分割され
て上記第１のｐｉｎ素子上に相互に所定の間隔をあけて
形成され、上記第３のｐｉｎ素子は上記第１のｐｉｎ素
子上の上記第２のｐｉｎ素子の形成されていない部分及
び上記第２のｐｉｎ素子上に連続して上記第１のｐｉｎ
素子上では絶縁膜を介して形成されたものである事を特
徴とする特許請求の範囲第１項記載の積層型光起電力素
子。(3) The first PIN element is formed on the entire surface of the conductive substrate, and the second PIN element is divided into a plurality of pieces and placed on the first PIN element at a predetermined distance from each other. The third pin element is formed on the first pin element where the second pin element is not formed and on the second pin element.
2. The stacked photovoltaic device according to claim 1, wherein the layered photovoltaic device is formed with an insulating film interposed on the device.
導電性基板上に相互に所定の間隔をあけて形成され、 上記第２のｐｉｎ素子は上記導電性基板上の上記第１の
ｐｉｎ素子の形成されていない部分に絶縁膜を介して形
成され、 上記第３のｐｉｎ素子は上記第１のｐｉｎ素子上及び第
２のｐｉｎ素子上に連続して上記第１のｐｉｎ素子上で
は絶縁膜を介して形成されたものであることを特徴とす
る特許請求の範囲第１項記載の積層型光起電力素子。(4) The first PIN element is divided into a plurality of pieces and formed on the conductive substrate at predetermined intervals, and the second PIN element is divided into a plurality of pieces and formed on the conductive substrate at a predetermined interval. The third PIN element is formed on a portion where no PIN element is formed via an insulating film, and the third PIN element is continuously formed on the first PIN element and the second PIN element. The stacked photovoltaic device according to claim 1, wherein the stacked photovoltaic device is formed with an insulating film interposed therebetween.
シリコン系合金で形成されていることを特徴とする特許
請求の範囲第１項ないし第４項のいずれかに記載の積層
型光起電力素子。(5) The multilayer photovoltaic device according to any one of claims 1 to 4, wherein the first, second, and third pin elements are made of an amorphous silicon alloy. element.
を含むアモルファスシリコン系合金を用いたことを特徴
とする特許請求の範囲第１項ないし第５項のいずれかに
記載の積層型光起電力素子。(6) The multilayer photovoltaic device according to any one of claims 1 to 5, characterized in that an amorphous silicon alloy containing germanium is used for a part of the first and second pin elements. power element.
むアモルファスシリコン系合金を用いたことを特徴とす
る特許請求の範囲第１項ないし第５項のいずれかに記載
の積層型光起電力素子。(7) The multilayer photovoltaic device according to any one of claims 1 to 5, wherein an amorphous silicon alloy containing carbon is used as a part of the second and third pin elements. power element.
にｐｉｎ素子が単層もしくは２層積層されたｐｉｎ素子
を用いたことを特徴とする特許請求の範囲第１項ないし
第５項のいずれかに記載の積層型光起電力素子。(8) Any one of claims 1 to 5, characterized in that one or both of the first and second pin elements uses a pin element in which a single layer or two layers of pin elements are stacked. A laminated photovoltaic device according to claim 1.
、ｐｉｎ素子が単層もしくは２層積層されたｐｉｎ素子
を用いたことを特徴とする特許請求の範囲第１項ないし
第５項および第７項のいずれかに記載の積層型光起電力
素子。(9) Claims 1 to 5 and 5 are characterized in that one or both of the second and third PIN elements is a PIN element in which a single layer or two layers of PIN elements are stacked. 8. The stacked photovoltaic device according to any one of Item 7.
透明導電層により電気的に直列に接続したことを特徴と
する特許請求の範囲第１項ないし第９項のいずれかに記
載の積層型光起電力素子。(10) The laminated type according to any one of claims 1 to 9, characterized in that the first pin element, the second pin element, and the third pin element are electrically connected in series by a transparent conductive layer. Photovoltaic element.
リコンを用いたことを特徴とする特許請求の範囲第２項
ないし第１０項記載の積層型光起電力素子。(11) The stacked photovoltaic device according to any one of claims 2 to 10, characterized in that silicon oxide or silicon nitride is used as the transparent insulating film.
ウムスズ（ＩＴＯ）を用いたことを特徴とする特許請求
の範囲第１０項または第１１項記載の積層型光起電力素
子。(12) The laminated photovoltaic device according to claim 10 or 11, wherein tin oxide or indium tin oxide (ITO) is used as the transparent conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62055846A JPS63222469A (en) | 1987-03-11 | 1987-03-11 | Laminated photosensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62055846A JPS63222469A (en) | 1987-03-11 | 1987-03-11 | Laminated photosensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63222469A true JPS63222469A (en) | 1988-09-16 |
Family
ID=13010389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62055846A Pending JPS63222469A (en) | 1987-03-11 | 1987-03-11 | Laminated photosensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63222469A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999048157A1 (en) * | 1998-03-19 | 1999-09-23 | Toyota Jidosha Kabushiki Kaisha | Solar battery |
| US6166320A (en) * | 1998-03-19 | 2000-12-26 | Toyota Jidosha Kabushiki Kaisha | Tandem solar cell |
| KR100636093B1 (en) * | 1999-07-12 | 2006-10-19 | 삼성전자주식회사 | Photo-detector device and method manufacturing thereof |
-
1987
- 1987-03-11 JP JP62055846A patent/JPS63222469A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999048157A1 (en) * | 1998-03-19 | 1999-09-23 | Toyota Jidosha Kabushiki Kaisha | Solar battery |
| AU727351B2 (en) * | 1998-03-19 | 2000-12-14 | Toyota Jidosha Kabushiki Kaisha | Solar cell |
| US6166320A (en) * | 1998-03-19 | 2000-12-26 | Toyota Jidosha Kabushiki Kaisha | Tandem solar cell |
| KR100636093B1 (en) * | 1999-07-12 | 2006-10-19 | 삼성전자주식회사 | Photo-detector device and method manufacturing thereof |
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