JPS63221274A - Target azimuth detecting circuit - Google Patents

Target azimuth detecting circuit

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Publication number
JPS63221274A
JPS63221274A JP5440287A JP5440287A JPS63221274A JP S63221274 A JPS63221274 A JP S63221274A JP 5440287 A JP5440287 A JP 5440287A JP 5440287 A JP5440287 A JP 5440287A JP S63221274 A JPS63221274 A JP S63221274A
Authority
JP
Japan
Prior art keywords
video
difference
signal
quadrant
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5440287A
Other languages
Japanese (ja)
Inventor
Hiroshi Ishii
弘 石井
Masanobu Tsudo
津藤 正信
Kazumi Yamaguchi
山口 和巳
Yutaka Kinoshita
木之下 裕
Masaki Yasufuku
安福 正樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5440287A priority Critical patent/JPS63221274A/en
Publication of JPS63221274A publication Critical patent/JPS63221274A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To decide the azimuth of a target with high accuracy even from a small input by finding the quadrant of the phase of each video by using only sign bits of a sum video signal and a difference video signal after digital conversion, and making a decision from a quadrant difference. CONSTITUTION:A quadrant converter 3a inputs only a sign between the sign and amplitude after the bipolar A/D conversion of a sum pattern video from a monopulse antenna receiver to find a quadrant where the phase of the video is present. Similarly, a quadrant converter 3b finds a quadrant from the size of a difference pattern video. Then a quadrant difference detector 4 finds the quadrant difference and a right-left decision device 5 decides three conditions, i.e. right, left, and unknown conditions from the output of the detector 4. Then latch circuits 11 in an integrator 6 and an integral decision device 7 are stored with a right, a left, or an unknown signal and an adder 10b performs integration to decide right when the integral value is larger than a specific value or left in other cases.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、モノパルス・アンテナを用いたレーダ装置
において、目標の反射波が左右のどちらの方位からのも
のかを判別するための目標方位検出回路に関するもので
ある。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to target direction detection for determining whether a reflected wave from a target is from the left or right direction in a radar device using a monopulse antenna. It is related to circuits.

〔従来の技術〕[Conventional technology]

従来、この種の回路としては、第4図に示すものがあっ
た0図において、1a及び1bはモノパルス・アンテナ
受信機からの和パターンビデオ(以後ΣIビデオ、ΣQ
ビデオと呼び、■ビデオとQビデオは90°の位相差を
もつ。)および差パターンビデオ(以後Δ■ビデオ、Δ
Qビデオと呼ぶ。)が各距離ゲートごとにアナログビデ
オからディジタル信号に変換された符号付きビデオ信号
を用いて、Σビデオの位相角度およびΔビデオの位相角
度をそれぞれ求めるための位相角度検出器、2は位相角
度検出器1a、lbからのΣビデオの位相角度φΣ(O
〜360  °)とΔビデオの位相角度φΔ(O〜36
0 °)から位相差を求め、左右の方位の判定を行なう
位相差判定器である。
Conventionally, this type of circuit has been shown in Figure 4. In Figure 0, 1a and 1b are sum pattern videos (hereinafter ΣI video, ΣQ) from a monopulse antenna receiver.
It is called video, and ■video and Q video have a phase difference of 90°. ) and difference pattern video (hereinafter Δ■ video, Δ
It's called Q-video. ) is a phase angle detector for determining the phase angle of Σ video and the phase angle of Δ video, respectively, using a signed video signal converted from an analog video to a digital signal for each distance gate, and 2 is a phase angle detector. The phase angle φΣ(O
~360°) and Δvideo phase angle φΔ(O~36
This is a phase difference determiner that determines the phase difference from 0°) and determines the left and right orientation.

ここで、簡単に一般的なモノパルスアンテナによる方位
判定の概念を第6図(a)、 (b)、 (C)により
説明する。(通信学会績レーダ技術〔その2〕初版11
.4モノパルス方式より) 2個の一部重なり合ったモノパルスアンテナパターン(
第6図(a))を用い、2個のアンテナパターンを同相
にて合成する和パターンと逆相によって合成する差パタ
ーンとを用いる。
Here, the concept of orientation determination using a general monopulse antenna will be briefly explained with reference to FIGS. 6(a), (b), and (C). (Communications Association Research Radar Technology [Part 2] First Edition 11
.. 4 monopulse method) Two partially overlapping monopulse antenna patterns (
Using FIG. 6(a), a sum pattern in which two antenna patterns are combined in the same phase and a difference pattern in which they are combined in opposite phases are used.

Σビデオの位相とΔビデオあ位相との位相差φΔ−φΣ
は方位O@を境として一90@から+90”(又は+9
0″から一90@、ここでは右側を+90°、左側を−
90”として説明する。)に反転することが知られてお
り、第6図(b)の位相差φΔ−φΣが+90°の時に
目標が右方位、−90°の時に目標が左方位と判定する
(+90’の時に左方位とし、−90”の時に右方位と
仮定してもよいが、ここでは+90°の時に右方位、−
90”の時を左方位と仮定する)。
Phase difference between Σ video phase and Δ video a phase φΔ−φΣ
is from -90@ to +90” (or +9
0″ to 190@, here the right side is +90° and the left side is -
When the phase difference φΔ−φΣ in FIG. 6(b) is +90°, the target is determined to be on the right, and when it is −90°, it is determined that the target is on the left. (Although it may be assumed that +90' is the left direction and -90" is the right direction, here, the right direction is +90°, and -90" is the right direction.
90” is assumed to be the left direction).

そこで、次に従来の回路動作について説明する。Therefore, the conventional circuit operation will be explained next.

モノパルス・アンテナ受信機においては、Σパターンと
Δパターンのアンテナ合成を行ない、位相検波器により
、90″位相差をもつI、Qビデオにする。すなわち振
幅をAvp−r、目標の角周波数をωとすると、ビデオ
信号は AVF−P (CO3(ωt+θo ) + jsin
(ωを十〇。))の複素数で表わされる。このビデオ信
号のうち実軸上のものA cos (ωを十〇)を■ビ
デオ、虚軸上のものAs1n(ωを十〇)をQビデオと
呼ぶ。
In a monopulse antenna receiver, the Σ pattern and the Δ pattern are combined into I and Q videos with a phase difference of 90'' using a phase detector. That is, the amplitude is Avp-r, and the target angular frequency is ω. Then, the video signal is AVF-P (CO3(ωt+θo) + jsin
(ω is 10)) is expressed as a complex number. Among these video signals, the one on the real axis A cos (ω is 10) is called ■video, and the one on the imaginary axis As1n (ω is 10) is called Q video.

このΣI、ΣQ、Δ■、ΔQの4つのアナログビデオを
A/D変換し、符号と振幅値を用いて位相角度を検出す
る。位相角度検出器1aでは、ま符号より、第5図の右
半面か、左半面かを判定する。
The four analog videos ΣI, ΣQ, Δ■, and ΔQ are A/D converted, and the phase angle is detected using the sign and amplitude value. The phase angle detector 1a determines whether it is the right half plane or the left half plane in FIG. 5 from the mark.

の条件をROM (Read 0nly Memory
)に入れ、ROMからΣの位相角(φΣ)を出力する。
The conditions of ROM (Read Only Memory
) and output the phase angle (φΣ) of Σ from the ROM.

同様に、Δの位相角(φΔ)も位相角度検出器1bにて
出力する。
Similarly, the phase angle of Δ (φΔ) is also output from the phase angle detector 1b.

位相差判定器2では、Δの位相(φΔ)からΣの゛位相
(φΣ)を引き一180°〜+180 ”の間で表わし
、0°〜+180 ”の間の時は1 (右)として、−
180”〜0°の間の時にはO(左)として左右方位の
判定結果を出力する。
In the phase difference determiner 2, the phase of Σ (φΣ) is subtracted from the phase of Δ (φΔ) and expressed as between -180° and +180'', and when it is between 0° and +180'', it is set as 1 (right). −
When the angle is between 180'' and 0°, the left/right direction determination result is output as O (left).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の目標方位検出回路は以上のように構成されている
ので、レーダ受信ビデオの入力振幅が大きなレベルの時
は位相角を求めることができるが、入力振幅が雑音に近
い小さなレベルの時にはく演算することができない。し
たがってΔとΣのビデオの位相差(Δの位相−Σの位相
)が正確に計算できないので、左右の方位を誤って判断
するおそれがあるという問題点があった。
Since the conventional target direction detection circuit is configured as described above, it is possible to obtain the phase angle when the input amplitude of the radar received video is at a large level, but it is difficult to calculate when the input amplitude is at a small level close to noise. Can not do it. Therefore, since the phase difference between the videos Δ and Σ (phase of Δ−phase of Σ) cannot be calculated accurately, there is a problem that the left and right directions may be incorrectly determined.

この発明は、上記のような問題点を解決するためになさ
れたもので、高精度に目標の方位を判定することができ
る目標方位検出回路を得ることを目的とする。
The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to obtain a target direction detection circuit that can determine the direction of a target with high precision.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る目標方位検出回路は、バイポーラA/D
 (アナログ/ディジタル)変換後の和ビデオ信号と差
ビデオ信号の符号ビットのみを用いてそれぞれのビデオ
の位相が位置する象限を求め、該和ビデオ信号と差ビデ
オ信号の位相の象限差から目標の方位を判定するように
したものである。
The target direction detection circuit according to the present invention includes a bipolar A/D
(analog/digital) Using only the sign bits of the sum video signal and difference video signal after conversion, find the quadrant in which the phase of each video is located, and use the quadrant difference between the phases of the sum video signal and difference video signal to find the target. It is designed to determine the direction.

〔作用〕[Effect]

この発明においては、和ビデオ信号と差ビデオ信号の位
相符号のみを用いて目標の方位を判定するようにしたの
で、受信ビデオのレベルが雑音に近いレベルであっても
高精度に目標の左右方位を判定することができる。
In this invention, the target direction is determined using only the phase codes of the sum video signal and the difference video signal, so even if the level of the received video is close to noise, the left and right direction of the target can be determined with high accuracy. can be determined.

〔実施例〕〔Example〕

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)及び申)はこの発明の第1実施例による目
標方位検出回路を示すブロック図及び回路図であり、両
図において、3a、3bは和ビデオ(Σビデオ)信号及
び差ビデオ(Δビデオ)信号のそれぞれ90°位相差を
もつI、QビデオのA/D変換後の符号を用いて、和、
差ビデオの位相の象限をそれぞれ求める象限変換器、4
はΣビデオの象限とΔビデオの象限との差を演算し、そ
の結果を2ビットで出力する象限差検出器、5は2ビッ
トで表わされた象限差から、右、左、不明の3条件を判
別する左右判別器、6は右、左、不明の判定を積分する
ための積分器、7は積分した結果から左、右の最終判別
結果を得るための積分判定器、8aはΣI、Qの符号が
、8bはΔI、Qの符号が、それぞれ入力される排他的
OR回路、10aはBz、B+端子の入力信号を上位、
下位ビットとする2ビット信号と、A t 、 A I
端子の入力信号を上位、下位ビットとする2ビット信号
と、“1”とを加算し、加算結果の下位2ビットを82
、S、の端子から出力する加算器であり、B+端子には
ΣQの符号がインバータ回路9aを介して入力され、B
、端子にはOR回路8aの出力がインバータ回路9bを
介して入力され、A2端子にはΔQの符号が入力され、
A、端子にはOR回路8bの出力が入力され、CO端子
にはインバータ回路9Cを介して常に“1”が入力され
ている。12は上記加算器10aのSZ端子の出力のイ
ンバータ回路9dによる反転信号とS、端子の出力とを
入力とするAND回路、9eは上記加算器10aの81
端子の出力を反転するインバータ回路、11は−AND
回路12の出力を上位ビットとしインバータ回路9eの
出力を下位ビットとする2ビット信号を記憶するランチ
回路、10bは記憶された2ビット信号を所定の回数だ
け積分する加算器である。
FIGS. 1(a) and 1) are block diagrams and circuit diagrams showing a target direction detection circuit according to a first embodiment of the present invention, and in both figures, 3a and 3b are a sum video (Σ video) signal and a difference video signal. (ΔVideo) Using the codes after A/D conversion of I and Q videos, each having a 90° phase difference, the sum,
quadrant converter for determining the phase quadrants of the difference video; 4;
5 is a quadrant difference detector that calculates the difference between the quadrant of Σ video and the quadrant of Δ video and outputs the result in 2 bits. 6 is an integrator for integrating the judgment of right, left, and unknown; 7 is an integral judge for obtaining the final discrimination result of left and right from the integrated result; 8a is ΣI; 8b is an exclusive OR circuit into which the sign of Q is input, ΔI is input, and the sign of Q is input, 10a is Bz, the input signal of the B+ terminal is input to the upper,
2-bit signal as lower bit, A t , A I
Add "1" to a 2-bit signal whose upper and lower bits are the input signal of the terminal, and convert the lower 2 bits of the addition result to 82
, S, and the sign of ΣQ is input to the B+ terminal via the inverter circuit 9a.
, the output of the OR circuit 8a is input to the terminal via the inverter circuit 9b, the sign of ΔQ is input to the A2 terminal,
The output of the OR circuit 8b is input to the A terminal, and "1" is always input to the CO terminal via the inverter circuit 9C. 12 is an AND circuit which receives as input the inverted signal from the inverter circuit 9d of the output of the SZ terminal of the adder 10a and the output of the S terminal, and 9e is an AND circuit 81 of the adder 10a.
Inverter circuit that inverts the output of the terminal, 11 is -AND
A launch circuit 10b stores a 2-bit signal in which the output of the circuit 12 is the upper bit and the output of the inverter circuit 9e is the lower bit. Reference numeral 10b is an adder that integrates the stored 2-bit signal a predetermined number of times.

次に動作について説明する。Next, the operation will be explained.

象限変換器3aでは、ΣI、ΣQビデオのバイポーラA
/D変換後の符号と振幅のうち、符号のみが入力され、
象限に変換される。すなわち、第1図(′b)に示すよ
うに、ΣQの符号と排他的OR回路8aの出力とからな
る2ビット信号が出力される。ここでは(Σ■、ΣQ)
 −(0,0)なら第1象限、(1,O)なら第2象限
、(1,1)なら第3象限、(0,1)なら第4象限と
している。
In the quadrant converter 3a, bipolar A of ΣI, ΣQ video
Of the sign and amplitude after /D conversion, only the sign is input,
converted into quadrants. That is, as shown in FIG. 1('b), a 2-bit signal consisting of the sign of ΣQ and the output of the exclusive OR circuit 8a is output. Here (Σ■, ΣQ)
-(0,0) is the first quadrant, (1,O) is the second quadrant, (1,1) is the third quadrant, and (0,1) is the fourth quadrant.

同様に、象限変換器3bによりΔ■、ΔQビデオの符号
から象限が求められ、同様の信号が出力される。
Similarly, quadrants are determined from the codes of the Δ■ and ΔQ videos by the quadrant converter 3b, and similar signals are output.

次に、象限差検出器4では、 象限差−Δの位相象限−Σの位相象限 が求められる。すなわち、加算器10aには象限変換器
3aの出力の反転信号と、象限変換器3bの出力と、“
1″とがそれぞれ入力されて、所定の加算が行われ、S
、、S、端子から加算結果が2ビット信号で出力される
Next, the quadrant difference detector 4 determines the phase quadrant of the quadrant difference -Δ and the phase quadrant of -Σ. That is, the adder 10a receives the inverted signal of the output of the quadrant converter 3a, the output of the quadrant converter 3b, and "
1'' are input, a predetermined addition is performed, and S
,,S, terminals output the addition result as a 2-bit signal.

そして、左右判別器5では、該2ビ・ノド信号に基づい
て象限差が2ビット信号で表現されて出力される。ここ
では、Δの方が位相象限が1象限進んでいる時は2(1
0)の信号、Σの方が1象限進んでいる時は0(00)
の信号が出力され、また位相象限差がO又は2 (同−
象限又は180@ずれ)の時には、原因はモノパルス・
アンテナのΣ、Δビデオの位相ずれ又はΣ、Δビデオの
A/D変換時の変換誤まりによるものと考え、不明とし
て1(01)の信号が出力される。
Then, in the left/right discriminator 5, the quadrant difference is expressed as a 2-bit signal based on the 2-bit signal and output. Here, when the phase quadrant of Δ is one quadrant ahead, 2(1
0) signal, 0 (00) when Σ is one quadrant ahead
signal is output, and the phase quadrant difference is O or 2 (same -
quadrant or 180@ deviation), the cause is monopulse.
It is assumed that this is due to a phase shift of the Σ and Δ videos of the antenna or a conversion error during A/D conversion of the Σ and Δ videos, and a signal of 1 (01) is output as unknown.

次に、積分器6および積分判定器7では、ラッチ回路1
1により2(右)、O(左)、1 (不明)の信号が記
憶され、加算器10bにより積分が行なわれて所定の値
より大の時には右として、そうでない時は左として判別
される。たとえば8回積分するとすると、積分結果が8
以上なら右となる。
Next, in the integrator 6 and the integral determiner 7, the latch circuit 1
1 stores the signals 2 (right), O (left), and 1 (unknown), and the adder 10b performs integration, and when the value is greater than a predetermined value, it is determined as right, and when it is not, it is determined as left. . For example, if you integrate 8 times, the integration result will be 8
If it is above, it is right.

このように、本実施例では、和ビデオ信号と差ビデオ信
号の位相符号のみを用いて目標方位を判定するようにし
たので、受信ビデオのレベルが雑音に近いレベルであっ
ても高精度に左右方位の判定をすることができ、しかも
判定結果を複数回積分して得るようにしたので、和ビデ
オと差ビデオの位相ずれやA/D変換器の変換誤りの影
響を少なくでき、より信舷性の高い判定結果を得ること
ができる。
In this way, in this embodiment, the target direction is determined using only the phase codes of the sum video signal and the difference video signal, so even if the level of the received video is close to noise, it is possible to Since the direction can be determined and the determination result is obtained by integrating it multiple times, the effects of phase shifts between the sum video and difference video and conversion errors of the A/D converter can be reduced, increasing reliability. It is possible to obtain highly accurate judgment results.

第2図はこの発明の第2実施例による目標方位検出回路
を示すブロック図であり、本実施例は第1図(a)、 
(blに示す実施例から積分器6及び積分判定器7を除
いた構成のものである。このような本実施例では、モノ
パルス・アンテナのΣ、Δビデオの位相ずれやΣ、Δビ
デオのA/D変換時の変換誤りが許容値内であれば、正
確な方位判定を行うことができる。
FIG. 2 is a block diagram showing a target direction detection circuit according to a second embodiment of the present invention.
(This is a configuration in which the integrator 6 and the integral determiner 7 are removed from the embodiment shown in bl.) In this embodiment, the monopulse antenna's Σ and Δ video phase shifts and Σ and Δ video's A If the conversion error during /D conversion is within the allowable value, accurate direction determination can be performed.

第3図はこの発明の第3実施例による目標方位検出回路
を示す回路図である。本実施例は第1図(a)、 (b
)に示す実施例の象限変換器3a、3b及び象限差検出
器4をΣT、ΣQ、Δ■、ΔQの4つの符号を入力とし
て2(右)、0(左)、1 (不明)の左右判別信号を
出すROM (Read 0nly Mewary)回
路13に置き換えたものであり、これによっても、第1
図(a)、 (b)に示す実施例と同様に、正確な判定
を行うことができる。
FIG. 3 is a circuit diagram showing a target direction detection circuit according to a third embodiment of the present invention. This example is shown in Figs. 1(a) and (b).
) The quadrant converters 3a, 3b and the quadrant difference detector 4 of the embodiment shown in FIG. This is replaced with a ROM (Read Only Memory) circuit 13 that outputs a discrimination signal.
As in the embodiments shown in FIGS. (a) and (b), accurate determination can be made.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明の目標方位検出回路によれば、
バイポーラA/D変換後の和ビデオ信号と差ビデオ信号
の符号ビットのみを用いてビデオの位相が位置する象限
を求め、和ビデオ信号と差ビデオ信号の位相の象限差か
ら目標の方位を判定するようにしたので、受信ビデオの
レベルが雑音に近いレベルであっても、正確に左右方位
の判定をすることができる効果がある。
As described above, according to the target direction detection circuit of the present invention,
The quadrant in which the video phase is located is determined using only the sign bits of the sum video signal and the difference video signal after bipolar A/D conversion, and the target direction is determined from the quadrant difference between the phases of the sum video signal and the difference video signal. This has the advantage that even if the level of the received video is close to noise, the left and right direction can be determined accurately.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)及び(b)はこの発明の第1実施例による
目標方位検出回路を示すブロック図及び回路図、第2図
はこの発明の第2実施例による目標方位検出回路を示す
ブロック図、第3図はこの発明の第3実施例による目標
方位検出回路を示す回路図、第4図は従来の目標方位検
出回路を示すブロック図、第5図は従来の目標方位検出
回路の位相差演算を説明するための図、第6図(a)、
 (b)、 (C)はモノパルスアンテナにおける左右
方位検出の概念を説明するための図である。 図において、3a、3bは象限変換器、4は象限差検出
器、5は左右判別器、6は積分器、7は積分判定器、8
a、8bは排他的OR回路、9a。 9b、9c、9d、9eはインバータ回路、10a、l
Qbは加算器、11はラッチ回路、12はAND回路、
13はROM (Read 0nly Memory)
回路である。 なお図中同一符号は同−又は相当部分を示す。
1(a) and (b) are block diagrams and circuit diagrams showing a target direction detection circuit according to a first embodiment of the present invention, and FIG. 2 is a block diagram showing a target direction detection circuit according to a second embodiment of the present invention. 3 is a circuit diagram showing a target direction detection circuit according to a third embodiment of the present invention, FIG. 4 is a block diagram showing a conventional target direction detection circuit, and FIG. 5 is a circuit diagram showing a conventional target direction detection circuit. Diagram for explaining phase difference calculation, FIG. 6(a),
(b) and (C) are diagrams for explaining the concept of left/right direction detection in a monopulse antenna. In the figure, 3a and 3b are quadrant converters, 4 is a quadrant difference detector, 5 is a left/right discriminator, 6 is an integrator, 7 is an integral determiner, and 8
a, 8b are exclusive OR circuits, and 9a. 9b, 9c, 9d, 9e are inverter circuits, 10a, l
Qb is an adder, 11 is a latch circuit, 12 is an AND circuit,
13 is ROM (Read Only Memory)
It is a circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (4)

【特許請求の範囲】[Claims] (1)モノパルスアンテナの和パターンと差パターンの
誤差感度曲線を用いて目標の方位を検出する目標方位検
出回路において、 和ビデオ信号及び差ビデオ信号のそれぞれ90°位相差
をもつI、QビデオをA/D変換した後の符号を用いて
、和ビデオ及び差ビデオの位相の象限をそれぞれ求める
象限変換器と、 和ビデオと差ビデオの象限差を検出する象限差検出器と
、 上記象限差に基づいて左右の判別を行なう左右判別手段
とを備えたことを特徴とする目標方位検出回路。
(1) In a target orientation detection circuit that detects the target orientation using the error sensitivity curves of the sum pattern and difference pattern of the monopulse antenna, I and Q videos with a 90° phase difference between the sum video signal and the difference video signal are used. A quadrant converter that calculates phase quadrants of the sum video and the difference video using codes after A/D conversion; a quadrant difference detector that detects the quadrant difference between the sum video and the difference video; and a quadrant difference detector that detects the quadrant difference between the sum video and the difference video. 1. A target orientation detection circuit comprising: left and right discrimination means for determining left and right based on the left and right discrimination means.
(2)上記左右判別手段は、判別結果を示す信号を複数
回積分する積分器と、 該積分結果に基づいて左右の判別を行なう積分判定器と
を備えたものであることを特徴とする特許請求の範囲第
1項記載の目標方位検出回路。
(2) A patent characterized in that the left/right discrimination means is equipped with an integrator that integrates a signal indicating the discrimination result multiple times, and an integral determiner that discriminates between left and right based on the integration result. A target direction detection circuit according to claim 1.
(3)上記象限変換器は、和ビデオ信号及び差ビデオ信
号の各I、QビデオのA/D変換後の符号がそれぞれ入
力される第1、第2の排他的OR回路を備えてなり、 上記象限差検出器は、 上記和ビデオ信号のQビデオの符号の反転信号を上位ビ
ットとし上記第1の排他的OR回路の出力の反転信号を
下位ビットとする2ビット信号と、上記差ビデオ信号の
Qビデオの符号を上位ビットとし上記第2の排他的OR
回路の出力を下位ビットとする2ビット信号と、キャリ
ー入力信号“1”とを加算し、加算結果の下位2ビット
の信号を出力する加算器を備えてなり、 上記左右判別手段は、 上記加算器出力の上位ビット信号の反転信号と下位ビッ
ト信号とを入力とするAND回路と、該下位ビット信号
が入力されるインバータ回路とを備えてなるものである
ことを特徴とする特許請求の範囲第1項記載の目標方位
検出回路。
(3) The quadrant converter includes first and second exclusive OR circuits to which the A/D converted codes of each I and Q video of the sum video signal and the difference video signal are input, respectively; The quadrant difference detector detects a 2-bit signal in which the upper bit is an inverted signal of the sign of the Q video of the sum video signal and the lower bit is an inverted signal of the output of the first exclusive OR circuit, and the difference video signal. The above second exclusive OR with the code of the Q video of
The left/right discrimination means includes an adder that adds a 2-bit signal whose lower bit is the output of the circuit and a carry input signal "1" and outputs a signal of the lower 2 bits of the addition result, and the left/right discrimination means is configured to perform the addition. Claim 1, characterized in that the invention comprises an AND circuit receiving an inverted signal of the upper bit signal of the output of the device and a lower bit signal, and an inverter circuit receiving the lower bit signal. The target direction detection circuit described in item 1.
(4)上記左右判別手段は、 上記AND回路の出力を上位ビットとし上記インバータ
回路の出力を下位ビットとする2ビット信号を記憶する
ラッチ回路と、 該ラッチ回路に記憶された信号を所定回数積分するため
の加算器とを備えたものであることを特徴とする特許請
求の範囲第3項記載の目標方位検出回路。
(4) The left/right discrimination means includes a latch circuit that stores a 2-bit signal in which the output of the AND circuit is the upper bit and the output of the inverter circuit is the lower bit, and the signal stored in the latch circuit is integrated a predetermined number of times. 4. The target direction detection circuit according to claim 3, further comprising an adder for calculating the target direction.
JP5440287A 1987-03-10 1987-03-10 Target azimuth detecting circuit Pending JPS63221274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5440287A JPS63221274A (en) 1987-03-10 1987-03-10 Target azimuth detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5440287A JPS63221274A (en) 1987-03-10 1987-03-10 Target azimuth detecting circuit

Publications (1)

Publication Number Publication Date
JPS63221274A true JPS63221274A (en) 1988-09-14

Family

ID=12969696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5440287A Pending JPS63221274A (en) 1987-03-10 1987-03-10 Target azimuth detecting circuit

Country Status (1)

Country Link
JP (1) JPS63221274A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013521737A (en) * 2010-03-10 2013-06-10 タレス・カナダ・インク RF tag reader for accurate position determination
JP2015121404A (en) * 2013-12-20 2015-07-02 日本電気株式会社 Angle measuring device, angle measuring method and program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013521737A (en) * 2010-03-10 2013-06-10 タレス・カナダ・インク RF tag reader for accurate position determination
JP2015121404A (en) * 2013-12-20 2015-07-02 日本電気株式会社 Angle measuring device, angle measuring method and program

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