JPS6321991B2 - - Google Patents
Info
- Publication number
- JPS6321991B2 JPS6321991B2 JP56089169A JP8916981A JPS6321991B2 JP S6321991 B2 JPS6321991 B2 JP S6321991B2 JP 56089169 A JP56089169 A JP 56089169A JP 8916981 A JP8916981 A JP 8916981A JP S6321991 B2 JPS6321991 B2 JP S6321991B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- magnetic
- layer
- conductor
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002223 garnet Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 25
- 239000004020 conductor Substances 0.000 description 23
- 230000006866 deterioration Effects 0.000 description 6
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- ZPDRQAVGXHVGTB-UHFFFAOYSA-N gallium;gadolinium(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Gd+3] ZPDRQAVGXHVGTB-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910000889 permalloy Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- -1 polysiloxane Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
- G11C19/0875—Organisation of a plurality of magnetic shift registers
- G11C19/0883—Means for switching magnetic domains from one path into another path, i.e. transfer switches, swap gates or decoders
Description
【発明の詳細な説明】
本発明は層構成により駆動パターン上に生ずる
段差の発生を局部的に抑制する磁気バブルメモリ
チツプに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic bubble memory chip that locally suppresses the occurrence of steps on a drive pattern through a layer structure.
磁気バブルメモリチツプは非磁性ガーネツトで
あるガドリニウム・ガリウム・ガーネツト
（Gd3Ga5O12）の上に必要とする磁性を備えたガ
ーネツト結晶薄膜をエピタキシヤル成長せしめ、
この上に厚さ約1000ÅのSiO2（酸化硅素）絶縁層
を設けたものを基板とし、この上に磁気バブルの
発生器、ゲート回路などの導体パターンよりなる
第１層パターンが金属蒸着技術と写真蝕刻技術
（ホトリソグラフイ）を用いて形成されており、
その上に絶縁層を介して磁気バブルの転送回路、
検出回路などの第２層パターンが軟磁性体を用い
て形成され更にこの上に保護層を設けることによ
り層形成されるが第１層、第２層パターン間の絶
縁物質として樹脂を用いるものがある。 Magnetic bubble memory chips are made by epitaxially growing a garnet crystal thin film with the required magnetism on gadolinium gallium garnet (Gd 3 Ga 5 O 12 ), which is a non-magnetic garnet.
A SiO 2 (silicon oxide) insulating layer with a thickness of approximately 1000 Å is formed on this substrate, and a first layer pattern consisting of conductor patterns such as a magnetic bubble generator and a gate circuit is formed using metal vapor deposition technology. It is formed using photolithography,
Magnetic bubble transfer circuit, through an insulating layer on top of it
A second layer pattern such as a detection circuit is formed using a soft magnetic material, and a protective layer is further provided on top of the second layer pattern, but in some cases a resin is used as an insulating material between the first and second layer patterns. be.
かゝる構成の磁気バブルメモリ素子は上記のよ
うに基板上に導体パターンが第１層パターンとし
てあり、絶縁層を隔てゝパーマロイからなる転送
パターンが第２層パターンとして設けられている
がその表面は平坦ではなく、その下に導体パター
ンが存在する部分では局部的に絶縁層が隆起する
ため第２層パターンを形成する転送パターンが、
第１層を形成する導体パターンと立体交叉する部
分では転送パターンの一部がその厚さ方向に段差
を伴つて形成される。その場合平坦な面上に形成
されている転送パターンに較べその転送特性が劣
化する場合がある。 A magnetic bubble memory element having such a structure has a conductor pattern as a first layer pattern on a substrate as described above, and a transfer pattern made of permalloy is provided as a second layer pattern with an insulating layer in between. is not flat, and the insulating layer is locally raised in areas where there is a conductor pattern underneath, so the transfer pattern that forms the second layer pattern is
A portion of the transfer pattern is formed with a step in the thickness direction at a portion that three-dimensionally intersects with the conductor pattern forming the first layer. In that case, the transfer characteristics may deteriorate compared to a transfer pattern formed on a flat surface.
例えばゲート回路は転送パターン上を駆動磁界
により転送されてきた磁気バブルがこの下に設け
られている導体パターンを流れる信号電流による
誘起磁界の影響を受けて機能動作を行う回路であ
り、転送パターンに段差が存在する場合は磁気バ
ブルメモリの動作マージンの減少と云う形で影響
が現われ、また通常の転送動作においても段差が
原因して誤動作を起すことがある。 For example, a gate circuit is a circuit in which a magnetic bubble transferred by a driving magnetic field on a transfer pattern operates under the influence of a magnetic field induced by a signal current flowing through a conductor pattern provided below. If a step exists, the effect appears in the form of a reduction in the operating margin of the magnetic bubble memory, and even in normal transfer operations, the step may cause malfunctions.
本発明は転送パターンの段差の存在による磁気
バブルメモリの特性劣化を無くすることを目的と
し、そのために転送パターンと立体交叉している
導体パターンの近傍にこれと電気的に絶縁された
ダミーの細分化導体パターンを設けることによ
り、交叉部における段差の発生を極力抑えると共
に不要バブルの発生等も抑えることを本旨とする
ものであり、以下図面により実施例について本発
明を説明する。 The purpose of the present invention is to eliminate the deterioration of the characteristics of magnetic bubble memory due to the presence of steps in the transfer pattern, and for this purpose, a dummy subdivision is provided near the conductor pattern that intersects the transfer pattern in three dimensions, electrically insulated from the conductor pattern. The main purpose of the present invention is to suppress the occurrence of steps at the intersection as much as possible by providing a conductor pattern, and also to suppress the occurrence of unnecessary bubbles.The present invention will be described below with reference to the drawings.
第１図は導体パターンと転送パターンとが立体
交叉している部分について従来構造断面図で、磁
性ガーネツト結晶膜１の上にSiO2（酸化硅素）よ
になる厚さ約1000Åの絶縁層２がありこの上に磁
気バブルメモリの回路パターンが形成されてい
る。 FIG. 1 is a cross-sectional view of the conventional structure of the part where the conductor pattern and the transfer pattern intersect in three dimensions. On the magnetic garnet crystal film 1, there is an insulating layer 2 of about 1000 Å thick made of SiO 2 (silicon oxide). A magnetic bubble memory circuit pattern is formed on the dovetail.
すなわちAu（金）或はAl（アルミ）・Cu（銅）合
金よりなる導体パターン（図の場合はゲート回
路）３が約4000Åの厚さで形成されており、この
第１層回路の上にポリイミド系樹脂或はポリシロ
キサン系樹脂などをスピンコート法により4000Å
程度の厚さに被覆して絶縁層４が形成され、この
上にパーマロイからなる転送パターン５が4000Å
程度の厚さで構成され、図では省略してあるがこ
の上に樹脂及びSiO2よりなる保護膜を被覆する
ことで層形成が終つている。 That is, a conductor pattern (gate circuit in the figure) 3 made of Au (gold) or Al (aluminum)/Cu (copper) alloy is formed with a thickness of approximately 4000 Å, and on top of this first layer circuit. Polyimide resin or polysiloxane resin is coated with a thickness of 4000Å by spin coating.
An insulating layer 4 is formed to a thickness of about
Although not shown in the figure, layer formation is completed by covering this with a protective film made of resin and SiO 2 .
さて磁気バブルメモリは磁気バブルが面方向磁
界により磁化している転送パターンの磁極に吸引
され、面方向磁界の回転に追随して転送パターに
副つて移行する現象と導体パターンを流れる信号
電流による誘導磁界との相互作用を利用するメモ
リである。 Now, magnetic bubble memory is a phenomenon in which magnetic bubbles are attracted to the magnetic pole of a transfer pattern that is magnetized by a planar magnetic field, and follow the rotation of the planar magnetic field and move along with the transfer pattern, and induction by a signal current flowing through a conductor pattern. This is a memory that uses interaction with magnetic fields.
それで第１図に示すように導体パターン３の上
に形成されている転送パターン５が段差を伴つて
存在する場合に図示の面内磁界が与えられると、
本来パターンの端面部に誘起される磁極６以外に
段差部７にも磁極が誘起され、これが動作特性の
劣化を招きまた誤動作の原因となる。 Therefore, when the transfer pattern 5 formed on the conductor pattern 3 exists with a step difference as shown in FIG. 1, when the illustrated in-plane magnetic field is applied,
In addition to the magnetic poles 6 that are originally induced at the end faces of the pattern, magnetic poles are also induced at the stepped portions 7, which leads to deterioration of operating characteristics and causes malfunctions.
なお転送パターン５に加えられる面内磁界とし
ては駆動コイルによるもの以外にメモリチツプを
上下より挾装する永久磁石の水平成分によるホー
ルド磁界もある。 In addition to the in-plane magnetic field applied to the transfer pattern 5, there is also a hold magnetic field caused by the horizontal component of a permanent magnet that clamps the memory chip from above and below, in addition to that caused by the drive coil.
本発明は転送パターンの段差による特性劣化を
防ぐためのもので第２図に示すように導体パター
ン３の周囲にこれと電気的に絶縁された導体片よ
りなるダミーパターン８を設けることを本旨とす
るものでこれ以外のパターン形成法および層形成
法は第１図に示した従来方法と変らない。 The purpose of the present invention is to prevent characteristic deterioration due to steps in the transfer pattern, and as shown in FIG. Other than this, the pattern forming method and layer forming method are the same as the conventional method shown in FIG.
このように転送パターン５と交叉する導体パタ
ーン３の周囲にダミーパターン８を設ける場合は
樹脂よりなる絶縁層４のレベリング効果により転
送パターン５の段差は無くなり一方、ダミーパタ
ーン８は導体パターン３と同時形成され、また材
質がAuやAl・Cu合金などの金属導体であるため
磁気バブルメモリチツプの磁気的性質に悪影響を
及ぼすことはない。 When the dummy pattern 8 is provided around the conductor pattern 3 that intersects with the transfer pattern 5 in this way, the leveling effect of the insulating layer 4 made of resin eliminates the level difference in the transfer pattern 5. Since the bubble is formed and the material is a metal conductor such as Au or Al/Cu alloy, it does not adversely affect the magnetic properties of the magnetic bubble memory chip.
第３図および第４図は本発明のゲート回路への
実施例で第３図Ａは従来のスワツプゲートの正面
図である。 3 and 4 are embodiments of the gate circuit of the present invention, and FIG. 3A is a front view of a conventional swap gate.
図で基板上にはヘアピン形導体回路９があり、
この上に絶縁層を隔ててマイナループ及びメジヤ
ラインなどの磁気バブル転送パターンが構成され
ている。 In the figure, there is a hairpin conductor circuit 9 on the board.
A magnetic bubble transfer pattern such as a minor loop and a major line is formed on this layer with an insulating layer in between.
図ではメジヤループの一部のみを記しマイナル
ープは〇印１０として省略してある。 In the figure, only a part of the major loop is shown, and the minor loop is omitted as a circle 10.
図で示したスワツプゲートにおいてヘアピン形
導体回路９と交叉しているハーフデイスク形転送
パターン１１には何れも第１図のような段差が生
じ、これが動作特性劣化の原因となつている。 In the swap gate shown in the figure, the half-disk transfer pattern 11 intersecting the hairpin conductor circuit 9 has a step as shown in FIG. 1, which causes deterioration of the operating characteristics.
第３図Ｂはこれに本発明を適用したもので、ス
ワツプゲートを構成するヘアピン形導体９′，
９″，９の間にこれと電気的に絶縁された導体
片よりなるダミーパターン１２′，１２″，１２
を置くことにより、この上に形成される絶縁層の
平坦化を行つたものである。 FIG. 3B shows the application of the present invention to this, in which hairpin-shaped conductors 9',
Dummy patterns 12', 12'', 12 made of conductor pieces electrically insulated between 9'' and 9
By depositing this, the insulating layer formed thereon is planarized.
第４図はリプリケータゲートに本発明を適用し
たもので、ヘアピン形導体の間に角形の導体片よ
りなるダミーパターン１３を置いて平坦化を行つ
たものである。そして、第２図、第３図Ｂ、第４
図におけるダミーパターン８，１２′，１２″，１
２，１３は実際には第５図Ａの如く、短冊状の
ダミーパターン１４を用いたり、また第５図Ｂは
数多くの小さな方形のダミーパターン１５を用い
るものであり、このようにダミーパターンを細分
化すれば駆動磁界による渦電流の発生を抑えるこ
とができるため、不要バブル発生等の悪影響を防
止することができる。 FIG. 4 shows the application of the present invention to a replicator gate, in which a dummy pattern 13 made of rectangular conductor pieces is placed between hairpin-shaped conductors for flattening. And, Figure 2, Figure 3 B, Figure 4
Dummy patterns 8, 12', 12'', 1 in the figure
2 and 13 actually use a strip-shaped dummy pattern 14 as shown in FIG. 5A, and FIG. 5B uses a large number of small rectangular dummy patterns 15. By subdividing, it is possible to suppress the generation of eddy currents due to the drive magnetic field, and therefore it is possible to prevent adverse effects such as the generation of unnecessary bubbles.
本発明は磁気バブルメモリチツプにおいて、導
体パターンの直上に絶縁層を隔てゝ形成されてい
る転送パターンは多くの場合段差がありこれが素
子特性の劣化の原因となつている点に着目し、こ
れを解消するためになされたものであり、本発明
の実施により特性劣化および誤動作発生を無くす
ることができた。 The present invention focuses on the fact that in magnetic bubble memory chips, the transfer pattern formed directly above the conductor pattern with an insulating layer in between often has a step, which causes deterioration of the device characteristics. By implementing the present invention, it was possible to eliminate the deterioration of characteristics and the occurrence of malfunctions.
第１図は導体パターン上に絶縁層を隔てゝ駆動
パターンが形成される磁気バブルメモリチツプの
従来構造を示す断面図、第２図はこれに本発明を
適用したものゝ断面図、第３図および第４図は本
発明の実施例で、第３図Ａは従来のスワツプゲー
ト回路、同図Ｂは本発明の実施例、また第４図は
リプリケートゲート回路の本発明の実施例、第５
図Ａ，Ｂは本発明にかゝるダミーパターンの実施
例である。
図において ３，９，９′，９″，９は導体パ
ターン、４は樹脂絶縁層、５は駆動パターン、
８，１２′，１２″，１２，１３，１４，１５は
ダミーパターン。
Fig. 1 is a cross-sectional view showing the conventional structure of a magnetic bubble memory chip in which a driving pattern is formed on a conductor pattern with an insulating layer in between, Fig. 2 is a cross-sectional view of a chip to which the present invention is applied 4 shows an embodiment of the present invention, FIG. 3A shows a conventional swap gate circuit, FIG. 3B shows an embodiment of the present invention, and FIG.
Figures A and B show examples of dummy patterns according to the present invention. In the figure, 3, 9, 9', 9'', 9 are conductor patterns, 4 is a resin insulation layer, 5 is a drive pattern,
8, 12', 12'', 12, 13, 14, 15 are dummy patterns.
Claims (1)
ンが形成され、この上に絶縁層を隔てて駆動パタ
ーンが形成される磁気バブルメモリチツプにおい
て、前記導体パターンの周辺にこれと電気的に絶
縁されたダミーパターンが該導体パターンと同時
形成されると共に、該ダミーパターンは電気的に
絶縁された複数の細分化パターンとして形成され
ていることを特徴とする磁気バブルメモリチツ
プ。1. In a magnetic bubble memory chip in which a conductive pattern is first formed on a magnetic garnet crystal substrate, and a driving pattern is formed on this with an insulating layer in between, a dummy pattern is provided around the conductive pattern to be electrically insulated from the conductive pattern. A magnetic bubble memory chip characterized in that a dummy pattern is formed simultaneously with the conductive pattern, and the dummy pattern is formed as a plurality of electrically insulated subdivided patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8916981A JPS57205886A (en) | 1981-06-10 | 1981-06-10 | Manufacture of magnetic bubble memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8916981A JPS57205886A (en) | 1981-06-10 | 1981-06-10 | Manufacture of magnetic bubble memory chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57205886A JPS57205886A (en) | 1982-12-17 |
| JPS6321991B2 true JPS6321991B2 (en) | 1988-05-10 |
Family
ID=13963292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8916981A Granted JPS57205886A (en) | 1981-06-10 | 1981-06-10 | Manufacture of magnetic bubble memory chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57205886A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3249317B2 (en) * | 1994-12-12 | 2002-01-21 | 富士通株式会社 | Pattern creation method |
| JP3366471B2 (en) * | 1994-12-26 | 2003-01-14 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54136141A (en) * | 1978-04-14 | 1979-10-23 | Hitachi Ltd | Magnetic bubble memory element and its manufacture |
| JPS54149529A (en) * | 1978-05-17 | 1979-11-22 | Hitachi Ltd | Magnetic bubble element |
| JPS5545159A (en) * | 1978-09-27 | 1980-03-29 | Hitachi Ltd | Magnetic bubble memory element |
-
1981
- 1981-06-10 JP JP8916981A patent/JPS57205886A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54136141A (en) * | 1978-04-14 | 1979-10-23 | Hitachi Ltd | Magnetic bubble memory element and its manufacture |
| JPS54149529A (en) * | 1978-05-17 | 1979-11-22 | Hitachi Ltd | Magnetic bubble element |
| JPS5545159A (en) * | 1978-09-27 | 1980-03-29 | Hitachi Ltd | Magnetic bubble memory element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57205886A (en) | 1982-12-17 |
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