JPS63215279A - Sequence converting circuit for video signal - Google Patents

Abstract

PURPOSE:To decrease the memory capacity required for blocking a 3-dimensional block by applying 1st and 2nd write address control to write a signal in a memory and applying the 1st read address control different from a 1st write address and 2nd read address control in the same sequence as that of the 1st read address to read the signal. CONSTITUTION:An input digital video signal subjected to shuffling is written in a 2-frame memory by the 1st write address control (write 1) at first. The input data of the 4-field next to the input data written by the write 1 is written in a 2-frame memory by the 2nd write address control (write 2). In the write 2, one field is split into 4 and after the data write of 1/4 field, the data by the next 1/4 field is written through the write by each 1/4 field. The head line of each 1/4 field of the same field is read at first by the 2nd read address control from the data written by the write 2 and the next line is read respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal order conversion circuit for converting a digital video signal in television scanning order to three-dimensional block order.

[Summary of the invention]

In this invention, in a video signal order conversion circuit for converting an input digital video signal in a television scanning order into a three-dimensional block order, the data order is converted into three-dimensional blocks.
In order to convert to the order of dimensional blocks, a memory with a capacity equal to the number of frames included in one 3D block and a memory capacity equal to the number of lines included in one 3D block connected to the subsequent stage are used. The address controller of the former memory has a cycle that is twice the number of frames included in one three-dimensional block, and the address controller of the latter memory has a cycle that is twice the number of lines included in one three-dimensional block.
A digital video signal order conversion circuit can be realized with a small memory capacity by having twice the period and each address controller generating an appropriate address so that there is no duplication of data.

[Conventional technology]

When recording/playing digital video signals on a VTR,
In order to compress the amount of data to be transmitted, high-efficiency encoding methods have been proposed in which the number of bits per sample is reduced from the original, eg, 8 bits. As one of these encoding methods, the applicant has proposed A D RC (Adaptive
Dyna+*ic Range Coding).

For example, as described in Japanese Patent Application No. 59-266407, the level difference (dynamic range) between the maximum and minimum values of multiple pixels included in a two-dimensional block is determined, and a code adapted to this dynamic range is used. transformation is done. Furthermore, as described in Japanese Patent Application No. 60-232789, there is a device that performs encoding adapted to the dynamic range with respect to a three-dimensional block formed from pixels in a two-dimensional area included in each of a plurality of frames. Proposed. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. Proposed.

Since the above-mentioned ADRC can significantly compress the amount of data to be transmitted, it is suitable for application to digital VTRs whose data transmission rate is not sufficiently high. ADRC, which performs encoding on a three-dimensional block basis, requires a blocking circuit that converts the order of input digital video signals into the order of three-dimensional blocks.

This blocking circuit requires memory to change the order of pixel data of multiple frames.

For example, if an l-field image is divided into a large number of two-dimensional regions and one three-dimensional block is formed by the two-dimensional regions included in each of two temporally consecutive frames (four fields), A blocking circuit shown in FIG. 27 was used.

In FIG. 27, 22A and 22B indicate 2-frame memories, and the input digital video signal from the input terminal 21 is transferred to the 2-frame memory 22 via the switch circuit 23.
Written to one of A and 22B. Data read from the other of the two frame memories 22A and 22B is taken out to the output terminal 25 via the switch circuit 24. The switch circuits 23 and 24 each have a terminal a connected to the 2-frame memory 22A and a terminal A connected to the 2-frame memory 22B.

The connection states of the switch circuits 23 and 24 are switched every two frames, and during the two frame period when one of the switch circuits 23 and 24 is connected to the terminal a side, the other one is connected to the terminal a side. Ru. Therefore, the bank switching signal from the terminal 26 is supplied to the 2-frame memory 22A and the switch circuit 23, and the bank switching signal inverted by the inverter 27 is supplied to the 2-frame memory 22B and the switch circuit ''R124.

Address controllers 28 and 29 are provided, the address signal formed by the address controller 28 is supplied to one terminal C of the switch circuits 30 and 31, and the address signal formed by the address controller 29 is supplied to the other terminal C of the switch circuits 30 and 31. is supplied to terminal d of. The output signal of the switch circuit 30 is supplied as a write address to the two frame memories 22A and 22B, and the switch circuit 3
The output signal 1 is supplied to the 2 frame memories 22A and 22B as a read address.

The address controller 29 and the switch circuit 31 are controlled by a mode switching signal from a terminal 33, and the switch circuit 30 is controlled by a mode switching signal passed through an inverter 32.

This mode switching signal is for specifying each of the blocking operation and the block decomposition operation. During the blocking operation, the address signal generated by the address controller 28 is used as a write address, and the address signal generated by the address controller 29 is used as a read address. On the other hand, during the block decomposition operation, the address signal generated by the address controller 28 is used as a read address, and the address signal generated by the address controller 29 is used as a write address. In this way, the relationship between the write address and the read address is reversed between the blocking operation and the block decomposition operation, and the phase relationship between the write operation and the read operation is different. When forming blocks, input data in the order of television scanning is written into the 2-frame memories 22A and 22B in the order in which they are input manually, and the data of the three-dimensional block is created by controlling the read address. Output data converted to @ order is obtained.

[Problem that the invention seeks to solve]

In the above configuration, two 2-frame memories are required, which increases the memory capacity and increases the circuit scale including the memory control circuit.Therefore, the object of the present invention is to An object of the present invention is to provide a video signal order conversion circuit that can reduce the memory capacity when converting dimensional blocks into blocks.

[Means for solving problems]

In this invention, a first predetermined amount of the input digital video signal is written to the memory by a first write address control (write l), and a second predetermined amount of the digital video signal following the first predetermined amount is written to the memory by a first write address control (write l). The data written to the memory by write address control (write 2) is read out by the first read address control (read 1) different from write l, and the data written by write 1 is read out by the first read address control (read 1) different from write l.
The data written by WRITE 2 is read by the second read address system m (READ 2) to obtain read data in the same order as the data read by WRITE 1, and the data written by WRITE 1 is different from WRITE 2. Light 2. Lead 1. Address control consisting of lead 2 is performed in return.

[Effect]

Write 1 writes four fields of the input digital video signal to the two-frame memory 51 in the order of input (television scanning order).

The next four fields of input digital video signals are written into the two-frame memory 51 by write 2. The data written under the write 1 address control is read out from the 2-frame memory 51 by the read 1. Data written to the 2-frame memory by write 2 is read from the 2-frame memory by read 2.

In this way, data of four fields are sequentially outputted from the two-frame memory 51 in the order of every eight lines, for example, the number of lines included in one three-dimensional block.

After the 2-frame memory 51 blocks the data in the time axis direction, it blocks the data in the horizontal and vertical directions. That is, if the number of pixels in one line in one block is, for example, four, output data in the order of a three-dimensional block consisting of four pixels included in each of eight lines is obtained. An 8-line memory is used for this horizontal and vertical blocking. The 9-line memory 52 is used in consideration of the case where the number of pixels Nh in one line is not divisible by 8.

A three-dimensional block, in which an l block consists of 32 pixels (4 pixels x 2 (lines) x 4 (fields)), can be created with a memory capacity of (2 frames + 9 lines memory). Capacity can be reduced.

〔Example〕

This invention will be explained below. This description will follow the order of the items below.

a, recording side and shuffling circuit A, reproducing side and deshuffling circuit C, block and blocking circuit d, 2-frame memory address control e, 9-line memory address control a, recording side and shuffling circuit 1 The figure shows the overall configuration of the recording side. In FIG. 1, a digital video signal having a sampling frequency of 13.5 (MHz), for example, is supplied to an input terminal indicated by 1. This input digital video signal is supplied to a shuffling circuit 2 shown surrounded by a broken line. The shuffling circuit 2 converts the order of the video data into an order different from the television scanning order. The output signal of the shuffling circuit 2 is supplied to the blocking circuit 3, where it is converted into three-dimensional block order data.

The output data of the blocking circuit 3 is sent to the ADRC encoder 4.
The ADRC encoder 4 supplies output data whose data amount has been compressed.

In the ADRC encoder 4, the minimum value MIN for each block
, maximum value MAX, dynamic range DR (=MAX-
MIN) is detected, the number of bits corresponding to the dynamic range DR is set, the dynamic range DR is divided into a number of level ranges determined by this number of bits, and a code corresponding to the level range to which the pixel data after minimum value removal belongs is set. A signal DT is formed.

Two additional data such as the dynamic range DR, the minimum value MIN, and the code signal DT are supplied to the framing circuit 5.

In the framing circuit 5, the above data from the ADRC encoder 4 is converted into recording data having a frame structure. The framing circuit 5 encodes an error correction code as necessary.

Recorded data is taken out to an output terminal 6 of the framing circuit 5 and recorded on a magnetic tape by a rotating head (not shown).

If encoding is performed in units of three-dimensional blocks, AD
Not limited to RC, other encoding methods may be applied.

The shuffling circuit 2 is a field memory 7A.

7B, and input digital video signals are written into these field memories 7A and 7B via a switch circuit 8 for each field.

Also, field memory? Data for one field read out alternately from A and 7B is supplied to the blocking circuit 3 via the switch circuit 9. The switch circuit 8 and the switch circuit 9 are switched for each field and operate in opposite phases.

For example, in a field where one switch circuit 8 is connected to the terminal a side, the other switch circuit 9 is connected to the terminal a side.

Writing data to field memories 7A and 7B or these field memories? When reading data from A and 7B, either the write address or the read address (one of them is controlled for shuffling).

- By way of example, the input digital video signals are written to the field memories 7A, 7B in the order of input (i.e. in the order of television scanning) and the field memories 7A, 7B
.

Digital video signals are read out from 7B in a different order from the input.

Figure 3 conceptually shows shuffling.
Input digital video signals are written into one field memory in input order, and the contents of this one field memory are read out during the next field period. Shuffling is performed in units of two-dimensional regions numbered in FIG.

A three-dimensional block is formed by a set of four two-dimensional regions at corresponding positions in four consecutive fields (two frames). When reading from the field memory, the two-dimensional areas in the input field that are spatially close to each other (in FIG. 3, nine two-dimensional areas are shown as an example) are read out so that they are spatially separated. The addresses are controlled and a shuffled output field is obtained. This shuffling disperses burst errors that occur during the recording/reproducing process of the VTR, making the errors less noticeable in the reproduced image.

b: Reproducing side and deshuffling circuit FIG. 2 shows the overall configuration of the reproducing side. In FIG. 2, an input terminal indicated by 11 is supplied with a digital reproduction signal reproduced by a VTR.

This digital reproduction signal is supplied to the frame decomposition circuit 12, and the dynamic range DR2 minimum value M for each block is
IN and code signal DT are separated. The output signal of the frame decomposition circuit 12 is supplied to the ADRC decoder 13,
The original pixel data is restored. The output signal of the ADRC decoder 13 is in block order and is therefore supplied to the block decomposition circuit 14. The output signal of the block decomposition circuit 14 is supplied to a deshuffling circuit 15 shown surrounded by a broken line. The deshuffling circuit 15 is for returning the order of data to the original order, that is, the order of television scanning, contrary to the shuffling circuit 2 on the recording side, and its output terminal 16
A playback digital video signal is obtained.

Similar to the shuffling circuit 2, the deshuffling circuit 15 includes two field memories 17A.

17B and switch circuits 18 and 19. The switch circuits 18 and 19 are connected to the field memory 17A.
The terminal A is connected to the field 17B, and the terminal A is connected to the field 17B. In a certain field, these switch circuits 18 and 19 are connected to the terminal a side, so that the field memory 17A performs a write operation and the field memory 17B performs a read operation. In the next field, the connection states of the switch circuits 18 and 19 change to a state where a terminal is selected. Therefore, the field memory 17A becomes the read state, and the field memory 17B
is in the writing state. By controlling at least one of the read address and the write address,
It is returned to a state without shuffling.

C. Block and blocking circuit FIG. 4 shows a three-dimensional block in this embodiment. In FIG. 4, fl, f2° [3, f4 are
Each of the two-dimensional regions of four temporally continuous fields is shown. The size of one two-dimensional area is (2×4 pixels). Therefore, one block includes 32 pixel data.

The blocking circuit 3 converts the shuffled pixel data for each field into [line Lll of field f1→line L12 of field f1 - line L of field f2].
21-Field “2 line L22 → field f3
Line L31 → Line L32 of field f3 → Line L41 of field f4 - Line L of field r4
42) (The order of the four pixel data in each line is
scan order).

FIG. 5A shows the basic configuration of an example of the blocking circuit 3, and FIG. 5B shows the basic configuration of the block decomposition circuit 14. Input data from an input terminal indicated by 41 in FIG. 5A is supplied to a 2-frame memory 42, and processed into blocks in the time axis direction. That is, the order of input data of two temporally consecutive frames (four fields) constituting one block is converted. 4 fields fl, f2°f3. [The first line of each of 4 is Lll, L
21, L31. When L41 is set, the 2 frame memory 42 allows (Lll-4L21→L31-L41
) the data order is changed to the order of The data order of the second line is also changed in a similar order.

The output data of the 2-frame memory 42 is transferred to the 9-line memory 4.
3 (has a capacity for 9 lines). This 9-line memory 43 performs horizontal and vertical blocking, and in the case of the block shown in FIG.
L12 L21 L22...L41.
All data included in the line L42 is written to the 9-line memory 43. Then, from the 9-line memory 43 to the output terminal 44, the order (
In other words, the output data (block order) is obtained. The reason why the capacity for 9 lines is provided is to cope with the case where the number of pixels in one line is not divisible by 8, as will be described later.

In FIG. 5B, block order input data is supplied to an input terminal 45 and supplied to a 9-line memory 46. In FIG. The 9-line memory 46 performs block decomposition in the horizontal and vertical directions, and the output data of the 9-line memory 46 is supplied to the 2-frame memory 47. This 2-frame memory 47 performs block decomposition in the time axis direction, and output data in the same order as television scanning is obtained at the output terminal 48.

The 2-frame memory and the 9-line memory can also be used for the blocking circuit 2 and the block decomposition circuit 15. FIG. 6 shows an example of a blocking/block decomposition circuit. In FIG. 6, 51 indicates a 2-frame memory, and 52 indicates a 9-line memory.

A switch circuit S1 and a switch circuit S2 are connected to the data input/data output side of the 2-frame memory 51, respectively, and a switch circuit S3 and a switch circuit S4 are connected to the data input/data output side of the 9-line memory 52, respectively. be done. Switch circuits S5 and S6 are connected to the data input terminal 53 and the data output terminal 54, respectively. Switch circuits S7 and S8 are respectively connected to the address signal supply path of the 2-frame memory 51, and the 9-line memory 52
Similarly, switch circuits S9 and SIO are respectively connected to the address signal supply path. The output signal of the switch circuit S7 is supplied to the 2-frame memory 51 as a write address, and the output signal of the switch circuit S8 is supplied to the 2-frame memory 51 as a read address. Further, the output signal of the switch circuit S9 is supplied to the 9-line memory 52 as a write address, and the output signal of the switch circuit 310 is supplied to the 9-line memory 52 as a read address.

Address signals for the 2-frame memory 51 are generated by frame memory control circuits 55 and 56, and address signals for the 9-line memory 52 are generated by line memory control circuits 57 and 58. Timing signals are received and passed between frame memory control circuits 55 and 56, and timing signals are similarly received and passed between line memory control circuits 57 and 58.

Switch circuits 81 to S10 and frame memory control circuit 5
5 and the line memory control circuit 57 are supplied with a mode switching signal from a terminal t to switch between blocking operation and block decomposition operation. When functioning as the blocking circuit 3, the switching circuits 81 to SIO are connected to the terminal a side, as shown in FIG. 6, and when functioning as the blocking circuit 14, the switching circuits 81 to SIO
10 is connected to the terminal side.

When the switch circuits 31 to S10 are connected to the terminal a side, input data from the input terminal 53 is connected to the switch circuit S5.
and 81 to the 2-frame memory IJ51, and data read from the 2-frame memory 51 is written to the 9-line memory 52 via switch circuits S2 and S3. Data read from the 9-line memory 52 is taken out to the output terminal 54 via switch circuits S4 and S6. During this blocking operation, the address signal formed by the frame memory control circuit 55 is supplied as a write address to the 2-frame memory 51,
An address signal formed by the frame memory control circuit 56 is supplied to the 2-frame memory 51 as a read address. Similarly, the address formed by the line memory control circuit 57 is supplied to the 9-line memory 52 as a write address, and the address formed by the line memory control circuit 58 is supplied to the 9-line memory 52 as a read address.

During the block disassembly operation in which the switch circuits 81 to S10 are connected to the terminal side, input data from the input terminal 53 is transferred to the 9-line memory 52 via the switch circuits S5 and S3.
The data read from the 9-line memory 52 is written to the 2-frame memory 51 via the switch circuits S4 and Sl, and the data read from the 2-frame memory 51 is written to the 2-frame memory 51 via the switch circuits S2 and S6. It is taken out to the output terminal 54. During this block decomposition operation, the frame memory control circuit 55 and line memory control circuit 57 form a read address, and the frame memory control circuit 56 and line memory control circuit 58 form a write address. That is, in the blocking operation and the block decomposition operation, the address signals for the 2-frame memory 51 and the 9-line memory 52 have an opposite relationship between the write address and the read address.

d. Address control of 2-frame memory Address control of the 2-frame memory 51 when forming blocks will be described below. This address control is
It is performed periodically in the order of [Write 1 → Read 1 → Write 2 → Read 2] so that it is completed in four frames. 7th
Figures 8 and 9.

For simplicity, FIG. 10 shows address control assuming that one field is composed of 12 lines. The addresses of the two frame memories are Ax and Ay.

given by Az. Ax indicates an address in the horizontal direction (in units of pixels), AV indicates an address in the vertical direction (in units of lines), and Az indicates an address in the time direction (in units of fields).

The shuffled input digital video signal is first written into the 2-frame memory under write 1 address control. When address control is performed in write 1 mode, two frames are written to the memory in the order of input, as shown in FIG. 7A, FIG. 7B, and FIG. 7C. That is, the address Az (FIG. 7C) is increased stepwise for each field of input data, and the address A
y (FIG. 7B) is increased stepwise from 0 to 12 line by line within one field.

The data written in Write 1 is read from the 2-frame memory under address control in Read 1. 8th
As shown in FIG. A, FIG. 8B, and FIG. 8C, in read 1, four lines corresponding to four fields are sequentially read out. That is, address Ay (Fig. 8B) is (θ~11)
Address Az (FIG. 8C) is changed to 0.1.2.3 while it is fixed at a predetermined line in . The write 1 and read 1 operations described above create blocks in the time axis direction using two frame memories.

The four fields of input data following the input data written in Write 1 are written to the 2-frame memory in Write 2. Figure 9A, Figure 9B.

As shown in FIG. 9C, in write 2, one field is divided into four, and after writing the data for A field, the data for A field of the next field is written, so that each A field is written. Ru. That is, 1
If the field has 12 lines, 1 field has 3 lines.
It is divided into lines, and while the address Az (C in FIG. 9) is between predetermined values, the address ly (B in FIG. 9) repeats changes for three lines.

The data written in write 2 is read out under address control in read 2. As shown in Figures 10A, 10B, and 10C, in read 2, the first line of each A field of the same field is read out first, and then the second line of each is read out. Read out.

When this read operation is completed for that one field, a similar read operation is performed for the next field. That is, during the l field period when the address Az (FIG. 10C) is a predetermined value, the address Ay (first
0 figure B) is (0, 3, 6, 9) (1, 4° 7.10
)(2,5,8,11).

The next data written in write 2 is again written to the 2 frame memory under the address control of write 1. By the address control of 0 or more, the data read from the 2 frame memory is data of 4 temporally continuous fields. The first lines of 4 are output in order, and then these 4
The second lines of the fields are output in sequence, and in the same way, the corresponding lines of the four fields are output in sequence.

FIG. 11 is a diagram showing the phase relationship between a write operation and a read operation in a 2-frame memory when one field is composed of 12 lines.

In FIG. 11, the vertical line indicates the length corresponding to the period during which one line of data occupies the corresponding address in the two-frame memory.

That is, data written at the timing of one end on the upper side of this vertical line is read out at the timing of the other end on the lower side. The field order of input data is [f01→
f02→f03→f04→fil→f12...
...f23→f24], the input data of the first four fields is sequentially written to the 2-frame memory under the address control of write 1, and then this data is written from the 2-frame memory under the address control of read 1. Read out sequentially. From the middle of this read 1 period, the input data of the next field f11 is written into the 2-frame memory under address control of write 2. From the middle of the write 2 period, the written data is read out under the read 2 address control. From the middle of the read 2 period, the input data of the next field f21 is written 1.
is written under address control. As shown in FIG. 11, the vertical lines do not overlap, so that the input data is written to the 2-frame memory without excess or deficiency, and is read out without any loss.

In general, data written first in line l-1 is read by read 1 at a timing of (3Nf-3) lines, assuming that the number of lines in the ■ field is Nf.

The above is the address control of the 2-frame memory during the blocking operation. Address control during block decomposition involves swapping the write address and read address.

FIG. 12 shows a specific example of an address counter for controlling the address performed during the aforementioned blocking. In FIG. 12, CTx represents a counter for generating the address ^X, and CTy-LCTy -2 indicates a counter for generating address Ay, and CTz indicates a counter for generating address Az. The counter CTx has a count range of (0-Nh-1) when the number of pixels included in one line is Nh, and the weight of one count is 1. Counter CTy-1 has address Ay
When the maximum value of is Nv (-4Xm, where m is a natural number), it has a count range of (0 to 'A N v -1), and the weight of one count is 1. The counter CTy-2 has a count range of (0 to 3), and the weight of one count is 'A N v. Counter CTZ is (0 to 3)
It has a count range of , and the weight of 1 count is 1 (1 field).

4 counters CTx, CTy-1, CTy-2, ,C
Tz is configured to transmit the carry output of the lower counter to the upper counter. In FIG. 12A, a carry output is transmitted in order from a lower counter to an upper counter, and an address signal in the case of write 1 is formed.

As shown in FIG. 12B, the carry output of counter CTx is transmitted to counter CTz, the carry output of counter CTZ is transmitted to counter CTy-1, and counter C
The address for lead l is formed by the configuration in which the carry output of Ty-1 is transmitted to counter CT31-2.

As shown in FIG. 12C, the carry output of counter CTx is transmitted to counter CTy-1, and counter c'ry
The address for write 2 is formed by the configuration in which the carry output of -t is transmitted to the counter CTz, and the carry output of the counter CTz is transmitted to the counter CTy-2.

As shown in Figure 12, the carry output of the second counter CTx is transmitted to the counter CTV-2, and the carry output of the second counter CTx is transmitted to the counter CTV-2.
The address for lead 2 is formed by the configuration in which the carry output of lead 2 is transmitted to counter CTy-1 and the carry output of counter CTy-1 is transmitted to counter CTz.

As is clear from FIG. 12, the address counter requires systems corresponding to four types of address control. However, write 1 and write 2 do not overlap in time, only one counter configuration is required for address control during write operation, and switching between write 1 and write 2 is as follows:
The connection relationship between the counters may be switched using a gate circuit. Similarly, only one counter configuration is required for address control during a read operation, and the configuration of read 1 and 2 can be changed by switching the connection relationship between the counters.

e.Address control of 9-line memory By blocking using the 2-frame memory described above, it is necessary to construct a 3-dimensional block in 4 temporally continuous fields (2 lines x 4 = 8 lines). The data was divided into continuous blocks in the time direction. Next, 9
Each line is divided into four pixel data by the line memory, and the four pixels belonging to each of the eight lines are grouped into blocks in the horizontal and vertical directions.

Blocking using this 9-line memory will be explained below. For ease of understanding, one field consists of 8 lines, and the number of pixels in each line is a number divisible by 8 (8
The address control of the 9-line memory (n) is performed at the cycle of [Write 1-Read 1-Write 2-Read 2].

As shown in FIG. 13A, the first 8 lines of input data are written to the 9-line memory in the order in which they are input (
Write 1), the 9th line of the 9-line memory contains
No data is written. As shown in FIG. 14A, the next eight lines of input data are written into eight lines for every n pixels formed by dividing each line into eight (Write 2).

As shown in FIG. 13B, the data written by write 1 address control is read out for each pixel at the same position in the vertical direction (read 1), and the data in these four consecutive columns ( A total of 32 pixel data) constitute one three-dimensional block. Furthermore, as shown in FIG. 14B, the data written by write 2 address control is read out every four pixels in the horizontal direction of each line (read 2), and the reading of one line is completed. Then, the next line is read out in the same way. The data read out under the address control of read 2, similar to the data read out under the address control of read 1, consists of 32 temporally consecutive pixel data forming one three-dimensional block. .

Address control of the above-mentioned 9-line memory will be explained using an example in which the number of pixels Nh in one line is 32 (n=4). When controlling the address of write 1, as shown in FIGS. 15A and 15B, the address /ly is (0, 1,
2,...7), and within the period when the address Ay is a predetermined value, the address ^X increases to (0, 1, 2,...31.3).
2 (-0)).

When controlling the address of lead 1, see Figure 16A and Figure 16.
As shown in Figure B, the address AV increases as (0, 1, 2...7°8(-0)) during the period when the address 8K is a predetermined value, and the pixels at the same position are on each line. are read out sequentially.

When controlling the write 2 address, FIGS. 17A and 17
As shown in Figure B, the address Ax is (0°1.2.3)
The address AV is incremented each time the address AV changes.

When controlling the address of lead 2, FIGS. 18A and 18
As shown in Figure B, the address Ay is incremented every 32 pixel data period, and the address Ax is a discrete value (0, 4, 8°...28) (1, 5
,9,...29)... (3,7,11,...
...31).

FIG. 19 is a diagram showing the phase relationship between a write operation and a read operation in a 9-line memory. Similar to FIG. 11 described above, in FIG. 19, the closed area indicates a period during which one line of data occupies a predetermined address in the nine-line memory. That is, data written at the timing of one end on the upper side of this closed area is read out at the timing of the other end on the lower side. The first 8 lines of input data are sequentially written into the 9-line memory under the write l address control, and then this data is sequentially read from the 9-line memory under the read l address control. From the middle of this read 1 period, the next 8 lines of input data are written into the 9 line memory under write 2 address control. From the middle of the write 2 period, this written data is read 2 under address control.
Read out. From the middle of the read 20 period, the next 8 lines of input data are written under write 1 address control. As shown in FIG. 19, the closed regions do not overlap each other, and therefore the input data is 9 lines without too much or too little.
is written to the online memory and read without any loss.

Generally, the first 8 lines of input data written into the 9 line memory are read out at the data timing of (7Nh-7).

The above is the address control of the 9-line memory during the blocking operation. Address control during block decomposition involves swapping the write address and read address.

Further, address control when the number of pixels Nh in one line is not divisible by 8 will be described below.

As described above, address control is performed in the cycle of [Write 1→Read 1→Write 2→Read 2].

As shown in FIG. 20A, in write 1 address control, input data is sequentially written from the first line in the order of input. The 9-line memory has horizontal addresses corresponding to the number of pixels Nh in one line. This number of pixels N
h is (8n+Δ). Data written under write 1 address control is read from the 9-line memory under read 1 address control. As shown in FIG. 20B, in lead 1, pixel data at the same position in the vertical direction is sequentially read out. These write 1 and read 1 address controls are performed based on the number of pixels in one line, Nh.
This is the same as when is divisible by 8.

When writing the next 8 lines of input data, each group consisting of n pixel data and mod, (Nh.

8), and these groups are written over nine lines as shown in FIG. 21A (Write 2). Data written under write 2 address control is read from the 9-line memory under read 2 address control.

As shown in FIG. 21B, in read 2, reading is performed intermittently in the horizontal direction for every four pixels.

Address control when the number of pixels in one line Nh is not divisible by 8 will be explained assuming (Nh=34). Second
Figure 2 shows addresses ^X and AV when data is written by the write l operation.

Address Ay (Figure 22B) is (0, 1, 2,...
・7), the address is increased every 34 pixels, and within the period when the address Ay is a predetermined value, the address Ax (Fig. 22A) becomes (0,
1, 2, ... 34).

The data written by the write 1 operation described above is
It is read by the read 1 operation.

FIG. 23 shows addresses 8X and Ay when data is read out by the operation of lead 1. In read 1, pixel data at the same position in the vertical direction is sequentially read out from each line, so address Ax (23rd Figure A) is (0
, 1, 2, ... 34), and is increased every 8 pixels, and within the period of the predetermined value of the address Ax, the address Ay
(Fig. 23B) is changed to (0°1.2...7).

FIG. 24 shows that during the period in which input data of 34 pixels for one line, which indicates the addresses Ax and Ay at the time of data writing, is supplied by the operation of write 2, the address Ay
(Fig. 24B) every 4 pixels (0, 1° 2, ... 8)
It changes. Further, within this four-pixel period, the address Ax (FIG. 24A) is changed to (0°1.2.3).

The data written in this write 2 is read out from the 9-line memory by the read 2 operation.

As shown in FIG. 25B, the address Ay changes to (0, 1, 2...8) for each line period.

During the period of one line in which the address Ay is a predetermined value, the address Ax (FIG. 25A) changes intermittently every four times, and one line of data is read by changing the address Ax four times.

FIG. 26 shows a specific example of an address counter for performing address control during the aforementioned blocking in the horizontal and vertical directions. In FIG. 26, CTx-1 and CTx-2 represent counters for generating address Ax, and CTy represents a counter for generating address ^y. The counter CTx-1 is (0 to int
(Nh/8)-1), and the weight of one count is one pixel (however, in the horizontal direction). The counter CTx-2 has a count range of (0 to 8), and the weight of one count is int (Nh/8) (however, in the horizontal direction). The counter CTy has a count range of (0 to 8), and each count has a weight of 1 (in the vertical direction).

FIG. 26A shows a connection configuration of a counter and a gate circuit when performing write 1 address control.

FIG. 26B shows the connection configuration of the counter and gate circuit when controlling the address of lead 1. Figure 26C is
This is a connection configuration of a counter and a gate circuit when performing address control for write 2. Figure 26 shows the connection configuration of the counter and gate circuit when controlling the address of lead 2.

As is clear from FIG. 26, the address counter requires systems corresponding to four types of address control. However, similar to the control of a two-frame memory, write 1 and write 2 do not overlap in time, and only one counter configuration is required for address control during write operation. The switching is done by the gate circuit.
All you have to do is switch the connection relationship between the counters. Further, for address control during read operation, only one counter configuration is required, and lead 1 and lead 2 can be changed by switching the connection relationship between the counters.

〔Effect of the invention〕

According to this invention, three-dimensional blocks can be divided into blocks using a small memory capacity.

In other words, the number of frames included in one three-dimensional block and 1
Blocking processing can be performed using a memory with a capacity equal to the number of lines included in each three-dimensional block.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the recording side of a digital VTR in which the blocking circuit according to the present invention is used, and FIG.
The figure is a block diagram showing the configuration of the playback side of a digital VTR in which a blocking circuit is used, FIG. 3 is a route diagram showing an outline of shuffling, and FIG. 4 is for explaining the three-dimensional blocks in this embodiment. Figures 5 and 6 are block diagrams of the blocking circuit and block decomposition circuit, and Figures 7, 8, 9, and 10 are block diagrams of the two-frame memory provided in the blocking circuit. 11 is a route diagram for explaining the address control of the 2-frame memory. FIG. 12 is a block diagram showing the configuration of the address counter of the 2-frame memory. Figure 14 is a route map for explaining the writing and reading of data to the 9-line memory, Figures 15 and 16.
figure. FIGS. 17, 18, and 19 are route maps for explaining address control of a 9-line memory, and FIGS. 20 and 21 are
The figure is a route map for explaining other examples of writing and reading data to and from a 9-line memory, and Figures 22, 23, 24, and 25 are for explaining other examples of address control. FIG. 26 is a block diagram showing the configuration of an address counter of a 9-line memory, and FIG. 27 is a block diagram showing the configuration of an example of a blocking circuit. Explanation of main symbols in the drawings 1: Digital video signal input terminal, 2: Shuffling circuit, 3 niblock circuit, 14 niblock decomposition circuit, 15: Deshuffling circuit, 51: 2 frame memory, 52: 9 Line memory, 53: Data input terminal, 5
4: data output terminal, 55.56: frame memory control circuit, 57.58 two-line memory control circuit. Agent Patent Attorney Tadashi Sugiura (Fig. 2 f M Fig. 4) - Waffy/l/l' i-Ko Feel "Shuffling No. 3 v! J 33 Fig. 27 - Ax -A X A x A x Fig. 10 t2 51 t1 Fig. 13 A 'J-to°1 Fig. 13 day Fig. 12 A 'I-t'1 Lee 12 A--1mu k+-- Leet'2 Fig. 14B Light 1 No. 16 Figure Light 2 Figure 18 Riito 2 A x Light 1 x Lee 11 Figure 20 B A x X ・I-1:'2 Figure 21 B Uiro Rito'2
Puito 2
REIT 2 Figure 26C Figure 26D

Claims (1)

[Claims] A first predetermined amount of an input digital video signal is written to the memory by a first write address control,
A second predetermined amount of the digital video signal following the predetermined amount of is written to the memory by second write address control, and the data written by the first write address control is written to the memory by the first write address control. is read by a different first read address control, the data written by the second write address control is different from the second write address control, and the data read by the first read address control. The address control consisting of the first and second write address control and the first and second read address control is repeated. 1. A video signal order conversion circuit characterized in that the circuit is constructed as follows. A video signal order conversion circuit comprising: