JPS63215181A - Control device for extracting clock phase of teletext data extracting circuit - Google Patents

Abstract

PURPOSE:To extract correct teletext data by switching the phase of an extracting clock and feeding back a detection output from an error detecting circuit so as to reduce it when the phase of a character signal is shifted from a normal value due to ghost or group delay. CONSTITUTION:When the phase of a character signal to be sampled is shifted from the normal value to the advanced side or the delayed side due to ghost, group delay or noise, the detection output of the error rate detecting circuit 15 is changed. A clock phase control circuit 19 controls a clock phase switching circuit 10 on the basis of the detection output so that the phase of the extracting clock is switched to the advanced side or the delayed side and the detection output of the circuit 15 is fed back in the reducing direction (error rate reducing direction). Consequently, a noise margine corresponding to an interval between a character signal value and a slice level at the rising time of the extracting clock can be maximized and the teletext data can be correctly extracted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sampling clock control device for a teletext data extraction circuit of a teletext receiver.

[Prior Art] In a conventional teletext data extraction circuit, the phase of a sampling clock for extracting teletext data from a received video signal is fixed.

[Problems to be Solved by the Invention] For this reason, the waveform of the received video signal is distorted due to ghosts, group delay, noise, etc., and the phase of the character signal sampled by the sampling circuit is changed to the solid line (0) in FIG. 2(a). If it deviates from the normal value shown by the dotted line (P) or chain line (Q), the phase-locked sampling clock shown in (b) of the same figure
If the sampling is performed with , the noise margin (N) becomes small and there is a problem that correct teletext data cannot be obtained.

The present invention has been made in view of the above-mentioned problems, and it is possible for the teletext data extraction circuit to always extract correct teletext data even if a phase shift occurs in the character signal to be sampled due to ghosting, group delay, noise, etc. The purpose is to obtain a control device that can

[Means for Solving the Problems] The present invention provides a sampling circuit that extracts teletext data from a received video signal by sampling using a sampling clock. a circuit, an erroneous car detection circuit for detecting an error rate of the teletext data obtained by the sampling circuit, and a detection output of the erroneous car detection circuit.

The present invention is characterized by comprising a clock phase control circuit that switches and controls the clock phase switching circuit in a direction in which the error rate decreases.

[Operation] When the phase of the character signal to be sampled deviates from the normal value to the lead side or lag side due to ghost, group delay, noise, etc., the detection output of the erroneous vehicle detection circuit changes. Based on this detection output, the clock phase control circuit controls the clock phase switching circuit to switch the phase of the sampled clock to the leading side or the lagging side, thereby decreasing the detection output of the error car detection circuit (i.e., reducing the error rate. Feedback control is performed in the direction of decreasing Therefore, correct teletext data can be extracted.

[Embodiment] Figure 1 shows an embodiment of the present invention. In this figure, (1) is a video signal input terminal received by a teletext receiver and led from a video signal processing circuit. . The video signal input terminal (1) is connected to a sampling circuit (6) via a waveform equalization circuit (5) that includes an A-D conversion circuit (2), a digital filter circuit (3), and a mixing circuit (4). It is connected.

The video signal input terminal (1) is connected to a PLL (Ph
5, 7 locked using aseLock 1oop)
A sampling clock generation circuit (7) that outputs a sampling clock of 3 MHz is connected. The output side of this sampling clock generation circuit (7) has a delay time in five stages (
For example, if the repetition period of a 5.73 MHz sampling clock is T, then the delay time is above T (approximately 18 degrees in phase angle).
, 1 knife.

The delay circuit (8
1) (8□) (s, ) (g, ) (s, ) and these delay circuits (at) (L) (g, )
A clock phase switching circuit (10) consisting of a changeover switch (9) that switches and outputs one of (g, ) (8s) is connected. The extraction circuit (6) includes a character signal extraction circuit (11) that extracts a character signal from the signal output from the waveform equalization circuit (5), and a character signal extraction circuit (11) that extracts a character signal from the character signal extraction circuit (11). An input data counter (12) samples the sampling clock output from the clock phase switching circuit (10) and outputs the sampled value as 3-bit data, and an input data counter (12) that switches the slice level to 8 stages (3-bit data). A slice level counter (13) as an output slice level switching circuit, and the input data counter (13).
12) to the slice level counter (1).
Compare with the output data of 3), and if the former is large, set it to '1''.
, and a comparator (14) that outputs 0'' data when the latter is larger. On the output side of the comparator (14) is a BEST (error correction circuit).
(15) is connected, and this BEST (15) corrects errors in the teletext data output from the sampling circuit (6) and sends it to a program memory (not shown). Said BES
T (15) detects the error rate (for example, error occurrence number data D, which is the number of error bits per packet) of the teletext data output from the sampling circuit (6), and transmits this detected data to the signal line (16). It also serves as an error vehicle detection circuit that outputs the output via the .

(17) is 1. m(7)CP
U (17) is connected from the BEST (15) to the signal line (16
), the filter constant of the digital filter circuit (3) of the waveform equalization circuit (5) is varied in the direction of decreasing the error number data (that is, the error rate is a filter constant control circuit (18) that performs feedback control in a direction in which the number of errors decreases; and a filter constant control circuit (18) that performs feedback control in a direction in which
), a clock phase control circuit (19) performs feedback control in a direction to decrease the error occurrence number data, and a slice level of the slice level counter (13) is switched based on the error occurrence number data. , and a slice level control circuit (20) that performs feedback control in the direction of reducing error occurrence number data.

Next, the operation of the embodiment described above will be explained with reference to FIGS. 2 to 5.

(A) First, filter constant control will be explained.

The waveform of the received video signal is distorted due to ghosting, group delay, noise, etc., and the waveform of the signal input to the waveform equalization circuit (5) is distorted.
16) exceeds the allowable error occurrence number data D0, the filter of the digital filter circuit (3) is activated based on the control signal from the filter constant control circuit (18) of the CPU (17). constant is controlled, D
Feedback control is performed in the direction in which the value becomes 00 or less. Here, D is a number that is greater than or equal to the number of bits that can be error corrected in BEST (15) (for example, 8 bits when errors can be corrected up to 8 bits in one packet (296 bits)) and that is an acceptable error occurrence. Set to numerical data.

(B) Next, phase control of the extracted clock will be explained using FIGS. 2 and 3. The waveform of the received video signal is distorted due to ghosting, group delay, noise, etc., and the character signal appearing on the output side of the character signal extraction circuit (11) of the extraction circuit (6) is indicated by the solid line (0) in Fig. 2(a). It is assumed that there is a shift from the normal value shown to the delayed side or the advanced side as shown by the dotted line (P) or the chain line (Q).

(a) When the shift is to the delay side shown by the dotted line CP), in the initial state, for example, the changeover switch (9) of the white/white phase switching circuit (10) is connected to the output side of the delay circuit (83), The initial setting of the extraction clock ■ is set.

(b) Next, CPU (17) selects BEST (1
Check the error occurrence number data D output from 5) via the signal line (16), and check whether r D > Do? ” and
If it is rNOJ, there will be fewer errors, so use the sample clock■
Teletext data is sampled at the rising edge of the signal.

(c) "D>Do?" is rYEsJ'? ' If there are many errors, the clock phase control circuit (19
) outputs a switching control signal to the changeover switch (9), switches the changeover switch (9) to the delay circuit (84) side, delays the clock phase by one step, and performs sampling using the sampling clock ■.

(d) Compare the error count data D due to this clock ■ with the error count data D due to the immediately preceding clock ■, and as is clear from Figure 2 (a) and (b), the former is smaller. ``Has the error rate decreased?'' is rYEs.
J, the clock phase is further delayed by one step, and sampling is performed using the sampling clock ■.

(e) Compare the error occurrence data D due to this clock ■ and the error occurrence count data D due to the serial clock ■, and as is clear from Figure 2 (a) and (b), the former is larger. ``Has the error rate decreased?'' is ``NO''.
'', the clock phase is advanced by one step and sampling is performed using the sampling clock ■.

(F) Since the error occurrence number data D due to this clock ■ is smaller than the allowable error occurrence number data D0, "Are there many errors?"
” becomes rNOJ.

(g) In this way, the character signal is changed to the dotted line (P
), sampling using the sampling clock ■ is performed using the feedback control described above, and a noise margin (N ) becomes the largest, and the correct teletext data is extracted.

(h) Even if the shift is to the advancing side indicated by the chain line (Q), the above (
In the same manner as (a) to (c), in the initial state, sampling is performed using the extraction clock ■, and the r
D) D, huh? '' is rYEsJ, the clock phase is advanced by one step and sampling is performed using the sampling clock ■.Then, in the same way as in (d) to (g) above, the question ``Has the error rate become smaller?'' is determined. rYESJ, the clock phase is advanced by one step and sampling is performed using the sampling clock ■.In sampling using this clock ■,
Has the error rate decreased? '' becomes rNOJ, the clock phase is delayed by one step, and feedback control is performed in which sampling is performed using the sampling clock (3) with the largest noise margin (N), and correct teletext data is extracted.

(C) Next, slice level control will be explained using FIGS. 4 and 5. The received video signal is distorted due to noise, group delay, ghost, etc., and the character signal appearing on the output side of the character signal extraction circuit (11) is as shown in Fig. 4(a).
from the normal value shown by the solid line (R) to the dotted line (S) or the dashed line (
T), and as a result, the desired center level of the amplitude shifts from r 100J to r 10IJ on the higher side or rollJ on the lower side.

(a) In the case of a shift to the higher side shown by the dotted line (S), in the initial state, for example, the slice level counter (13) is set to rloOJ. Assuming that the peak-to-peak amplitude of the character signal is 0.7V for rlooJ.

It corresponds to 0.35V at its center.

(b) Next, the CPU (17) checks the error occurrence number data D output from the BEST (15) via the signal line (16), and determines whether rD>D? ”, and if it is “NO”, there are few errors, so sampling of the teletext data is performed at the slice level rlo()J. That is, the input data counter (1z) samples the character signal at the rising edge of the sampling clock shown in FIG. 4(b), and the comparator (14) converts this sampling data (3 bits) into slice level data rlo.
When compared with OJ, when the former is large, 111 I+ is output, and when the former is small, data of "0" is output.

(c) ro>oo? ” is rYEsJ, there are many errors, so the slice level control circuit (20)
A switching control signal is output from to the slice level counter (13), and the slice level is switched from rloOJ to rlolJ, which is one step higher, and the slice level is set to rloI.
Sampling by J.

(d) Compare the error occurrence number data D obtained by sampling this slice level r101J and the data D obtained by sampling the immediately preceding slice level rloOJ,
As is clear from FIGS. 4(a) and 4(b), since the former is smaller, "Has the error rate become smaller?" becomes rYEsJ, and the slice level is sampled at rllOJ, which is one step higher.

(E) Compare the data D based on this slice level rllOJ and the data D based on the immediately preceding level rloIJ, and as is clear from FIGS. 4(a) and (b), the former is larger, so the error rate is lower. "Has it changed?" becomes rNO, and the slice level is lowered by one level to the slice level r.
101 J sampling.

(to) Data D based on this slice level rloIJ is permissible data D. Since it is smaller, "Do you have many errors?" becomes rNOJ.

(G) In this way, the center level of the amplitude of the character signal is
If it shifts to the higher side as shown by the dotted line (S) in Figure (a), sampling is performed at the slice level rloIJ with the largest noise margin (N) by the feedback control described above, and correct teletext data is obtained. Extraction is performed.

(H) Even when the shift is to the lower side shown by the chain line (T), the above (
Similarly to (a) to (c), sampling is performed at slice level r100J in the initial state.

Is r D > D a at that time? ” is rYEsJ, the slice level is set to one step lower, rollJ, and sampling is performed.

(S) Next, in the same manner as in (d) to (g) above, "Has the error rate become smaller?" becomes rYEsJ, and the slice level is set to "010", which is one level lower, and sampling is performed at this level ro10J. Then, "Has the error rate become smaller?" is "NO", and the level is set to 1.
Feedback control is performed in which sampling is performed at the slice level ro11J with the largest noise margin (N), and correct teletext data is extracted.

In the embodiment described above, sampling is performed at the rising edge of the sampled clock, but the sampling can be similarly applied to the case where sampling is performed at the falling edge.

[Effects of the Invention] The extraction clock phase control device of the teletext data extraction circuit according to the present invention can prevent the phase of the character signal to be sampled from shifting to the lead side or the lag side from the normal value due to ghosting, group delay, etc. as described above. In this case, the phase of the sampled clock is switched to the leading side or the lagging side to perform feedback control in the direction of decreasing the detection output of the error detection circuit (in other words, in the direction of decreasing the error rate), so that the noise margin is at its maximum. Sampling is possible and the correct teletext data can be extracted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a sampling clock phase control device for a teletext data sampling circuit according to the present invention;
Figures 2 (a) and 2 (b) explain the phase control effect of the sampled clock; (a) is a waveform diagram of the character signal; (b)
) is a timing diagram of the sampling clock, and FIG. 3 is a flowchart explaining the phase control action of the sampling clock.
4(a) and 4(b) explain the slice level control action, (a) is a waveform diagram of the character signal, (b) is a timing diagram of the sampling clock, and FIG. 5 explains the slice level control action. This is a flowchart. (1)...Video signal input terminal, (6)...Sampling circuit, (7)...Sampling clock generation circuit, (10)...
...Clock phase switching circuit, (13)...Slice level counter (slice level switching circuit), (15)...
...BEST (error correction circuit) (also serves as error executive output circuit), (17)...CPU, (19)...clock phase control circuit, (20)...slice level control circuit,
(N)...Noise margin. Applicant: Fujitsu General XI Ltd. Figure 2 Figure 3 Figure 4 Cause 1 May

Claims (2)

[Claims] (1) In a sampling circuit that extracts teletext data from a received video signal by sampling using a sampling clock, the sampling circuit includes a clock phase switching circuit that switches the phase of the sampling clock into multiple stages, and a clock phase switching circuit that switches the phase of the sampling clock into multiple stages; The system includes an error rate detection circuit that detects an error rate of broadcast data, and a clock phase control circuit that switches and controls the clock phase switching circuit in a direction in which the error rate decreases based on the detection output of the error rate detection circuit. A teletext data sampling clock phase control device for a sampling circuit. (2) Sampling clock phase control of the teletext data sampling circuit according to claim 1, wherein the error rate detection circuit also serves as an error correction circuit for correcting errors in the teletext data obtained by the sampling circuit. Device.