JPH0832026B2 - Teletext data sampling control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to the teletext data of a teletext receiver that can always extract correct teletext data when the teletext data is distorted due to noise or the like. The present invention relates to a sampling control circuit.

[Prior Art] In the conventional teletext data sampling circuit, the phase of the sampling clock for sampling for sampling teletext data from the received video signal is fixed.

[Problems to be Solved by the Invention] Therefore, the waveform of the received video signal is distorted by ghost, group delay, noise, etc., and the phase of the character signal sampled by the sampling circuit is indicated by the solid line (O) in FIG. 2 (a). When the normal value indicated by is shifted as shown by the dotted line (P) or the chain line (Q), sampling with the sampling clock with the fixed phase shown in (b) of FIG. There was a problem that data could not be obtained.

The present invention, even if the phase shift of the character signal to be sampled due to ghost, group delay or noise,
An object of the present invention is to obtain a control device in which a teletext data sampling circuit can always extract correct teletext data.

[Means for Solving the Problems] The present invention relates to an AD conversion circuit (2) for AD converting a received video signal, and a waveform equalization circuit for shaping the waveform of the AD converted signal ( 5), a sampling clock generation circuit (7) for forming and outputting a sampling clock based on the received video signal, and the sampling clock generation circuit (7)
A clock phase switching circuit (10) for switching the phase of the sampling clock output from the device in a plurality of stages and outputting the sampling clock, and sampling of the sampling clock output from the clock phase switching circuit (10) for waveform equalization circuit (5). A sampling circuit (6) for sampling the teletext data from the output video signal, and detecting and outputting the error rate of the teletext data obtained by the sampling circuit (6) and correcting when there is a data error. Error correction circuit / error rate detection circuit (15) for outputting the teletext data, the waveform equalization circuit (5), the sampling circuit (6), and the clock phase switching circuit (10)
A digital filter circuit (3) to which the output signal of the A-D conversion circuit (2) is input, and a digital filter circuit (3), Correction signal output from circuit (3) and original AD
And a mixing circuit (4) for mixing the converted signal,
The clock phase switching circuit (10) includes at least five stages of delay circuits (8 ₁ ) (8 ₂ ) (8 ₃ ) (8 ₄ ) (8 ₅ ), and a changeover switch (9) for selecting one of these. The sampling circuit (6) samples the character signal sampling circuit (11) with the sampling signal output from the clock phase switching circuit (10) and outputs the sampled character signal as 3-bit data. Input data counter (12), a slice level counter (13) for switching the slice level to 3-bit data and outputting, output data of the input data counter (12) and output data of the slice level counter (13) And a comparator (14) that compares and outputs the error rate output from the error correction circuit / error rate detection circuit (15) to the digital filter circuit (3). Output from the filter constant control circuit (18) that feeds back and changes the filter constant of the digital filter circuit (3) so as to reduce the error rate, and the error correction circuit / error rate detection circuit (15). The slice level control circuit (20) that feeds back the error rate to the slice level counter (13) of the sampling circuit (6) and switches the level of this slice level counter (13) to control the error rate in a direction to reduce the error rate. And the error correction circuit and error rate detection circuit (15)
The error rate output from the clock phase switching circuit (10)
And a clock phase control circuit (19) for feeding back the changeover switch (9) to change over the changeover switch (9) and controlling the direction to reduce the error rate. Is.

[Operation] If the phase of the character signal to be sampled deviates from the normal value to the lead side or the lag side due to ghost, group delay, noise, etc., the error rate output from the error correction circuit / error rate detection circuit (15) changes. , The error rate from the filter constant control circuit (18), the clock phase control circuit (19) and the slice level control circuit (20), respectively, digital filter (3), changeover switch (9) and slice level counter (13). To control the variable of the filter constant, the switching of the phase of the sampling clock to the lead side or the lag side, and the slice level to reduce the error rate of the error correction circuit / error rate detection circuit (15). To do. Therefore, correct teletext data can be extracted.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which (1) is an input terminal of a video signal received by a teletext receiver and led from a video signal processing circuit. is there. This video signal input terminal (1) is connected to a sampling circuit (6) via a waveform equalization circuit (5) equipped with an AD conversion circuit (2), a digital filter circuit (3) and a mixing circuit (4). It is connected.

The digital filter circuit (3) changes the signal obtained based on the received video signal AD-converted by the AD converter circuit (2) in accordance with the generation time of a ghost or the like, and outputs a correction signal. The mixing circuit (4) is a circuit that mixes and corrects the corrected signal and the original received video signal, and is a conventionally known waveform equalization circuit.

To the video signal input terminal (1), the color burst (≈3.58MHz) in the video signal is multiplied by 8/5, and the PLL (Phase Lock)
A sampling clock generating circuit (7) that outputs a sampling clock of 5.73 MHz locked by using a loop is connected.

On the output side of this sampling clock generation circuit (7),
Delay time in 5 steps (For example, if the cycle of the 5.73 Hz sampling clock is T, the delay time is T / 10 (about 18 degrees in phase angle), 2T / 10, 3T / 10, 4T / 10, 5T / 5 stages of 10}
Delay circuit set to (8 ₁ ) (8 ₂ ) (8 ₃ ) (8 ₄ ) (8 ₅ )
When these delay circuits (8 ₁₎ (8 ₂₎ (8 ₃₎ (8 ₄₎ (8 ₅₎
A clock phase switching circuit (10) consisting of a switching switch (9) for switching and outputting one of the two is connected.

The extraction circuit (6) extracts a character signal extraction circuit (11) for extracting a character signal from the signal output from the waveform equalization circuit (5) and a character signal extracted from the character signal extraction circuit (11). An input data counter (12) for sampling with a sampling clock output from the clock phase switching circuit (10) and outputting the sampled value as 3-bit data, and a slice level for switching to eight stages (3-bit data) The output data of the slice level counter (13) as a slice level switching circuit for outputting and the input data counter (12) are compared with the output data of the slice level counter (13). The data consists of a comparator (14) that outputs "0" data when the latter is large.

An error correction circuit / error rate detection circuit (15) is connected to the output side of the comparator (14). The error correction circuit / error rate detection circuit (15) is the extraction circuit (6).
The presence or absence of an error in the teletext data input from is detected, if there is no error, it is determined that there is no error and correction is not performed.If there is an error, the error rate is detected and output, and the information bit is output. The corrected teletext data is sent to a program memory (not shown). When correcting the teletext data input from the sampling circuit (6), the error correction circuit / error rate detection circuit (15) corrects the error rate of information bits (for example, the number of error occurrences that is the number of error bits per packet). Since the data D) is detected, the detection data of this error rate is output from the signal line (16) and is also used for the filter constant control, the clock phase control and the slice level control.

(17) is a CPU (Central Processing Unit), and this CPU (17)
Includes a filter constant control circuit (18), a clock phase control circuit (19), and a slice level control circuit (20).

The filter constant control circuit (18) receives error rate data input from the error correction circuit / error rate detection circuit (15) through a signal line (16), that is, as described above, the error rate is, for example, 1 packet. If it is the number of error bits per hit, as a digital signal indicating how much the number of error bits deviates from the normal value in the positive or negative direction,
Digital filter circuit (3) of the waveform equalization circuit (5)
If the number of remaining bits is greater than the number of error bits before feedback is applied, the filter constant is changed in the opposite direction, and if the number of error bits is decreased, the filter constant is changed in the same direction, and the number of error occurrences is changed. The correction signal is controlled in the direction of reducing the data (that is, the method of reducing the error rate).

Similarly, the slice level control circuit (20) feeds back error rate data from the error correction circuit / error rate detection circuit (15) to the slice level counter (13), switches the slice level, and The number of occurrences data is controlled to be small (that is, the error rate is small). Further, the clock phase control circuit (1
9) feeds back error rate data from the error correction circuit / error rate detection circuit (15) to the clock phase switching circuit (10) and switches the changeover switch (9) to reduce the error occurrence number data. Control (that is, the direction in which the error rate decreases).

Next, the operation of the above embodiment will be described with reference to FIGS. 2 to 5.

(A) First, the filter constant control will be described.

The waveform of the received video signal is distorted due to ghost, group delay, noise, etc., and the waveform of the signal input to the waveform equalization circuit (5) is distorted, which causes the error correction circuit / error rate detection circuit (15) to pass through the signal line (16). When the error occurrence number data D as an error rate output via () exceeds the allowable error occurrence number data D ₀ , it is fed back from the filter constant control circuit (18) of the CPU (17) to the digital filter circuit (3). Based on the control signal, the filter constant of the digital filter circuit (3) is controlled so that D becomes D ₀ or less. For example, when the filter constant is changed and D is increased, the filter constant is changed in the opposite direction, or when D is decreased, the filter constant is changed in the same direction. That is, the digital filter circuit (3) outputs a correction signal based on the received video signal having distortion from the AD conversion circuit (2), and the correction signal and the distortion from the AD conversion circuit (2) are output. The mixing circuit (4) mixes (adds or subtracts) the received video signal to have the waveform of the character signal.

Here, D ₀ is an error correction circuit / error rate detection circuit (15)
The number of error-correctable bits (for example, 8 bits when up to 8 bits in one packet (296 bits) is 8 bits) and is set to allowable error occurrence number data.

(B) Next, the phase control of the sampling clock will be described with reference to FIGS. 2 and 3.

The waveform of the received video signal is distorted by ghost, group delay, noise, etc., and the character signal appearing at the output side of the character signal extracting circuit (11) of the extracting circuit (6) is indicated by the solid line (O) in FIG. 2 (a). It is assumed that the normal value is deviated to the delay side or the advance side as indicated by the dotted line (P) or the chain line (Q).

(A) When the line is shifted to the delay side indicated by the dotted line (P), in the initial state, for example, the changeover switch (9) of the clock phase changeover circuit (10) is connected to the output side of the delay circuit (8 ₃ ), The initial settings for the sampling clock are set.

(B) Next, the CPU (17) checks the error occurrence number data D as the error rate output from the error correction circuit / error rate detection circuit (15) via the signal line (16), and "D> D ₀ Do? "to determine, because the error if it is" NO "is a small sampling of the character broadcast data by the rising edge of the sampling clock is performed.

(C) If “D> D ₀ ?” Is “YES”, there are many errors, and therefore a changeover control signal is output from the clock phase control circuit (19) to the changeover switch (9) and the changeover switch (9 ) switching to the delay circuit (8 ₄₎ side, the sampling by sampling clock by delaying the clock phase 1 phase.

(D) The error occurrence count data D by this clock is compared with the error occurrence count data D as the error rate by the clock immediately before, and as is clear from FIGS. 2A and 2B, the former one Is small, "Is the error rate small?" Becomes "YES" and the clock phase is further delayed by one step to perform sampling with the sampling clock.

(E) The error occurrence number data D by this clock is compared with the error occurrence number data D as the error rate by the clock immediately before, and as is clear from FIGS. 2A and 2B, the former one "Is the error rate small?" Becomes "NO", and the clock phase is advanced by one step for sampling with the sampling clock.

(F) Since the error occurrence rate data D due to this clock is smaller than the allowable error occurrence number data D ₀ , "Is there many errors?"
Becomes "NO".

(G) When the character signal is thus deviated to the delay side indicated by the dotted line (P) in FIG. 2A, sampling is performed by the sampling clock by the feedback control as described above, and the sampling clock rises. The noise margin (N) corresponding to the interval between the value of the character signal and the slice level at the time is maximized, and the correct character broadcast data is extracted.

(H) Even when the line is shifted to the leading side indicated by the chain line (Q), sampling is performed by the sampling clock in the initial state in the same manner as in (a) to (c) above, and "D> D ₀ " at that time. If? Is "YES", set the clock phase to 1
Sampling is performed with a step-out sampling clock.

(Ri) Then, in the same manner as in (d) to (g) above, "whether the error rate has decreased?" Becomes "YES", the clock phase is advanced by one step, and sampling is performed by the sampling clock. In sampling, "whether the error rate has decreased?" Becomes "NO", the clock phase is delayed by one step, and feedback control is performed to perform sampling by the sampling clock with the largest noise margin (N), and correct sampling of teletext data is performed. Done.

(C) Next, the slice level control will be described with reference to FIGS. 4 and 5.

The received video signal is distorted by noise, group delay or ghost, and the character signal appearing on the output side of the character signal sampling circuit (11) changes from the normal value shown by the solid line (R) in FIG. 4 (a) to the dotted line (S). Alternatively, it is assumed that the center line of the desired amplitude is shifted from "100" to "101" on the high side or "011" on the low side, as shown by the chain line (T).

(A) When the line is shifted to the higher side shown by the dotted line (S), in the initial state, for example, the slice level counter (13) is set to "100". Assuming that the peak-to-peak amplitude of the character signal is 0.7V, this "100" is 0.35 at the center.
Equivalent to V.

(B) Next, the CPU (17) checks the error occurrence number data D as the error rate output from the error correction circuit / error rate detection circuit (15) via the signal line (16), and "D> D ₀ Do? "determines, since errors if" NO "is small, the sampling of the teletext data by slice level" 100 "is performed. That is, the input data counter (12)
Performs sampling of the character signal at the rising edge of the sampling clock shown in FIG. 4 (b), and the comparator (14)
Compares this sampling data (3 bits) with slice level data “100”, and outputs “1” when the former is large and outputs “0” when it is small.

(C) If “D> D ₀ ?” Is “YES”, there are many errors, and therefore the switching control signal is output from the slice level control circuit (20) to the slice level counter (13), and the slice One level higher from "100" to "10"
Switch to “1” and sample at slice level “101”.

(D) The error occurrence count data D as the error rate due to the sampling of the slice level "101" is compared with the data D due to the sampling of the slice level "100" immediately before that, and the results are shown in FIGS. As is clear from the above, since the former is smaller, "Is the error rate smaller?" Is "YES", and the slice level is one step higher.
It will be sampled as "10".

(E) The data D at the slice level “110” is compared with the data D at the immediately preceding level “101”, and as is clear from FIGS. 4A and 4B, the former is larger. Is the error rate small? "Becomes" NO, and the slice level is lowered by one level and the slice level is "101".
Sampling by.

(F) Since the data D based on this slice level “101” is smaller than the allowable data D ₀ , “Are there many errors?” Is “N”.
O ”.

(G) As described above, the central level of the amplitude of the character signal is the fourth level.
When it shifts to the higher side as shown by the dotted line (S) in FIG. (A), the feedback control as described above performs sampling at the slice level “101” with the largest noise margin (N) and correct teletext. Data is extracted.

(H) Even when the position is shifted to the lower side indicated by the chain line (T), sampling is performed at the slice level “100” in the initial state in the same manner as in (a) to (c) above, and “D> If "D ₀ ?" Is "YES", the slice level is set to "011", which is one step lower, and sampling is performed.

(I) Then, as in (d) to (g) above, "Is the error rate small?" Becomes "YES" and the slice level is lowered by one step to "010" and sampling is performed. In the sampling by "010", "Is the error rate small?" Becomes "NO", the level is raised to "011" which is one step higher, and feedback control is performed by sampling at the slice level "011" with the largest noise margin (N). The correct teletext data is extracted.

In the above-described embodiment, sampling is performed at the rising edge of the sampling clock, but the same can be applied to the case of sampling at the falling edge.

[Advantages of the Invention] (a) When the phase of the character signal to be sampled is shifted from the normal value to the lead side or the lag side due to ghost or group delay, the error rate data of the correction circuit / error rate detection circuit (15) is changed. By feeding back and sampling, the phase of the clock is switched to the lead side or the lag side and automatically controlled in the direction to reduce the error rate, sampling can be performed in the state with the largest noise margin, and correct teletext data can be extracted.

(B) clock phase switching circuit (10) comprises at least 5 stages of delay circuits (8 ₁₎ (8 ₂₎ (8 ₃₎ (8 ₄₎ (8 _5), selector switch for selecting one of these ( 9) and a sample clock with multiple phases is prepared in advance, so when adjusting the group delay of a character broadcast that is broadcast by multiple stations, the optimum phase clock is automatically obtained by changing the channel. The delay circuit is selected and the adjustment at the factory becomes unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a teletext data sampling control circuit according to the present invention, and FIGS. 2 (a) and 2 (b) are for explaining the phase control operation of a sampling clock.
4A is a waveform diagram of a character signal, FIG. 4B is a timing diagram of a sampling clock, FIG. 3 is a flow chart for explaining the phase control action of the sampling clock, and FIG. 4A.
(B) is for explaining the slice level control action,
(A) is a waveform diagram of a character signal, (b) is a timing diagram of a sampling clock, and FIG. 5 is a flow chart for explaining a slice level control operation. (1) ... video signal input terminal, (6) ... sampling circuit,
(7) ... sampling clock generation circuit, (10) ... clock phase switching circuit, (13) ... slice level counter (slice level switching circuit), (15) ... error correction circuit and error rate detection circuit, ( 17) …… CPU, (19) …… Clock phase control circuit, (20) …… Slice level control circuit,
(N) …… Noise margin.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H04N 7/035 (72) Inventor Yuji Minami 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Within Fujitsu General Limited (72) Inventor Kota Hashiguchi, 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa, within Fujitsu General Co., Ltd. (72) Inventor, Shoji Ikuta 1116 Suenaga, Takatsu-ku, Kawasaki, Kanagawa, within Fujitsu General (56) References JP-A-60-212093 (JP, A) JP-A-56-51176 (JP, A) JP-A-59-34780 (JP, A)

Claims (1)

[Claims] 1. An A / D conversion circuit (2) for A / D converting a received video signal, a waveform equalization circuit (5) for shaping the waveform of the A / D converted signal, and the received video signal. A sampling clock generation circuit (7) that forms and outputs a sampling clock based on the sampling clock generation circuit (7)
A clock phase switching circuit (10) for switching the phase of the sampling clock output from the device in a plurality of stages and outputting the sampling clock, and sampling of the sampling clock output from the clock phase switching circuit (10) for waveform equalization circuit (5). A sampling circuit (6) for sampling the teletext data from the output video signal, and detecting and outputting the error rate of the teletext data obtained by the sampling circuit (6) and correcting when there is a data error. Error correction circuit / error rate detection circuit (15) for outputting the teletext data, the waveform equalization circuit (5), the sampling circuit (6), and the clock phase switching circuit (10)
A digital filter circuit (3) to which the output signal of the A-D conversion circuit (2) is input, and a digital filter circuit (3), Correction signal output from circuit (3) and original AD
And a mixing circuit (4) for mixing the converted signal,
The clock phase switching circuit (10) includes at least five stages of delay circuits (8 ₁ ) (8 ₂ ) (8 ₃ ) (8 ₄ ) (8 ₅ ), and a changeover switch (9) for selecting one of these. The sampling circuit (6) samples the character signal sampling circuit (11) with the sampling signal output from the clock phase switching circuit (10) and outputs the sampled character signal as 3-bit data. Input data counter (12), a slice level counter (13) for switching the slice level to 3-bit data and outputting, output data of the input data counter (12) and output data of the slice level counter (13) And a comparator (14) that compares and outputs the error rate output from the error correction circuit / error rate detection circuit (15) to the digital filter circuit (3). Output from the filter constant control circuit (18) that feeds back and changes the filter constant of the digital filter circuit (3) so as to reduce the error rate, and the error correction circuit / error rate detection circuit (15). The slice level control circuit (20) that feeds back the error rate to the slice level counter (13) of the sampling circuit (6) and switches the level of this slice level counter (13) to control the error rate in a direction to reduce the error rate. And the error correction circuit and error rate detection circuit (15)
The error rate output from the clock phase switching circuit (10)
And a clock phase control circuit (19) for feeding back the changeover switch (9) to change over the changeover switch (9) and controlling the direction to reduce the error rate. .