JPS63214887A - Display device - Google Patents

Abstract

PURPOSE:To select picture information even in any address of longitudinal and lateral addresses by dividing picture element storage areas into two groups constituting addresses of one area laterally and the other longitudinally. CONSTITUTION:The picture element information storage areas storing picture element information of a picture memory 108 are divided into two groups, the one area addresses are constituted laterally and the other area addresses are constituted longitudinally. The one area address of the picture element information storage areas of the picture memory 108 are designated by a graphic display controller 101 to select the picture element information. The selected picture information is converted into a video signal and displayed on a CRT monitor 212.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display device, and particularly to a bitmap type display device.

[Conventional technology]

When partially changing screen memory data in a conventional device, the microcomputer (hereinafter referred to as CPU)

(1) Read data already written in memoryC
Import into PU.

(2) Shift the character pattern to be written.

(3) Mask and extract the non-rewritten portion of the original data in the memory, extract the written bits of the character pattern after the shift, and take the logical sum of the two.

(4) The processing step was to write the completed data to the memory at the same address.

Furthermore, the bit processing of the CPU is slow, especially in the case of shifts, where a multiple-bit shift command repeats a single-bit shift command step multiple times. A method has also been proposed that uses a shift register and a counter to perform bit-by-bit rewriting using an external circuit, but in this method, even when the CPU finishes the write operation, the shift register ends its operation, and the actual Since it takes time for data to be written into the memory, continuous writing cannot be instructed, and although it is suitable for writing one bit, it is not suitable for writing a large amount of data.

That is, in the conventional device, for example, the address structure of the screen memory was as shown in FIG.

In this case, for example, when handling a 24x24 bit character pattern, the depth is 3 bytes in the raster scan direction and 24 bytes in the rask order direction. The CPU is usually provided with string instructions for repetitive processing of sequential addresses.

That is, the transfer of a specified number of bytes from a source address specified in a predetermined register to a destination address is performed with the minimum number of instruction steps and the shortest processing time.

Therefore, in order to obtain the maximum effect with this processing method, 1
It is effective to increase the number of bytes transferred each time. Therefore, focusing on this point, as shown in FIG. 7, the address structure of the screen memory is arranged in the forward raster direction.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the address structure of the memory was arranged horizontally or vertically.
It was not possible to arbitrarily select the address configuration of the double-sided memory, and this was not sufficient to increase the speed of the CPU.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that can select pixel information regardless of whether an address configuration of horizontal addresses or vertical addresses is specified.

[Means for solving problems]

To achieve the above object, the present invention provides a method in which a pixel information storage area for storing pixel information is divided into two groups, addresses of one area are arranged horizontally, and addresses of the other area are arranged vertically. the pixel information selected by the pixel information selection means is converted into a video signal and displayed on the screen. This is a display device having display means for displaying an image.

[Effect]

When selecting pixel information from the memory means, pixel information is selected by specifying horizontal or vertical addresses. An image is then displayed on the screen based on the selected pixel information.

〔Example〕

Hereinafter, an example in which the present invention is applied to a word processor will be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the configuration of a word processor. 201 is a CPU that controls the entire device.

A boot RO 202 consists of a non-volatile memory (hereinafter referred to as ROM) and has a program executed when the power is turned on.
M, 203 provides an interrupt signal to the CPU 201;
An interrupt controller 204 controls the keyboard 205 according to commands from the CPU 201 and sends input signals from the keyboard 205 to the CPU 201. A key controller 206 outputs signals for controlling the printer 207 and print signals according to commands from the CPU 201. 208 is a flexible disk controller (FDC) that controls the FDD 209 according to commands from the CPU 201, and 210 stores programs and information. Read-writable memory (for
(hereinafter referred to as RAM), 211 is a C
This is a CRT display device that sends a video signal to the RT monitor 212.

Next, the overall operation i of the word processor will be explained. That is, with the above configuration, when the power is turned on, the device loads the FD according to the program in the boot ROM 202.
A program for operating as a word processor stored in the flexible disk of the D209 is transferred to the main memory 210, and then the program is transferred to the main memory 210.
When performing zero document input processing to start operation as a word processor according to the program migrated to version 10, the input processing program in the main memory 210 is performed. In other words, by sending commands and data to the CRT controller 211 using an input processing program, the CRT controller 211 creates a screen pattern, converts it into a video signal, sends it to the CRT monitor 212, and displays the screen on the screen of the CRT monitor 212. form. Processing instructions associated with data input are performed in accordance with data and function instructions input from the keyboard 205. From then on.

This operation is repeated until there is an instruction to end data input.

When data entry is finished, the finish instruction is on the keyboard 205.
When an input is made, the CPU 201 detects this, executes termination processing, and prepares for the next processing.

FIG. 1 shows a block diagram of a display device according to the present invention. 101 is a graphic display controller (hereinafter referred to as GDC) that generates an address signal for sequentially reading the contents of the screen memory 108 and a synchronization signal to control the CRT monitor 212; 103 is a write signal from C1'U 201 to the screen memory 108; 102 is a control signal generation circuit that generates timing signals for circuits around the screen memory; 108 is a control signal generation circuit that generates timing signals for each image bit on the screen as a bit map; The existing screen memory is composed of dynamic RAM. 109 is a shift register that converts the data read from the screen memory 108 from parallel to serial; 110 is a synchronization circuit that synchronizes the horizontal and vertical synchronization signals from GDClol with the video signal from the shift register 109; , 212 is a CRT monitor that receives a video signal and a synchronization signal and displays a screen.

Numeral 104 is a multiplexer for selecting data, 111 is a multiplexer for selecting an address of the screen memory, and 107 is a multiplexer for selecting a refresh address, each of which selects and outputs a set of signals from input signal lines. 105 is a buffer for the output of the screen memory 108, and 106 is an address conversion circuit for converting the expanded address area into the memory area of the screen memory 108. For example, a method of performing address conversion using a ROM can be considered.

Next, referring to FIG. 3, the operation mode of the screen memory 108 will be described.

When the CPU 201 writes, it operates by read-modify-write. That is, data from the CPU 201 is temporarily stored in the data latch 301,
It is processed by the barrel shifter 302 and input to the light controller 303.

The contents of the designated address in the screen memory 108 are read out and applied to the other input terminal of the write controller 303. The above two inputs are logically operated bit by bit according to instructions stored in the operation register 305 and written to a specified address in the one-screen memory 108.

Next, the address structure of the one-screen memory 108 will be explained in detail using a diagram. A video signal is composed of a series of video bits in rask units. That is,
Reading from GDCIOI for refreshing the screen is in 16-bit units from the beginning of the screen, which is serially converted from the LSB, and after the MSB, the next 16-bit L is read.
SB is connected.

This allows the CPU to access the screen memory 108 by making it possible to arbitrarily select the arrangement of the address configurations described above.
By expanding the address area of the screen memory 108 viewed from above, two address configurations are provided, and the arrangement of the address configurations can be arbitrarily selected by selecting the address area of the CPU. FIG. 4 shows the address structure.

In this case, the address area of the one-screen memory 108 is 64 bytes from address 0 to address 65535, and an additional 6 bytes.
Addresses 13107131071 are expanded from address 5536, and screen memory 108 can be accessed from either side. The address structure seen from the CPU is 0.
The address area from address 65535 is aligned horizontally in the same direction as the rask scan direction, and from address 65536 to 1310
The address areas at locations 719 and 719 are arranged vertically in the same way as the rask forward direction. As a result, if you want to draw a horizontal line on the screen memory 108, you can issue a string command from address O to address 127, for example, and if you want to draw a vertical line, you can issue a string command from address 65536 to address 66047, for example. That's fine. Of course, the address configuration in this case.

Although addresses 0 to 65535 are arranged horizontally and addresses 65536 to 131071 are arranged vertically, the opposite may be used.

The relationship between the CPU memory map 701 and the screen memory 108 is shown in FIG. 5. In this case, the CPU address 10000
H (H indicates a hexadecimal number, the same applies hereinafter) to IFFF
The FH address area 702 has a horizontal address structure, and the CPU address 20000!1 to 2FFFFH
Assuming that the address area 703 is arranged vertically,
The configuration is such that when the address area 703 is accessed, the screen memory 108 is accessed via the address conversion circuit 106. Further, a method of performing address conversion using a ROM may also be considered. Of course, the order of the address structure in this case may be reversed.

In addition, when the screen memory is divided into two parts and one is used as the screen memory area and the other as the data area, it is possible to access the address areas arranged horizontally in the raster scan direction as the data area. The data area can be used as a continuous address, and there is no need to provide separate memory peripheral circuits for the screen memory area and the data memory area, so the circuit configuration can be simplified.

Next, the operation of this circuit will be explained with reference to FIG.

(+) Processing from the CPU 201 (screen creation). The display information is displayed by writing 3 "1" (bright dot) or "o" (n+1 point) to the screen memory 108 in bit units. The display of 0 characters displays the character pattern specified by the character generator. Characters will be displayed on both sides by writing to a byte address of 108 in the screen memory using a string instruction. By the way, a half-width character has a width of 1.5 bytes, so if even one half-width character is included in a sentence, the bit position of the character pattern will shift by 4 bits in the screen memory 108, causing a situation where it will not match. .

At this time, in a configuration without a screen memory control circuit, bit processing had to be performed every time one byte was transferred in the process of transferring a character pattern from the character generator to the screen memory 108. That is, 8086,80
88 For the CPU, memory movement using string instructions could not be used.6 In the present invention, by providing the one-screen memory control circuit 103, it is possible to perform bit shift processing, mask processing, etc. in place of the CPU 201. By using the string command, high-speed writing to the screen memory 108 can be realized.

(2) Processing (data processing) from the CPU 201 When drawing a vertical edge in the screen memory 108, write data from the CPU 201 is written to the screen memory 108 via multiplexers 104 and 105. The CPU addresses at this time are address areas arranged vertically in the raster forward direction. The control signal generation circuit 102 cuts the CPU address in half and sends the address conversion circuit 1 to the multiplexer 111.
A signal is given to select the address converted in 06 or the through address. Multiplexer 107 selects an address in the raster forward direction and provides the address to screen memory 108.

Furthermore, when using part of the screen memory 108 as a data storage area, write data from the CPU 201 is sent to the screen memory 108 via multiplexers 104 and 105.
written to. The CPU addresses at this time are horizontal address areas in the raster scan direction. The control signal generation circuit 102 cuts the CPU address in half and gives a signal to the multiplexer 111 to select either the address converted by the address conversion circuit 106 or the through address. Multiplexer 107 selects an address in the raster scan direction and provides the address to screen memory 108.

According to this method, addresses can be used continuously and memory can be used effectively as a data area.

(3) Refresh operation (II screen display).

Depending on the synchronization timing of the CRT monitor 212, the GDC
IOI generates a read signal to screen memory 108. GDClol generates addresses in the order of screen positions and applies read signals to the screen memory 108 through the control signal generation circuit 102. The data read from the screen memory 108 at the time given for CRT reading is added to the shift register 109, then converted from parallel to serial by the video clock and given to the CRT monitor 212 as a video signal.

〔Effect of the invention〕

As described above, according to the present invention, pixel information can be selected by specifying any address in horizontal or vertical arrangement, so that the display speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of the device according to the present invention, FIG. 2 is an overall configuration diagram of the device according to the present invention, FIG. 3 is a specific configuration diagram of the screen memory control circuit, and FIG. FIG. 5 is a diagram for explaining the address configuration of the screen memory according to the present invention, FIG. 6 is an address configuration diagram of a conventional screen memory, and FIG. 7 is a diagram of another conventional screen memory. FIG. 3 is an address configuration diagram of a memory. 101...Graphic diskless controller. 102... Control signal generation circuit, 103... Screen memory control circuit, 106... Address conversion circuit, 108.
...Screen memory...201...CPU, 211...
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Claims (1)

[Claims] 1. A memory means in which a pixel information storage area for storing pixel information is divided into two groups, addresses of one area are arranged horizontally, and addresses of the other area are arranged vertically;
pixel information selection means for selecting pixel information by specifying the address of one of the pixel information storage areas of the memory means; and converting the pixel information selected by the pixel information selection means into a video signal and displaying the image on the screen. A display device comprising: display means for displaying.