JPS63211977A - Cyclic type noise reducing device - Google Patents

Abstract

PURPOSE:To simplify a device constitution by constituting a parallel/serial conversion circuit used for parallel/serial conversion in such a way that a part of picture element data among parallel picture element data obtained from Hadamard inverse transform is substituted for other picture element data. CONSTITUTION:An Hadamard inverse transform circuit 22 and the parallel/serial conversion circuit 23 are provided. For the circuit 22, a circuit outputting only x'13 being one component among picture element data x'00-x'13 which are originally obtained eight is used, and adders and subtractors requiring 24 devices in total so far can be simplified to only seven subtractors 22b. Picture data x'13 is supplied to the circuit 23 as represent of other picture element data x'00-x'<13>, whereby only the output of data x'13 instead of them may be enough in a period when original data x'00-x'13 are outputted, and the constitution is simplified compared to a conventional parallel-serial conversion circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a cyclic noise low frequency band that simplifies a Hadamard inverse transform circuit and a subsequent parallel/serial transform circuit [Prior art] Video with high frame correlation. Due to its principle, a cyclic noise reduction device that reduces noise by cyclically adding signals tends to generate afterimages in rapidly moving images. For this reason,
For example, by applying Hadamard transform to the frame difference signal,
A cyclic noise reduction device has been proposed that reduces noise by considering the statistical properties of a video signal and the visual characteristics of the eye.

The cyclic noise reduction device I shown in FIG. 3 combines two-dimensional Hadamard transform with noise reduction processing using frame correlation, and includes two subtracters 2° to which input video signals are applied as addition power. A frame memory 4 is provided between the frame memory 4 and the delayed output video signal obtained from the frame memory 4. After the color signal phase shift circuit 5 inverts the phase of the color signal, a subtracter 3 subtracts the delayed output video signal from the input video signal. do. The frame difference signal obtained by the subtraction in the subtracter 3 focuses on a small area consisting of pixels divided into two-dimensional low frequency components, vertical components, diagonal components, or components that well represent the characteristics of the signal. The eight pixel data obtained as serial data are first converted into parallel data by a serial/parallel conversion circuit 6.

The eight pixel data subjected to serial/parallel conversion are subjected to orthogonal transformation, which will be described later, in the Hadamard transform circuit 7 and decomposed into the characteristic components. Furthermore, the pixel data from which only noise components are extracted by being subjected to nonlinear transformation processing according to saturation characteristics or decay characteristics in a nonlinear circuit 8 is converted into an array before transformation by a Hadamard inverse transformation circuit 9. After being restored to
Parallel data is converted into serial data by a serial conversion circuit IO. Then, the pixel data ordered on the time axis is passed through a coefficient circuit 11 for gain adjustment to be subtracted by a subtracter 2, and is again subjected to a delay of one frame period by a frame memory 4.

In the case of this example, the following 4x2 two-dimensional Hadamard transform is adopted from among orthogonal transforms suitable for digital configuration. That is, the conversion output vector is Fl,
4. When the input pixel vector is expressed as x2.4, using the transformation matrices H and H, P 2,4= II *
X t, all aHowever, .

In the Hadamard inverse transform, which is a pair of the Hadamard transform described above, the noise component extracted from the input pixel vector is
t+a, the conversion output vector that has passed through the nonlinear circuit 8 is F
'2+4, also transformation matrix 11. .

■The inverse transformation matrix obtained as the transposed matrix of o
, t , If , T, the following conversion is performed.

X't+4=1/8 ・Ht"F't, 4H*
THowever, it is.

By the way, the conventional cyclic noise reduction device 1 processes the Hadamard transform and the inverse Hadamard transform using a real-time parallel processing circuit shown in FIG.

The serial/parallel conversion circuit 6 shown in the figure consists of a line delay element 6a having a delay time of l horizontal scanning period and 12 dot delay elements 6b having a delay time of one pixel scanning period. Then, the eight pixel data X are converted into parallel data by this direct/phi/parallel conversion circuit 6. g'=X13 is the adder 7a provided in each Hadamard transform circuit 7 with 12 pieces
and is subjected to matrix calculation by the subtractor 7b, and the following 8 is obtained.
piece of data F. . ~F13. In addition, Hadamard's change, −−−mu−+ ・J+ 1 ^
Body u-A? rnlc l b-11r+bamboo Q
! ! '7 - 1+^λ calculators 7b are arranged in a matrix in three stages: front stage, middle stage, and rear stage, with four in each stage. It is input from someone.

F oo"X oo+X oI4X ot+X l13
”X lo+X eye+X It”X +3P Io”X
oo"X o++X ot"X 03-X 10-X
Eye-X +t-X 13F oI"X oo-X o
I"X at-X 03"X 10-X th"X +t
-X +3P ++"X oo-X oI"X at-
X os-X +o+X z-X It”X 13P
ot:X oo”X oI-X at-X os”X
+o+X z-X +t-X 13Fll°X oo+
X oI-X ox-X as-X Io-X z
+X It"X 13Fl13"Xall-XIl
l-XallXo3"XIo-X+self-X+t"X+3
P Io"X oo-X a+-X ot+X
a3-X +o+X z"X +t-X
+s Thus, eight components F that well represent the characteristics of the video signal
. . The frame difference signals classified into ~F13 are each nonlinearly processed by passing through eight nonlinear elements 8a provided in the nonlinear circuit 8, and converted output vector F'
! , 4. . ~F13 is extracted. Like the Hadamard transform circuit 7, the Hadamard inverse transform circuit 9 includes adders 7λ and subtracters 7, each having 12 adders 7λ and 12 subtracters 7.
b is configured by arranging 4 pixels in a matrix in 3 stages of front car width D - straddle, and 8 pixel data X° mainly composed of noise components shown below. . ~x°1. get.

x'. o"F'oo+F'614F' o2+F
'os"F'1o+F'+1+F'+
t+F"13x'+o"F'oo+F' ot+
F'ol+F'as-F'Ha-F' + 1-
F' 1 g-F'13x'ot"F' oo-F
'ot+F'ol-F"@3"F"10-F'
I t+F't*-F'+sx' + l"F'
60-F'OI+F'ot-F'as-F'
+o"F' + t-F' + 10F'+sx'
at:F'oo+F' o t-F'as-F'
os"F'+o+F' + +-F' + t-F'
+3x' + t"F'00+F'01-F'
at-F'os-F"+o-F' r t+F'
+t+F'+sx'oa"F'oo-F' a
t-F'ot"F'os+F'to-F', -F
” + *+F' + sx'rs=F' no
F'o+-F'ot+F'as-F'+o+F'
l ++F'+t-F' ls [Problem to be solved by the invention] The above-mentioned conventional cyclic noise reduction device! Since the Hadamard transform is executed by a real-time parallel processing circuit, each pixel data of 8 human pixel vectors x8.4
After serial/parallel conversion, the noise vector X'2 extracted from the input pixel vector x2.4 obtained from the Hadamard inverse transform circuit 9 is
．． The configuration is such that each component X'on to X' of a is all converted into serial data by a parallel/serial conversion circuit IO. However, the noise vector X'! +4 each component
'oo-X'+ko is evenly distributed among the 8 pixels, so any component X°. . ~x°1. It is safe to assume that they are almost the same from a macro perspective.

In other words, regarding the noise vector
8 pixel data X° in the serial conversion circuit 10. . ~X'
1M are all subjected to parallel/serial conversion, which not only complicates the configuration of the parallel/serial conversion circuit IO itself, but also poses problems such as the inability to simplify the Hadamard inverse conversion circuit 9 at the previous stage.

[Means for Solving the Problems] The present invention solves the above problems, and processes a certain number of pixel data in series or parallel from the difference between the input video signal and the delayed output video signal delayed by one frame period. This is a cyclic noise reduction device that performs Hadamard transformation, performs nonlinear transformation processing to focus on extracting noise components, performs inverse Hadamard transformation, performs parallel/serial transformation, and then delays the signal by one frame period. The parallel-to-serial conversion circuit used for the parallel-to-serial conversion is characterized in that it uses some pixel data as a substitute for other pixel data among the parallel pixel data obtained by Hadamard inverse transformation. It is something.

[Operation] This invention performs serial/parallel conversion on a certain number of pixel data from a difference signal between an input video signal and a delayed output video signal delayed by one frame period, performs Hadamard transformation, and then performs Hadamard transformation through nonlinear transformation processing. When the pixel data is inversely transformed, finally parallel-to-serial transformed, and then delayed for l frame periods again, instead of supplying all the pixel data obtained in parallel by the Hadamard inverse transform to the parallel-to-serial converter, it is By substituting pixel data for other pixel data, the circuit structure of the parallel-to-serial conversion circuit and the Hadamard inverse conversion circuit at the preceding stage is simplified.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1.2. FIG. 1.2 is a circuit configuration diagram and a circuit diagram of essential parts, respectively, showing an embodiment of the cyclic noise reduction device of the present invention.

In FIG. 1, the cyclic noise reduction device 2I includes a Hadamard inverse transform circuit 22 and a parallel-to-serial converter circuit in place of the previously used Hadamard inverse transform circuit 7 and the parallel-to-serial converter circuit 10 connected thereto. 23 is provided. In this embodiment, the Hadamard inverse transform circuit 22 originally obtains eight pixel data X°. . ~x°1. As shown in Fig. 2, an adder 9 that outputs only the negative component xol is used, which conventionally required 24 adders in total.
a and the subtractor 9b can be simplified to only seven subtractors 22b. Further, the parallel/serial conversion circuit 23 converts only the single pixel data x°13 into other pixel data X°. .

As a result of being supplied as a representative of ~x'+t, originally other pixel data X°. . ~x゛1. It is only necessary to output pixel data x°13 instead of this during the period when is output, and its configuration is a conventional parallel/serial conversion circuit! 0 is incomparably simplified.

By the way, single pixel data x°, 3 is used as other pixel data X゛. . ~x°1. Although the method of substituting 8 pixels is used to represent 8 pixels with 1 pixel, there is still room for error, although this method extracts noise components. However, these 8 pixels fit into a small area of 5 mm square on a 20-inch monitor screen, for example, and this small area can be further divided into 1
It goes without saying that even if data sampled from the /8 portion is used as representative data, there will be no significant adverse effect.

Furthermore, this slight influence can be overcome by the fact that it is possible to use the Hadamard inverse transform circuit 22, which omits a total of 17 adders 7a and subtracters 7b from the conventional Hadamard inverse transform circuit 9, and that it is easy to handle by a single person. Parallel/serial conversion circuit 2
It is no exaggeration to say that this is more than offset by the merits of the circuit configuration, such as the ability to use 3.

In this way, the cyclic noise reduction device 21 performs serial/parallel conversion on eight pixel data x0° to The pixel data X . 0~x'1. Instead of supplying all the pixel data X'+3 to the parallel/serial conversion circuit 23, the single pixel data X'+3 is supplied to the other pixel data X°. . ~x°1. Since the Hadamard inverse transform circuit 22 is configured to be used as a substitute for the Hadamard inverse transform circuit 22, it is only necessary to obtain pixel data Compared to Hadamard inverse transform circuit 2, which has a much simpler configuration.
2 may be prepared, and the configuration of the parallel/serial conversion circuit 23 can also be simplified accordingly.

Note that in the above embodiment, the Hadamard inverse transform circuit 22
Two or more pieces of pixel data may be selectively output.

"Effects of the Invention" As explained above, the present invention has the advantage that input video signals and! From the difference signal of the delayed output video signal delayed by a frame period,
After serial/parallel conversion of a certain number of pixel data, Hadamard transform is performed, then non-linear conversion processing is performed, Hadamard inverse transform is performed, and finally parallel/serial transform is performed, and when the data is subjected to l-frame period delay again, Hadamard inverse transform is applied. Rather than supplying all of the pixel data obtained in parallel to the parallel/serial conversion circuit, some pixel data is substituted for other pixel data.・It is only necessary to obtain the pixel data required by the serial conversion circuit. Therefore, compared to the conventional Hadamard inverse conversion circuit, it is sufficient to prepare a Hadamard inverse conversion circuit, which has a much simpler configuration. In extreme cases, a single By using pixel data in place of the remaining pixel data, the circuit structure can be simplified, and the configuration of the parallel/serial conversion circuit can also be simplified. play.

[Brief explanation of the drawing]

Fig. 1.2 is a circuit configuration diagram and a circuit diagram of main parts showing one embodiment of the cyclic noise reduction device of the present invention, and Fig. 3.
FIG. 4 is a circuit configuration diagram and a circuit diagram of essential parts, respectively, showing an example of a conventional cyclic noise reduction device. 2.3゜0. Subtractor, 4. ,,frame memory. 600. Serial/parallel conversion circuit, 7. ,,Hadamard transform circuit,8. ,,Nonlinear circuit, 2+,,,Cyclic noise reduction device,22. ,, Hadamard inverse transform circuit, 23. ,,common·
Series conversion circuit.

Claims (1)

[Claims] From the difference between the input video signal and the delayed output video signal delayed by one frame period, a certain number of pixel data are serially and parallelly converted, then Hadamard transform is performed, and noise components are intensively extracted by performing non-linear transformation processing. This is a cyclic noise reduction device that performs inverse Hadamard transform, then performs parallel/serial conversion, and then delays the process by one frame period again. A cyclic noise reduction device configured to use some pixel data as a substitute for other pixel data.