JPS63211495A - Inline system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an in-line system in which two file units and a plurality of terminals are connected in-line.

[Conventional technology] Conventionally, in an inline system in which two file units and multiple terminals are connected inline,
One side of the file unit is connected to the line, and the other is disconnected from the line for backup purposes.If one file unit goes down, a buzzer or display will notify you, and one file unit can be disconnected from the line by manual switching. The other file unit was connected to the line for backup.

In addition, two file units were always powered on, and when one went down, the system automatically switched to the other.

[Problems to be Solved by the Invention] If one file unit is notified when it goes down and manually switches to the other file unit, there is a delay in switching, which takes time to recover from the downtime, resulting in a large loss to the system. There was a problem. Furthermore, even if automatic switching is possible, if two file units are constantly powered on, power consumption is large, and unused file units are always energized, resulting in shortened service life.

This invention was made to solve these problems, and when one file unit goes down, it can be quickly switched to the other file unit, and power is supplied to the file unit only when it is in use. The present invention aims to provide an in-line system that can reduce power consumption and prevent shortening of life by starting up the system.

[Means for Solving the Problems] This invention consists of a plurality of terminals that register and process product sales data and issue receipts, and a file unit that files the data processed by each terminal, which are connected inline. In an inline system, two file units are connected inline, and each file unit has a power supply start-up means that starts up the IIL in response to a power control signal from each terminal, and a power supply start-up means that starts up the IIL in response to a power control signal from each terminal, and a power supply start-up means that starts up the and a means for disconnecting the 'M source from the line, and a transmission control means for detecting the rise of the power by the power supply start-up means, connecting itself to the line, and controlling data transmission with each terminal. The system is provided with means for detecting that one file unit is down, and means for transmitting a power control signal to the other file unit when the means detects that a file is down.

[Operation] In the present invention having such a configuration, when a power control signal is transmitted from one of the terminals to one file unit, that file unit turns on and maintains its own power supply. Data transmission control is then performed between one file unit and each terminal. At this time, the other file unit remains powered off. If one file unit goes down in this state, that file unit disconnects itself from the line and turns off the power. The terminal detects this and sends a power control signal to the other file unit. The other file unit then turns on and maintains the power, connects itself to the line, and controls data transmission with the terminal.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 and 2 are file units, 31.
32.33, -3n are terminals.

- Each of the file units 1.2 and each terminal 31~
3n are connected in-line by transmission line 4. Further, transmission lines 5t and 52 for power control signal RPCC are connected from each of the terminals 31 to 3rL to each file unit 1.2, respectively.

As shown in FIG.
A ROM 12 in which program data etc. for controlling various parts of the CPU are stored, a RAM 13 in which a memory for storing data processed by the CPU II and a counter constituting a timer, etc. Along with the product code, RA has an area where unit price, product name, department code, etc. are set corresponding to this product code, and an area where cumulative sales items and sales amount are set.
An M file 14, a power supply control circuit 15 to be described later, a transmission controller 16 for controlling data transmission to each of the terminals 31 to 3n, and an I10 boat 17 are provided.

A lamp 18 and a buzzer 19 are connected to the I10 port 17.

The CPU 11, the 80M 12, the RAM 13, and the RAM file 14 are connected via an address bus line 20°, a data bus line 21, and a control line 22. Further, the CPU 11, the transmission controller 16, and the I10 boat 17 are connected via the data bus line 21 and control line 22.

The transmission controller 16 houses a relay for connecting and disconnecting the line, and the relay is controlled by the CPU 11 to control the controller 16 to connect and disconnect from the transmission line 4 . Note that when disconnecting the line, the transmission lines 4 connected to the input terminals are short-circuited.

As shown in FIG. 3, each of the terminals 31 to 3n includes a CPU 31 constituting the main body of the control section, a ROM 32 that stores program data for the CPU 31 to control each section, and a ROM 32 that stores data processed by the CPU 31. RAM 33, which is equipped with a memory for storing data, a counter for configuring a timer, and a registration memory for cumulatively registering data divided by department or transaction, etc.; a transmission controller 34 for controlling data transmission with each file unit 1.2;
A printer/drawer controller 35, a display controller 36, and a keyboard controller 37 are provided.

The printer/drawer controller 35 is connected to a printer 38 for issuing receipts and printing a journal, and a drawer opening section 39 .
6 is connected to a display 40 that displays codes and amounts, as well as lamps to indicate business status, and a keyboard controller 37 is connected to a keyboard 41 for inputting product codes and the like.

The CPtJ 31, ROM 32, and RAM 33 are connected via an address bus line 42, a data bus line 43, and a control line 44. Also, the CP
U31 and each controller 34, 35, 36, 37 are connected via the data bus line 43 and control line 44.

The transmission controller 34 houses a line connection/disconnection relay, and the CPU 31 controls the relay to control the transmission controller 34 to connect/disconnect the transmission line 4 . Note that when disconnecting the line, the transmission lines 4 connected to the input terminals are short-circuited.

As shown in FIG. 4, the power supply control circuit 15 of each file unit 1.2 connects a power supply unit 52 to a commercial AC power supply 50 via a main switch 51. This power supply unit 52 outputs a RESET signal at startup, and also outputs +5■ voltage. The +5V voltage output terminal is also connected to a terminal of a battery, which will be described later, via a diode 53 and a resistor 54.

Further, the primary winding of a transformer 56 is connected to the AC power source 50 via a sub switch 55. The input terminal of a full-wave rectifier circuit 57 is connected to the secondary winding of this transformer 56.
A smoothing capacitor 5 is connected to the output terminal of the full-wave rectifier circuit 57.
8 are connected.

The input terminal of a regulator 59 is connected to this smoothing capacitor 58, and the output terminal of the regulator 59 has a
A coil 64 of a relay 63 is connected through a parallel circuit of NPN transistors 60°61.62. Note that the coil 64 is equipped with a diode 65 for surge absorption.
are connected in parallel.

A normally open contact 66 of the relay 63 is connected in parallel to the main switch 51.

Further, a light emitting diode 68 is connected to the output terminal of the regulator 59 via a resistor 67. A main switch 69 is connected in parallel to this light emitting diode 68. The main switches 51, 69 are turned on and off in conjunction with each other.

Further, the output terminal of the regulator 59 is connected to a resistor 70 and a resistor 7.
1 and a series circuit with resistors 72 and 73 are connected, respectively, and the connection point between resistors 70 and 71 is connected to one input terminal of a first comparator 74, and the resistor 7
The connection point between 2 and 73 is connected to one input terminal of a second comparator 75. Furthermore, the regulator 59
The + side of the output terminal of is connected to the other input terminal of the first comparator 74 via a resistor 76. The other input terminal of this comparator 74 is also connected to the transmission line 51 (52) via a resistor 77.

The other input terminal of the second comparator 75 is connected to the resistor 7.
It is connected to the ten terminal of the battery 79 via the terminal 8. This battery 79 is for power backup and backs up the RAM 13 and RAM file 14 when the power is stopped.

The output terminal of the first comparator 74 is connected to the base of the transistor 60 via a resistor 80 and also to a three-state buffer 81. The output terminal of this buffer 81 is connected to the data bus line 21.

The output terminal of the second comparator 75 is connected to the base of the transistor 61 via a resistor 82 and to the D input terminal of a D-type flip-flop 83. The T input terminal of this flip-flop 83 is connected to the RE
A SET signal is input. The Q output terminal of this flip-flop 83 is connected to a three-state buffer 84. The output terminal of this buffer 84 is connected to the data bus line 21. Each of the three-state buffers 81 and 84 is driven and controlled by the CPU 11.

The data bus line 43 is connected to a D-type flip-flop 85.
is connected to the D input terminal of the This flip flop 8
The output terminal of a gate circuit 86 is connected to the T input terminal of No. 5, and the σ/no signal and the IOw signal are inputted to the gate circuit 86 from the CPU II. In addition, the R (reset) input terminal of the flip 70 knob 85 is connected to the RES.
The ET signal is input.

The Q output terminal of this flip-flop 85 is connected to the base of the transistor 62 via a resistor 87.

Figures 6 and 7 show CPU1 of file unit 1.2.
FIG. 6 shows power-on processing, and FIG. 7 shows processing when a transmission error occurs.

That is, as shown in FIG.
1 and check whether the output is "1". If it is “1”, D of flip-flop 85
Input "1" to the input terminal. The program processing then shifts to the main program, where data transmission, etc. with each terminal 31 to 3n is performed. If it is "0", then the three-state buffer 84 is driven and it is checked whether its output is "1". If it is "1", "1" is input to the D input terminal of the flip-flop 85, and the RA
Set the time on the charging timer provided on M13. Then, this timer is counted down, and when the count value reaches "0", the output of the three-state buffer 84 is checked again, and if the output is rOJ, it is determined that charging of the battery 79 has been completed within a predetermined time, and the flip-flop is Input "0" to the D input terminal of the step 85. Further, if the output is "1", it is determined that there is an abnormality in the battery because charging of the battery 79 cannot be completed within a predetermined time, and the lamp 18 and buzzer 19 notify the abnormality.

Also, as shown in Figure 7, when a transmission error occurs, it is first checked to see if a collision has occurred on the line, and if a collision has occurred, retransmission processing is performed, and if no collision has occurred, the data is retransmitted. It performs transmission, and if the result is the same again, it determines that the line is defective, turns off the line relay, and disconnects itself from the line. Note that in this case, a line failure may be immediately determined without performing data transmission again.

When the device is disconnected from the line, it then performs a self-loop test (self-diagnosis of the transmission control unit), and if any abnormalities are found, an error is detected. Also, if there is no abnormality, the line relay is turned on to connect itself to the line. Then, as shown in FIG. 5, a self-check command is sent to each terminal 31-3n via a dedicated self-check command line 100.

Figures 8 and 9 are CPLJ3 at terminals 31-3.
FIG. 8 shows the processing at the time of a transmission error, and FIG. 9 shows the self-check processing.

In other words, as shown in Figure 8, when a transmission error occurs, it is first checked to see if a collision has occurred on the line, and if a collision has occurred, retransmission processing is performed, and if no collision has occurred, the data is retransmitted. It performs transmission, and if the result is the same again, it determines that the line is defective, turns off the line relay, and disconnects itself from the line.

Note that in this case, a line failure may be immediately determined without performing data transmission again.

When the device is disconnected from the line, it then performs a self-loop test (self-diagnosis of the transmission control unit), and if any abnormalities are found, an error is detected. Also, if there is no abnormality, the line relay is turned on to connect itself to the line. Then, a timer for receiving self-check commands is set. If a self-check command is received before this timer times out, retransmission processing is performed after waiting for a certain period of time. If the self-check command is not received before the timer expires, it is determined that the other file unit is down, and the power control signal RPCC is transmitted to the other file unit.

Further, as shown in FIG. 9, when a self-check command is received at a terminal that is not transmitting data, it turns off the line relay and disconnects itself from the line. Next, a self-loop test (self-diagnosis of the transmission control unit) is performed, and if any abnormalities are found, an error is detected. Also, if there is no abnormality, the line relay is turned on to connect itself to the line.

In this embodiment having such a configuration, it is assumed that, for example, one file unit 1 is used as the main file unit, and the other file unit 2 is used for backup.

When the main switch 51.69 and the sub switch 55 of the file unit 1 are turned on, the IL source unit 52 is connected to the AC power supply 50, and a +5V voltage is raised. At this time, a RESET signal is generated and the flip 70 knob 85 is reset. Further, the light emitting diode 68 remains in an extinguished state.

When +5V voltage is applied, the CPU 11 sets the flip-flop 85 via the data bus line 21, turns on the transistor 62, and operates the relay 63. As a result, the normally open contact 66 of the relay 63 is turned on, and even if the main switch 51 is subsequently turned off, the power is maintained in the on state. When the main switch 51 is turned off, the switch 69 is also turned off, so the light emitting diode 68 lights up to indicate this.

Now, however, file unit 1 is switched to switch 51.
69 is turned off and the switch 55 is turned on, power is maintained through the normally open contact 66 of the relay 63, and data transmission control is performed with each terminal 31-3. At this time, the main switch 51 of the other file unit 2 used for backup is also turned off, and the sub switch 55 is turned on.

If a transmission error occurs in the file unit 1 in this state, it is checked whether the error is due to line collision, a failure in its own transmission section, or a failure on the terminal side. In the event of a failure in its own transmission unit, an error is generated with the line disconnected. Further, if there is no line collision and its own transmission section 11111M1 is normal, the line is connected and a self-check command is sent to each terminal 31 to 3n.

On the other hand, when the terminal that was transmitting to file unit 1 also detects a transmission error, it checks whether the error is due to line collision or a failure in its own transmission control unit. If there is no line collision at the terminal and its own transmission control unit is also normal, the line is connected and a self-check command reception timer is set.

If file unit 1 is not down, the self-check command will be received before the timer times out, so in this case the terminal waits for a certain period of time and then performs the retransmission process. However, if file unit 1 is down, the self-check command will not be received even if the timer times out, so the terminal will assume that file unit 1 is down because this self-check command is not received within the specified time. The file unit 2 determines that the file unit 2 is present and sends a power control signal RPCC to the other file unit 2 that is on standby as a backup.

When the power supply control signal RPCC is received from the terminal, the output of the comparator 74 in the file unit 2 becomes "1", that is, high level, and the transistor 60
is turned on, the relay 63 is operated, and its normally open contact 66 is turned on.

In this way, the power is turned on and power is supplied to the CPU 11 and other parts. Further, a RESET signal is generated to reset the flip-flop 85 to -H. CPU1
1 controls the three-state buffer 81 and reads its output. Since the output of this buffer 81 is "1", the CPU 11 sets the flip 70 knob 85 via the data bus line 21 and the control line 22, turns on the transistor 62 with the Q output, and turns on the relay 6.
The operating state of 3 is maintained. Therefore, even if the power control signal RPCC from the terminal is turned off, the power-on state is maintained.

In this way, file unit 2 automatically starts operating when II is started up, and quickly controls data transmission with the terminal in place of file unit 1, which has gone down.

Further, when the file unit 1 is operating normally, the file unit 2 is connected to the AC N source 50 by the power supply unit 52.
Since the main circuits such as the power supply unit 52 and the CPU 11 are not constantly energized, there is a risk that their lifespan will be shortened since the regulator 59 is only operating. There isn't.

Further, when the file unit 2 is disconnected from the power supply 50, the RAMs 13 and 14 are backed up by the battery 79. If the voltage of the battery 79 decreases in this state, the output of the comparator 75 becomes "0".
to "1". Thus, the transistor 61 is turned on, the relay 63 is operated, and the power supply unit 52 is connected to the AC power supply 50. Thus, the output of the power supply unit 52 is supplied to the battery 79 via the diode 53 and the resistor 54, and the battery 79 is charged. Also, when the output of the comparator 75 becomes "1", the flip 7
0 knob 83 is now set. However, the CPU
11 controls the three-state buffer 84 to read its output "1", sets the flip 70 knob 85 via the data bus line 21 and the control line 22, and sets the charging time timer.

Then, when the timer value of the timer reaches "0", the output of the buffer 84 is read again. Battery 79 within this time
If the charging of the comparator 75 is completed, the output of the comparator 75 becomes “0”.
'', and the 7-lip flop 83 is reset, so the output of the buffer 84 is ``0''. Therefore, if the output of the buffer 84 is rOJ, then the battery 7
9 is normally charged, the flip 70 knob 85 is reset, the transistor 62 is turned off, and the power supply unit 52 is disconnected from the AC power supply 50. In addition, battery 7
When charging of the transistor 9 is completed, the output of the comparator 75 becomes "0" at that point, and the transistor 61 is controlled to be off.

Further, even if the timer value of the charging timer reaches rOJ, if the output of the buffer 84 remains "1", it is determined that an abnormality has occurred in the battery 79, and the lamp 18
It is notified by lighting up and sounding the buzzer 19.

The file unit 2 used for backup in this way is backed up by the battery 79,
Moreover, even if the battery voltage drops during the process, the power is automatically turned on and charging is performed, providing reliable backup. Moreover, when a failure occurs in the battery 79, it can be detected and notified.

In the above embodiment, the battery charging time is checked using a timer to detect battery abnormality, but the invention is not limited to this. For example, a clock IC may be provided to detect battery abnormality when battery charging is completed. Store the time in the RAM 13, then read the time when the battery voltage drops and battery charging starts,
It may be determined that an abnormality has occurred in the battery when the time from when charging of the battery is completed to when charging is started is within a preset time.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to quickly switch over the file unit when it is down, and by turning on the power to the file unit only when it is in use, power consumption and lifespan are reduced. It is possible to provide an in-line system that can prevent such problems.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention. Figure 1 is a block diagram showing the overall configuration, Figure 2 is a block diagram showing the circuit configuration of the file unit, and Figure 3 is a block diagram showing the circuit configuration of the terminal. , Figure 4 is a circuit diagram showing the specific configuration of the power supply control circuit of the file unit, Figure 5 is a diagram showing the self-check command line connecting the file unit and the terminal, and Figure 6 is a diagram showing the CPU of the file unit.
Figure 7 is a flowchart showing the temporary transmission error processing by the file unit's CPU, Figure 8 is a flowchart showing the terminal's CPU to handle the temporary transmission error, and Figure 9 is a flowchart showing the terminal's power-on processing. It is a flowchart which shows the self-check process by CPU. 1.2... File unit, 31-3n... Terminal, 4... Data transmission line, 51.52...
・Power control signal transmission line, 11.31・C
PLJ, 12.32・ROM, 14-RAM7 isle,
15... Power supply control circuit, 16.34... Transmission controller, 52... Power supply unit, 60.61°62.
・NPN transistor, 63 ・Relay, 85 ・
...D type flip-flop. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] In an inline system in which a plurality of terminals that register and process product sales data and issue receipts are connected inline, and a file unit that files data processed by each terminal is connected inline, two of the file units are connected inline, Each of the file units has a power supply start-up means for turning on the power in response to a power control signal from each terminal, and a means for detecting a down state due to a failure in itself and disconnecting itself from the line and turning off the power. and a transmission control means that detects the power up by the power supply startup means, connects itself to the line, and controls data transmission with each terminal, and each terminal detects that one of the file units is down. 1. An inline system comprising: means; and means for transmitting a power control signal to the other file unit when the means detects that a file is down.