JPS6320975A - Solid-state image sensor - Google Patents

Abstract

PURPOSE:To suppress the narrowing width of a transmission line when an image is made of large number of picture elements, and to prevent the decrease in the quantity of transfer charges by allocating one piece of vertical transfer CCD to two photoelectric transducer strings in a vertical direction. CONSTITUTION:After accumulating signals from the respective photoelectric transducers for 1/60 second, i.e., for one field period, first, the transmission age 5 of the row A whose threshold voltage Vth is low opens, and the signal charges in this row are filed-shifted all at once to a vertical transmission CCD 2 during a part of vertical blanking period. Thus field-shifted charges are sequentially transferred downward, and read out from an output amplifier 4 via a horizontal CCD 3, and then are stored in a field memory 7 through a change- over switch 6. thereafter, the transmission gate 5 of a row B opens, and signal charges are read out from the output amplifier 4 likewise. In such case, the switch 6 is changed over, so that the signal charges from the row B are added with the signal from the row A already prepared in the field memory 7, and the resulting signals are outputted as a one field picture, and stored in a track of a magnetic disk 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a solid-state image sensor, and particularly to a solid-state image sensor that can suppress a decrease in the amount of transferred charge due to a narrow channel effect when increasing the number of pixels.

(Prior art) A conventional interline transfer CCD (ILCCD) is
One vertical transfer CCD is assigned to one photoelectric conversion element column in the vertical direction, and a plurality of sets consisting of these CCDs are arranged in the horizontal direction. If an attempt is made to increase the number of i elements, the channel width of the transfer line in the horizontal direction will inevitably become narrower under the same chip size.

(Problem to be solved by the invention) However, if the transfer line width is narrowed to, for example, about 2μ, the maximum transfer charge amount will drop to about 40% of the previous amount, and as a result, the dynamic range will be reduced. Oops.

The object of the present invention was achieved based on the above circumstances, and
An object of the present invention is to provide a solid-state image sensor that can suppress the narrowing of the transfer line when increasing the number of pixels and prevent a decrease in the amount of transferred charge.

(Means and actions for solving problems) That is,
The above object of the present invention is to provide an interline transfer type solid-state image sensor in which signals from two-dimensionally arranged charging conversion elements are sequentially read out using a vertical transfer CCD and a horizontal transfer CCD. 1 for column
A book vertical transfer CCD is provided, each light,
This is achieved by a solid-state image sensor characterized in that the signals of the electric conversion element rows are sequentially field-shifted and output.

By halving the number of vertical transfer CCDs in this manner, the channel width of the transfer line when increasing the number of pixels can be configured without being narrower than in a sensor with the same number of pixels.

Note that since the image sensor of the present invention transfers signals from two photoelectric conversion element rows using one vertical transfer CCD,
Transfer gates that field shift charges to vertical transfer CCDs are set to open at different timings.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 shown in FIG. 1 exemplifies a case where the solid-state image sensor of the present invention is applied to an electronic still camera.

This solid-state image sensor includes a plurality of photoelectric conversion elements 1 arranged in a matrix, and one vertical transfer CCD 2 arranged corresponding to two vertical columns of the photoelectric conversion elements 1.
, one horizontal transfer CCD 3 arranged along the horizontal direction on the output side of the vertical transfer CCD 2 , and an output amplifier 4 provided at the output end of the horizontal transfer CCD 3 .

The vertical transfer CCDs 2 are arranged in parallel so as to be sandwiched between two rows of photoelectric conversion elements 1, and a plurality of sets of 1 m of these CCDs are provided in the horizontal direction to form an image plane. In addition,
Although not shown in the figure, the vertical transfer CCD 2 is composed of a group of transfer elements arranged in the vertical direction corresponding to each photoelectric conversion element l, and transfers signal charges to the horizontal transfer CCD 3 by mutual operation. It is composed of a so-called self-scanning shift register with functions, and its surface is shielded from light.

A transfer gate 5 is formed for each element between the photoelectric conversion element 1 and the vertical transfer CCD 2, and controls the field shift of signal charges generated in each photoelectric conversion element 1 to the vertical transfer CCD 2.

The transfer gates 5 are controlled simultaneously in one vertical column, but
For the left and right photoelectric conversion element columns attached to one vertical transfer CCD 2, the respective threshold voltages are set to different values, and the timing of field shift of charges in the left and right columns is shifted. For convenience of explanation, in the figure, the photoelectric conversion element array arranged on the left side of one vertical transfer CCD 2 is designated as A, and the photoelectric conversion element array arranged on the right side is designated as B, and in this embodiment, two columns are used. The threshold voltage vth of the transfer gate 5 is set at A and B.

Further, in this embodiment, the solid-state image sensor of the present invention is incorporated into a still camera, and the output read from the output amplifier 4 is divided into two systems by a changeover switch 6, and one system is stored in the field memory 7. The data are then summed up and recorded on the magnetic disk 9 via the magnetic recording head 8.

Next, the operation of this image sensor will be explained based on the process of imaging a subject.

An electronic still camera to which a solid-state image sensor with such a configuration is applied is exposed to light by shutter operation and an optical image of the subject is formed through a shadow lens.Then, the optical image of the subject is formed through a shadow lens, and the light is projected onto each photoelectric conversion element. Electric charge is induced and accumulated in the area, forming an electric image.

After signal accumulation of each photoelectric conversion element is carried out for 1/60 seconds, that is, one field per field, the transfer gate 5 of the A column with the lower threshold voltage vth is first opened, and the signal charge of the cough column is The fields are all shifted to the vertical transfer CCD 2 at tS during the vertical blanking period. The field-shifted charges are sequentially transferred downward and read out from the output amplifier 4 through the horizontal CCD 3, and then stored in the field memory 7 through the changeover switch 6. Next, the transfer gate 5 of column B is opened and the signal charges of the column B are field-shifted and transferred all at once, and the signal charges are read out from the output amplifier 4 in the same manner.

At this time, the changeover switch 6 is switched, and the signal charge of the B column is summed with the signal of the column B already prepared in the field memory 7, and outputted as one L field and one track of the magnetic disk 9. recorded.

FIG. 2 shows another embodiment of the present invention, in which the solid-state image sensor of the present invention is applied to a movie.

Components that are the same as those in the embodiment shown in FIG. 1 are designated by the same reference numerals, and explanations thereof will be omitted. That is, in this example,
A charge storage section 10, a second horizontal CCD'll attached to the charge storage section 10, and a second output amplifier 12 are further added to the sensor of the embodiment shown in FIG. With this configuration, the signal charges in the first column are simultaneously transferred to the charge storage section 10 and stored therein. Next, when the signal charges in column B are field-shifted to the vertical transfer CCD 2, all transfer preparations are completed. - At this stage, the column charges stored in the charge storage section are transferred to the second horizontal CCD 11.
On the other hand, the charges in column B transferred to the vertical transfer CCD 2 are transferred to each signal f via the originally existing first horizontal CCD 3.
t loads are read out simultaneously. At this time, the charge in column B is 1! in column A! The data is read out with a half-bit shift relative to the
The charges in both columns are summed and output as one field of movie images.

As described above, by adding the charge storage section 10 and the horizontal CCD II, the sensor of this embodiment can transfer one of the photoelectric conversion element arrays to the charge storage section 10 at high speed.
Therefore, there is no need to shield the vertical transfer CCD 2 from light using a shutter or the like, and it can be applied to movies.

However, it goes without saying that the top of the charge accumulating section must be shielded from light at all times.

Note that in each of the above embodiments, signals were read out from the photoelectric conversion elements in the two columns by changing the threshold voltage of the transfer gates, but the wiring of each transfer gate was provided in a separate system to achieve the same reading. It can also be configured to control under voltage.

(Effects of the Invention) As described above, according to the solid-state image sensor of the present invention, one vertical transfer CC is provided for two rows of photoelectric conversion elements.
By allocating D, the number of vertical transfer CCDs can be cut in half, thereby preventing narrowing of the channel when increasing the number of pixels. In other words, when increasing the number of pixels, the transfer line width can be increased compared to a sensor with the same number of pixels, so a reduction in the dynamic range can be avoided without reducing the amount of transferred charge. Also, since the number of vertical transfer CCDs can be halved,
Manufacturability can also be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating a solid-state image sensor applied to one embodiment of the present invention, and FIG. 2 is a diagram illustrating a solid-state image sensor applicable to another embodiment.

Claims (1)

[Claims] 1) In an interline transfer type solid-state image sensor that sequentially reads out signals from photoelectric conversion elements arranged two-dimensionally using a vertical transfer CCD and a horizontal transfer CCD, two photoelectric conversion elements in the vertical direction are used. One vertical transfer CC per element row
1. A solid-state image sensor, wherein a signal from each photoelectric conversion element array is sequentially field-shifted and output. 2) The solid-state image sensor according to claim 1, wherein the transfer gates corresponding to the two photoelectric conversion element rows are provided with different threshold voltages. 3) The exposed imaging surface is exposed during at least one image transfer;
2. The solid-state image sensor according to claim 1, wherein the surface of the vertical transfer CCD is shielded from light. 4) The solid-state image sensor according to claim 3, wherein the light shielding means for shielding the surface of the vertical transfer CCD is a shutter.