JPS6320936A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To quicken data transmission without storing once a transmission signal by replacing preceding data information at the detection of address coincidence to serial data obtained by parallel/serial conversion of data information to be sent when the address coincidence is detected at the time of receiving synchronizing information and address information and resending the replaced data. CONSTITUTION:A synchronizing carrier generating circuit 16 generates a carrier signal (b) synchronously with the transmission speed of a reception signal (a), an address coincidence detection storage circuit 20 detects the coincidence between address information of the reception signal and the setting address and stores the result. A comparator 23 compares an address set by an address setting switch 22 like a LS 85 with an address stored after being subjected to parallel conversion by a serial/parallel converter 21 and outputs an address coincidence storage signal (d). In receiving a carrier signal (b) as a clock, the receiving signal (a) is retarded by a serial signal delay circuit 25 until the signal (a) has the same timing as a serial signal (c) of a parallel/serial converter 24. After the start of reception, a transmission changeover switch 26 is connected to the position (h) in the presence of the coincidence storage signal (d) when address information passes to change over the transmission signal to the serial signal (c). When no address coincidence storage signal (d) is given, the transmission signal is sent again as it is through a signal delay circuit 25.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data transmission device used in automatic machines and the like.

Conventional Technology In recent years, automatic machines have become more sophisticated through the use of microprocessors, and as a result, machines with hundreds or even thousands of sensors and actuators are no longer uncommon. The total amount of wiring for such automated machines exceeds several kilometers in length and hundreds of input/output points, making it difficult to respond to troubles, reducing reliability, and increasing the amount of wiring man-hours. Ta.

In order to reduce the number of wires, recently a control unit called a remote E/Q is placed close to each sensor/actuator, and a single optical fiber or electric wire is used to connect the units using serial multiplex transmission. Various methods have been proposed, but since the noise environment near automated machinery is extremely poor, optical transmission systems using optical fibers that are resistant to noise are considered promising.

FIG. 5 is a system diagram consisting of the remote controller 10. 1 is a sensor, 2 is an actuator, 3 is an input unit, and 4 is an output unit, and 3 and 4 will be referred to as slave stations from now on. Reference numeral 5 denotes a controller that controls all of these slave stations, and this is called a master station for the slave stations. 6 is an optical fiber or an electric wire. However, in optical transmission, passive tapping of optical fibers is extremely difficult, so regeneration is required for each slave station.

In this case, broadly classified, there are the following two transmission methods that can also transmit light.

Two types of optical transmission systems will be explained below with reference to the drawings.

FIG. 6 shows one such method.

In the figure, the transmission signal that has passed through the optical fiber 7 is converted into an electrical signal by a photoelectric converter 8, and then is transferred to a receiving buffer 9.
The data is stored in the transmission buffer 11 after being decoded and processed by the microprocessor 1o. Thereafter, it is converted into a serial signal, and converted again into an optical signal by the electrical/optical signal converter 12, and then transmitted.

FIG. 7 shows another optical transmission system.

In the figure, all the serial received signals converted to electrical signals are converted into a shift register 1 that can be converted into serial parallel and parallel serial.
It is temporarily stored in 3. After that, address-number construction circuit 1
When it is detected in step 4 that this unit is being accessed, the output latch 16 stores the output data 3o. Further, the data once stored in the shift register 13 is replaced with the input data 32, and the data is parallel-serial converted again and transmitted.

If the addresses do not match, the data is converted into parallel/serial data and sent.

Problems to be Solved by the Invention However, in the above configuration, since all one frame of the transmission signal is once stored and processed before being transmitted, there is no choice but to delay the transmission time of one frame or more. Each time the transmission passes through a transmission device, these delay times are accumulated, and as a result, the response of some automatic machines may become slow and uncontrollable, and when fast response is required, it is unavoidable to use parallel electrical wiring. There was a problem that it was unavoidable.

The present invention solves the above problems by using either light or electricity as a transmission medium, and replacing data information during reception in a transmission format in which address information precedes data information without temporarily storing the transmission signal. This provides high-speed data transmission by retransmitting the data while the data is being sent.

Means for Solving the Problems and the technical means of the present invention for solving the above problems are such that the address information matches a preset address in a transmission signal composed of synchronization information, address information, and data information. an address match detection storage circuit that detects and stores the transmission speed of the transmission signal; a synchronous carrier generation circuit that generates a carrier signal synchronized with the transmission speed of the transmission signal; and a synchronous carrier generation circuit that takes in the carrier signal output from the synchronous carrier generation circuit as a timing. A parallel-to-serial converter converts parallel data information to be transmitted into a serial signal, and a parallel-to-serial converter converts data information in the transmission signal being received by an address match signal output from the address match detection storage circuit to the parallel to serial converter. It consists of a transmission changeover switch circuit that replaces the serial signal, and a serial signal delay circuit that delays the transmission signal being received until it reaches the same timing as the serial signal output from the parallel-serial converter.

According to the above-described configuration, when an address match is detected by the address match detection storage circuit at the time when synchronization information and address information are received, the subsequent data information and the data information to be transmitted are parallelized by the parallel-serial converter.・Since retransmission is performed by replacing the serial data that has been serially converted, the transmission signal can be transmitted without being stored once, and high-speed data transmission can be performed.

At this time, the serial signals of the synchronization information and address information in the received signal are delayed by the serial signal delay circuit until the timing to receive input data from the outside, so the waveform is not disturbed due to the replacement of data information. Almost never occurs. Therefore, stable data transmission can be achieved. Also, generally the carrier signal is ○N10FF of the received signal.
Since the pulse can be generated with a delay of approximately half the pulse width, the delay time until the received signal is retransmitted by the carrier signal is 0N10FF of the received signal.
The time is approximately half the pulse width, thus enabling high-speed data transmission.

Embodiment Hereinafter, a loop data transmission device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a data transmission device in one embodiment. In FIG. 1, reference numeral 16 denotes a synchronous carrier generation circuit, which generates a carrier signal synchronized with the transmission speed of the received signal a.

An example of an internal circuit is shown in detail: 17 is a clock oscillator, 18 is a counter such as LS393,
19 is an SR clip-flop.

When the reception of the transmission signal a starts, the SR flip-flop 19
is set, the CLR of the counter 18 is released, the clock of the oscillator 17 is divided, and a carrier signal S synchronized with the transmission speed of the received signal a is generated with a delay of about half the 0N10FF pulse width of the received signal.

When the number of carrier pulses required to receive one frame of the transmission signal is counted up, the SR flip-flop 19 is reset and stands by for reception.

Reference numeral 20 denotes an address match detection storage circuit that detects and stores the match between the address information of the signal being received and the set address. Describing one embodiment of the internal circuit in detail, 21 is a serial/parallel converter such as an LSI 64, which converts serial address information into parallel address information and stores the same.

23 is address setting switch 2 like LSss, for example.
The address set in step 2 is compared with the address parallel-converted and stored by the serial-parallel converter 21, and an address-number storage signal d is output. Reference numeral 29 is a gate for maintaining the parallel output state by setting the carrier signal to 0FFj after serial/parallel conversion of the address information. Reference numeral 24 denotes a parallel-to-serial converter which converts parallel input data into a serial signal cK using the carrier signal outputted from the synchronous carrier generation circuit 16, such as an LSI 65, as a clock input. 26
is a serial signal delay circuit that delays the received signal a until it reaches the same timing as the serial signal C output from the parallel-to-serial converter 24. In this embodiment, the same carrier signal as that of the parallel-to-serial converter 24 is applied to the D-type flip-flop as a clock input, so that the received signal a is parallel-to-serial converted at the same timing as the serial signal C output from the converter 24. It's delayed. 26 is a transmission selector switch, which is normally set to i.
connected to the side. When reception is started and the address information has passed, an address-number storage signal d is output from the address coincidence detection storage circuit and connected to the side of the bus h, and thereafter the transmission signal is switched to the serial signal C.

Further, if the address-number storage signal d is not output, switching is not performed, and the received signal delayed through the signal delay circuit 26 is retransmitted as it is.

27 is a serial/parallel converter that converts data information in a received signal into serial/parallel data. 28 is an output latch circuit that latches the output when an address matches.

FIG. 2 shows a transmission format of a loop-shaped transmission device in one embodiment. The transmission format consists of at least synchronization information for generating a synchronized carrier signal and address information and data information for distinguishing the slave station to be accessed, and the transmission order is as follows: synchronization information address information, data information The order is as follows.

A to G in Figure 3 are B in Figure 1 when the addresses match.
-, -(Each signal waveform of 7, fi % of Fig. 4 (7 is each signal waveform of a - q of Fig. 1 when the address does not match, and the transmitted signal q is the carrier of the received signal aK) This shows that the reproduction is delayed by approximately one pulse width of l.

The operation of the loop data transmission device configured as described above will be explained below with reference to FIGS. 1, 3, and 4.

When a received signal such as the one shown in FIG. 3A is received, the SR flip-flop 19 is set and the counter 1 is
The oscillation clock f is frequency-divided by 9 to generate a carrier signal as shown in FIG.

In this embodiment, the clock frequency is 24 MHz.

It is assumed that the frequency of the oscillation clock f is divided so that the frequency of the carrier signal is twice the transmission speed of the received signal. The frequency division ratio is selected to be 4 or more, and in this embodiment, the oscillation clock is divided by 4. Therefore, the transmission speed of this embodiment is 6
Mbps. The received signal a is connected to the serial input bin of the serial-to-parallel converter 21 constituting the address-replacement storage circuit 2o, and the necessary number of carriers j is given by the gate 29 to perform serial-to-parallel conversion of the address information. It will be done. This parallel address information and address setting switch 2
2 by the comparator 23, and if they match, the address -
The number storage signal d is output and the transmission changeover switch 26 is switched from the i side to the h side. Thereafter, the transmission signal q is replaced by input data C which is converted into a serial signal by the parallel-to-serial converter 24, and a transmission waveform as shown in FIG. 3Q is output. Furthermore, this book-
In the embodiment, when switching transmission, the received signal a becomes the serial signal C.
Since the same carrier signal as the clock input signal of the parallel-to-serial converter 24 is added to the clock input of the D flip-flop 25 and delayed so that the timing is the same as that of the clock input signal of the parallel-to-serial converter 24, there is very little disturbance in the waveform due to transmission switching.

Also, in Fig. 3, after receiving the received waveform a, the transmitted waveform q
The delay time from the start of reception to the rise of the carrier signal is the time required to output the signal, and the transmission speed is extremely small at 140 to 220 nSeC in this embodiment.

On the other hand, parallel output of the data information of the received signal a is performed as follows. That is, one serial data information is converted into parallel data by the serial input and clock input of the received signal a and the carrier signal A, respectively, of the serial/parallel converter 27. If the addresses match, the output latch circuit latches the parallelized data, and the latched parallel signal can be obtained as output data.

Next, a case where the addresses do not match will be explained.

If the address does not match, send switch 2
6 remains on the i side. The received signal a is the data input of the D-type 7 flip-flop 26, and the carrier signal is also input as the clock input, so the output waveform i of the D flip-flop, that is, the transmitted waveform q, is as shown in 9 in FIG.
The waveform will be reproduced into exactly the same waveform as the received waveform a. Also, at this time, no parallel data is input or output.

Effects of the Invention The present invention does not store the received signal once, but replaces the data information when the address information matches during reception, and retransmits it. Therefore, transmission delays can be extremely minimized, and the received signal is Since the signal is delayed until the timing is the same as that of the serial signal output from the parallel-serial converter, waveform disturbances due to switching of transmission data can be extremely reduced, and the following effects are also achieved.

In other words, in the case of optical transmission, when converting an optical ○N10FF signal into an electrical ON/○FF signal, the ratio of ON time and OFF time changes depending on the amount of received light, so the pulse width is distorted and the signal remains unchanged. There was a problem that as the conversion into electrical and optical signals was repeated, the distortion in the pulse width gradually increased, and eventually normal transmission could no longer be performed.However, in the present invention, as a serial signal delay circuit, for example, By using a D-type flip-flop, it is possible to shape the waveform of a distorted received signal so that the ratio of ON time and OFF time is equal, so that normal data transmission can be achieved even if many transmission devices of the present invention are connected in a loop. It can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a loop-shaped optical data transmission device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a transmission format used in the embodiment, and FIGS. Signal waveform diagram of each signal a-q, Fig. 5 is a conventional remote controller) Il
FIG. 6 is a block diagram showing an example of a conventional loop-shaped optical data transmission device, and FIG. 7 is a block diagram showing another example of the conventional loop-shaped optical data transmission device. 16...Synchronized carrier generation circuit, 2o...
... Address-replacement storage circuit, 24 ... Parallel-serial converter, 26 ... Serial signal delay circuit, 26
......Transmission selector switch. Name of agent: Patent attorney Toshio Nakao and one other person Ic
-・λ to J1 Yukine Tria A5 Saji li! 1st 2nd
Figure 3 Figure 4

Claims (1)

[Claims] An address match detection memory circuit that detects and stores a match between address information and a preset address in a transmission signal consisting of synchronization information, address information, and data information, and an address match detection memory circuit that is synchronized with the transmission speed of the transmission signal. a synchronous carrier generation circuit that generates a carrier signal output from the synchronous carrier generation circuit; a parallel-to-serial converter that converts parallel data information to be transmitted into a serial signal by taking in the carrier signal output from the synchronous carrier generation circuit as a timing; and the address coincidence detection memory. a transmission changeover switch circuit for replacing data information in a transmission signal being received with a serial signal of the parallel-serial converter by an address matching signal output from the circuit; and outputting the transmission signal being received from the parallel-serial converter. A data transmission device consisting of a serial signal delay circuit that delays the serial signal until it reaches the same timing as the serial signal.