JPS63209347A - Buffer assignment system for data exchange network - Google Patents

Buffer assignment system for data exchange network

Info

Publication number
JPS63209347A
JPS63209347A JP62041469A JP4146987A JPS63209347A JP S63209347 A JPS63209347 A JP S63209347A JP 62041469 A JP62041469 A JP 62041469A JP 4146987 A JP4146987 A JP 4146987A JP S63209347 A JPS63209347 A JP S63209347A
Authority
JP
Japan
Prior art keywords
buffer
regulation
restriction
idle
transition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62041469A
Other languages
Japanese (ja)
Inventor
Noriaki Kishino
岸野 訓明
Hiroshi Manba
博 萬羽
Takaaki Ozeki
尾関 隆章
Toshihiko Inagaki
敏彦 稲垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62041469A priority Critical patent/JPS63209347A/en
Priority to US07/127,502 priority patent/US4845710A/en
Priority to CA000555065A priority patent/CA1287182C/en
Priority to EP87311414A priority patent/EP0272939B1/en
Priority to AU82988/87A priority patent/AU599183B2/en
Priority to KR1019870014817A priority patent/KR920009387B1/en
Priority to DE3789706T priority patent/DE3789706T2/en
Publication of JPS63209347A publication Critical patent/JPS63209347A/en
Pending legal-status Critical Current

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  • Data Exchanges In Wide-Area Networks (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

PURPOSE:To attain stable control providing an idle buffer management section managing number of idle buffers and corresponding to the boundary value of the transition to the state strengthening the restriction in each stage to a smaller idle buffer number from the boundary of the transition of restriction relax. CONSTITUTION:An idle buffer management section 11 obtains the information of return from a transmission section 8 to a high-order device and the idle buffer information of a common buffer pool 10 and the reception buffer loop 13 to apply management to an idle buffer of the buffer 10 timely in response to the buffer 13. Each stage of the restriction value of the reception buffer number is decided in response to the idle buffer number managed by the management section 11. Then the idle buffer number is decreased and the stage is transited to the strengthened restriction at the next point of time and the stage is transited to the stage of relaxed restriction with the increased idle number similarly. The condition of the transition to the strengthened restriction is not transited when the transition to the relaxed restriction reaches the idle buffer number decided smaller than the idle buffer number decided in this way.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、データリンクアクセスプロトコル制御装置の
バッファ割当方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a buffer allocation method for a data link access protocol control device.

(従来の技術) パケット交換におけるバッファ管理方式について、電通
学会による昭和57年度電子通信学会通信部門全国大会
vol−178の「トラヒック制御方式における地域ふ
くそう制御」、及び日本電信電話株式会社による研究実
用化報告vol−35No、 5の53頁から61頁の
「パケット交換網のトラヒック制御アルゴリズム」に記
載の各方式がある。
(Prior art) Regarding the buffer management method in packet switching, research and practical application were conducted by the Institute of Electro-Communications Engineers of Japan in the 1985 IEICE Telecommunications Division National Conference vol-178 entitled "Regional Congestion Control in Traffic Control Methods" and by Nippon Telegraph and Telephone Corporation. There are various methods described in "Traffic Control Algorithm for Packet Switched Networks" on pages 53 to 61 of Report Vol. 35 No. 5.

前者の方式は入基幹回線の全話中時間率の各水準値とホ
ッパートランサクションメモリ (バッファ)の全話中
時間率の各水準値との相関によって、複数段階の規制に
より、その規制と解除とを同一のしきい値を用いて、ふ
くそう制御を行うようにしている。
The former method is based on the correlation between each level value of the total busy time ratio of the incoming trunk line and each level value of the total busy time ratio of the hopper transaction memory (buffer), and the regulation is controlled and released in multiple stages. The same threshold value is used to perform congestion control.

また、後者の方式はプロセッサ使用率とバッファ使用率
との相関によって、パケット呼に対して複数段階のふく
そう制御を行うようにしている。
Furthermore, the latter method performs multiple stages of congestion control on packet calls based on the correlation between the processor usage rate and the buffer usage rate.

(発明が解決しようとする問題点) しかしながら、前記した前者の方式においては、入基幹
回線とバッファとの両者の各水準値との対応を監視する
必要があるので、制御が繁雑になり、そして規制とその
解除とを同一のしきい値によって行なっているので制御
が不安定になるおそれがある。また、バッファの使用率
を監視してないので蓄積交換機の制御には向いていない
(Problems to be Solved by the Invention) However, in the former method described above, since it is necessary to monitor the correspondence between each level value of both the incoming trunk line and the buffer, the control becomes complicated, and Since the same threshold value is used for regulation and its release, there is a risk that the control may become unstable. Also, since the buffer usage rate is not monitored, it is not suitable for controlling a storage/exchange machine.

一方、後者の方式においては、プロセッサ使用率とバッ
ファ使用率について、前者におけると同様にその各対応
を監視する必要があるので制御が繁雑になる。そして、
パケット呼のみに対する制御であるから、複数の種類の
サービスに対応し得ない。
On the other hand, in the latter method, it is necessary to monitor each correspondence between the processor usage rate and the buffer usage rate, as in the former method, so the control becomes complicated. and,
Since the control is only for packet calls, it cannot support multiple types of services.

(問題点を解決するための手段) 本発明は前記問題点を解決するために、データリンクア
クセスプロトコル制御装置に複数のサービス群の通信相
手装置が接続され該多通信相手装置からの送受信用情報
を蓄積するためのバッファの割当数を管理するバッファ
管理方式において、通信相手装置との送受信用情報の蓄
積に使用可能な単位時間当りの空バッファ数を管理する
空バッファ管理部と、通信相手装置からの信号受信に必
要な単位時間当りに使用する受信用バッファ数の規制値
を各サービス群に共通の所定の空バッファ数に対応させ
て複数の所定の空バッファ数との対応によって複数の段
階をもって各サービス群毎に設定した規制設定回路とを
設け、前記各段階相互の規制強化への移行の境界値を規
制緩和への移行の境界値より空バッファ数を小に対応さ
せた。
(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a data link access protocol control device that is connected to communication partner devices of a plurality of service groups, and transmits and receives information from the multiple communication partner devices. In a buffer management method that manages the number of allocated buffers for storing information, an empty buffer management unit that manages the number of empty buffers per unit time that can be used to store information for transmission and reception with a communication partner device, and a communication partner device The regulation value of the number of reception buffers used per unit time required for receiving signals from the service group is set to correspond to a predetermined number of empty buffers common to each service group, and the regulation value is set in multiple stages by corresponding to a plurality of predetermined numbers of empty buffers. A regulation setting circuit is provided for each service group, and the boundary value for transition to stricter regulation between each stage is made to correspond to a smaller number of empty buffers than the boundary value for transition to deregulation.

(作 用) 本発明によれば、空バッファ管理部によって管理される
空バッファ数に応じて、当該受信用バッファ数の規制値
の各段階が決まる。そして空バッファ数が減少したこと
によって、当該段階かつぎの時点において規制強化の段
階に移行し、同様に、増大したことによって規制緩和の
段階に移行するが、規制強化への移行の条件は、規制緩
和への移行が定められている空バッファ数より小に定め
られた空バッファ数にならないと移行しない。前記各段
階の規制値は各サービス群毎に設定されていて、各サー
ビス群がその規制値によって規制される。
(Function) According to the present invention, each stage of the regulation value for the number of reception buffers is determined according to the number of empty buffers managed by the empty buffer management section. Then, as the number of empty buffers decreases, the number of empty buffers shifts to the phase of tightening regulations at that stage and the next point in time, and similarly, as the number of empty buffers increases, it shifts to the phase of relaxing regulations.However, the conditions for shifting to tightening regulations are The transition to relaxation does not occur unless the number of empty buffers becomes smaller than the specified number of empty buffers. Regulation values for each stage are set for each service group, and each service group is regulated by the regulation value.

(実施例) 第1図は本発明の一実施例を示し、ディジタル統合サー
ビス網(ISDN)におけるデータリンクアクセスプロ
トコル制御装置のシステム構成図である。
(Embodiment) FIG. 1 shows one embodiment of the present invention, and is a system configuration diagram of a data link access protocol control device in an integrated services digital network (ISDN).

同図において、1はデータリンクアクセスプロトコル制
御装置、2は下位レイヤからの受信部、3は通信相手装
置としての一サービス群の回線交換用端末、4は同様な
他のサービス群のパケット交換用端末、5は処理待ちキ
ュー、6は処理装置、7は送信処理待ちキュー、8は上
位への送信部、9は上位レイヤ装置、10は共通バッフ
ァプール、11は空バッファ管理部である。
In the figure, 1 is a data link access protocol control device, 2 is a receiving unit from a lower layer, 3 is a circuit switching terminal for one service group as a communication partner device, and 4 is a packet switching terminal for another similar service group. 1 is a terminal, 5 is a processing queue, 6 is a processing device, 7 is a transmission processing queue, 8 is a transmission unit to an upper level, 9 is an upper layer device, 10 is a common buffer pool, and 11 is an empty buffer management unit.

12はデータ蓄積部、13は受信用バッファプールで、
データ蓄積部12は、回線交換用端末3またはパケット
交換用端末4から受けた送受信用情報を、受信用バッフ
ァプール13から提供される各バッファ14に蓄積し、
処理装置6に送出する。15は受信規制制御回路で、処
理装置6の後記する規制値設定に基づいて、データ蓄積
部12による前記蓄積と送出とを規制する。16はその
規制値通知用のリードである。
12 is a data storage unit, 13 is a receiving buffer pool,
The data storage unit 12 stores the transmission/reception information received from the circuit switching terminal 3 or the packet switching terminal 4 in each buffer 14 provided from the reception buffer pool 13.
The data is sent to the processing device 6. Reference numeral 15 denotes a reception regulation control circuit, which regulates the storage and transmission by the data storage unit 12 based on regulation value settings, which will be described later, of the processing device 6. 16 is a lead for notification of the regulation value.

処理装置6は、キュー5のデータについて、データ転送
機能仕様書(S D L : 5pecificati
onand Description Languag
e)に基づいて分析を行ない、上位に対する情報内容の
変換処理を行なって、送信処理待ちキュー7に送出する
。上位への送信部8はキュー7のバッファ17のデータ
を上位レイヤ装置9に送出するとともに、使用済みバッ
ファを共通バッファプール10に返却する。空バッファ
管理部11は、上位への送信部8からの前記返却の情報
と、共通バッファプール10、受信用バッファプール1
3の空バッファ情報とヲ得て、共通バッファブール1o
の空バッファを受信用バッファ13に適時に供給管理す
るとともに、空バッファ通知用リード18を介して、処
理装置6に対して受信用バッファプール10における単
位時間当りの空バッファ数Bを通知する。19は相手端
末への送信部である。
The processing device 6 complies with the data transfer function specification (SDL: 5 specific) regarding the data in the queue 5.
onand Description Language
The data is analyzed based on e), and the information content is converted to a higher level, and then sent to the transmission processing waiting queue 7. The upper transmitter 8 transmits the data in the buffer 17 of the queue 7 to the upper layer device 9, and returns used buffers to the common buffer pool 10. The empty buffer management unit 11 receives the return information from the upper-level transmission unit 8, the common buffer pool 10, and the receiving buffer pool 1.
3 empty buffer information and common buffer Boolean 1o
It manages the supply of empty buffers to the reception buffer 13 in a timely manner, and notifies the processing device 6 of the number B of empty buffers per unit time in the reception buffer pool 10 via the empty buffer notification lead 18. Reference numeral 19 is a transmitting unit to the other party's terminal.

処理装置6はまた、規制設定回路6Aを備え、該規制設
定回路6Aは各端末3,4が使用する受信用バッファ数
を規制するための各段階の規制状態変数(規制フラグ)
rを設けていて、通常状態(非規制状態)をr−0,第
1規制状態をr−1゜第2規制状態をr−2に設定して
いる。そして各状態r−0,r=1.r=2の相互間の
移行については空バッファ管理部11から通知されるバ
ッファ数Bによって管理される。
The processing device 6 also includes a regulation setting circuit 6A, and the regulation setting circuit 6A sets regulation state variables (regulation flags) at each stage to regulate the number of reception buffers used by each terminal 3, 4.
The normal state (non-restricted state) is set to r-0, the first restricted state is set to r-1°, and the second restricted state is set to r-2. And each state r-0, r=1. Transfer between r=2 is managed by the number of buffers B notified from the empty buffer management unit 11.

第2図は、前記移行を含む規制の管理条件を示した受信
用バッファ規制条件図、第3図は各規制状態間の移行の
条件図である。
FIG. 2 is a receiving buffer regulation condition diagram showing the regulation management conditions including the above-mentioned transition, and FIG. 3 is a condition diagram of transition between each regulation state.

該各図において、w、x、y、zは、空きバッファ数B
と照合するための所定のバッファ数を示す各しきい値で
、互いにz>y>x>Wの関係にあり、しきい値Wは、
空バッファ数Bとの関係がBowのとき、第1規制状態
r−1がら第2規制状態r=2への規制強化の移行を設
定したその境界値をなす。そして、しきい値Xは、Bo
xのとき、第2規制状態r=2から第1規制状態r−1
への規制緩和の移行を設定した境界値をなす。そして、
しきい値yは、BSyのとき、通常状態r−〇から第1
規制状態r=1への規制強化の移行を設定した境界値を
なす。そして、しきい値2はB>zのとき、第1規制状
態r=1から通常状態r=oへの規制緩和の移行を設定
した境界値をなす。
In each figure, w, x, y, z are the number of free buffers B
Each threshold value indicates a predetermined number of buffers for checking with each other, and there is a relationship of z>y>x>W, and the threshold value W is
When the relationship with the number of empty buffers B is Bow, it forms the boundary value that sets the transition of enforcement of regulation from the first regulation state r-1 to the second regulation state r=2. And the threshold value X is Bo
When x, the second regulation state r=2 to the first regulation state r-1
This constitutes a threshold that sets the transition to deregulation. and,
The threshold value y is set from the normal state r−〇 to the first
This is the boundary value that sets the transition to stricter regulation to the regulation state r=1. When B>z, the threshold value 2 is a boundary value that sets the transition of deregulation from the first regulation state r=1 to the normal state r=o.

処理装置6の規制設定回路6Aはまた、各状態r=o、
rwl、r−2における規制値として、回線交換用端末
3とパケット交換用端末4のそれぞれからの信号受信に
必要な単位時間当りに使用する受信用バッファ数mci
とmpl  (但しiはrの値に対応して、i−0,1
,2)とを設定していて、各状態r=Qとr−1とr−
2に応じて、各規制値mco、mpO,とmci 、m
plとmc2.mp2を受信規制制御回路15に与える
The regulation setting circuit 6A of the processing device 6 also sets each state r=o,
As a regulation value for rwl and r-2, the number of receiving buffers mci used per unit time required for receiving signals from each of the line switching terminal 3 and the packet switching terminal 4 is
and mpl (where i corresponds to the value of r, i-0,1
, 2), and each state r=Q, r-1, and r-
2, each regulation value mco, mpO, and mci, m
pl and mc2. mp2 to the reception restriction control circuit 15.

規制設定回路6Aは、更にまた、各端末3.4に対して
、通常状態r−0から第1規制状態r=1または第2規
制状態r−2に移行の際は相手端末への送信部19を介
して受信不可(受信規制)通知RNRを送出し、通常状
態r=0に移行の際は同様にして受信可(規制の解除)
通知RRを送出する。そして上位レイヤ装置9に対して
は、通常状態r−0または第1規制状態r−1から第2
規制状態r−2に移行の際は上位への送信部8を介して
使用中(送信規制)通知BUSYを送出し、通常状態1
 == Qに移行の際は同様にして使用可(規制の解除
) gqB U S Y解除を送出する。
Furthermore, the regulation setting circuit 6A provides a transmitter to each terminal 3.4 to the other terminal when transitioning from the normal state r-0 to the first regulation state r=1 or the second regulation state r-2. Sends a notification RNR that reception is not possible (reception restriction) via 19, and when transitioning to normal state r = 0, reception is possible in the same way (restriction is lifted)
Send notification RR. Then, for the upper layer device 9, the normal state r-0 or the first restricted state r-1 to the second restricted state
When transitioning to restriction state r-2, a busy (transmission restriction) notification BUSY is sent via the transmitter 8 to the upper layer, and the state returns to normal state 1.
== Can be used in the same way when moving to Q (release of restrictions) Send gqB U S Y release.

つぎに第1図の回路における処理装置6を主体とした受
信用バッファ数の規制の動作を説明する。
Next, a description will be given of the operation of regulating the number of reception buffers mainly using the processing device 6 in the circuit shown in FIG.

第4図は受信用バッファ数規制動作のフローチャートで
ある。
FIG. 4 is a flowchart of the operation for regulating the number of reception buffers.

第4図において、各ステップSL、S2.END1のル
ートは、端末3,4が使用する受信用バッファ数を規制
しない通常状態r−0が継続されている状態である。即
ち、空バッファ管理部11による空バッファ数Bと所定
のしきい値2との関係がB>zであって(ステップS1
)、規制フラグr−0のときは(S2)、通常状態が継
続している状態であり、受信規制制御回路15に対して
各規制値mco、mpo (非規制)を送出している。
In FIG. 4, each step SL, S2. The route of END1 is a state in which the normal state r-0 in which the number of reception buffers used by the terminals 3 and 4 is not restricted is continued. That is, if the relationship between the number of empty buffers B determined by the empty buffer management unit 11 and the predetermined threshold value 2 is B>z (step S1
), when the restriction flag is r-0 (S2), the normal state continues, and each restriction value mco, mpo (non-restricted) is sent to the reception restriction control circuit 15.

ステップS1〜S5 、END2のルートは、第1規制
状態r−1または第2規制状態r−2から通常状態r=
oに移行する状態を示している。空バッファ数Bが通常
状態r−0への規制強化のレベルにあって(SL ) 
、フラグrが1または2であるから(S2 ) 、各規
制値mc o、mp oがセットされ、通常状態r=o
となる(S3)。そして上位レイヤ9に対して規制の解
除通知BUSY解除を送出しくS4)、各端末3,4に
対して規制の解除通知RRを送出する(S5)。
The route from steps S1 to S5 and END2 is from the first regulation state r-1 or the second regulation state r-2 to the normal state r=
This shows the state of transition to o. The number of empty buffers B is at the level of stricter regulation to the normal state r-0 (SL)
, since the flag r is 1 or 2 (S2), the respective regulation values mco and mpo are set, and the normal state r=o
(S3). Then, a restriction release notification BUSY release is sent to the upper layer 9 (S4), and a restriction release notification RR is sent to each terminal 3, 4 (S5).

ステップSL 、SO、S7 、END3のルートは、
前記ステップENDIに至るルートと同様に通常状態r
−0が継続されている状態である。
The routes of steps SL, SO, S7, and END3 are as follows:
Normal state r similar to the route leading to step ENDI
-0 continues.

ステップSl、86〜Sll、END4のルートは、通
常状態r−0から第2規制状態r−2に移行する状態を
示している。即ち規制フラグrが0であって(SB)、
空バッファ数BがB<wであると(SB ) 、各規制
値mc7! 、mp2がセットされ、第2規制状態r−
2となる(SO)。そして上位レイヤ9に送信規制通知
BUSYを送出しく510)、各端末3,4に受信規制
通知RNRを送出する( S 11)。
The route from steps Sl, 86 to Sll, END4 shows a transition state from the normal state r-0 to the second restricted state r-2. That is, the regulation flag r is 0 (SB),
If the number of empty buffers B is B<w (SB), each regulation value mc7! , mp2 are set, and the second regulation state r-
It becomes 2 (SO). Then, it sends a transmission restriction notification BUSY to the upper layer 9 (510), and sends a reception restriction notification RNR to each terminal 3, 4 (S11).

ステップSl、S6〜S8 、S12.  Sll、E
ND4のルートは、通常状態r−0から第1規制状態r
−1に移行する状態を示し、各規制値met 。
Steps Sl, S6-S8, S12. Sll, E
The route of ND4 is from the normal state r-0 to the first regulation state r
-1, each regulation value met.

mplがセットされ(S 12)る。そして各端末3゜
4に受信規制通知RNRを送出する( S 11)。
mpl is set (S12). Then, a reception restriction notification RNR is sent to each terminal 3.4 (S11).

ステップSL 、SO、S13.S14.END5は、
第1規制状態r−1が継続中であって、各規制値mci
、mplを送出している。
Steps SL, SO, S13. S14. END5 is
The first regulation state r-1 is continuing, and each regulation value mci
, mpl is being sent.

ステップSl 、  SO、S17〜S19.END[
iは、第2規制状態r=2から第1規制状態r−1に移
行する状態を示している。即ち空バッファ数BがB>x
であって(S13)、規制フラグrが2であると(S1
4)、各規制値mal 、mplがセットされる( S
 15)。
Steps Sl, SO, S17-S19. END[
i indicates a transition state from the second restriction state r=2 to the first restriction state r-1. That is, the number of empty buffers B is B>x
(S13), and the regulation flag r is 2 (S1
4), each regulation value mal, mpl is set (S
15).

ステップSL 、SB 、813.SlB、END7は
、第1規制状態r=1または第2規制状態r=2が継続
中であって前状態に応じて各規制値m c 1. 。
Steps SL, SB, 813. SlB, END7 indicates that the first regulation state r=1 or the second regulation state r=2 is continuing and each regulation value m c 1. .

m p 1 、またはmc2 、mp2を送出している
m p 1 or mc2, mp2 is being sent.

ステップSl 、  SB 、  S13.  SIB
、  S17.  END8は第2規制状態r=2が継
続中であって各規制値mc2 、mp2を送出している
Steps Sl, SB, S13. SIB
, S17. At END8, the second regulation state r=2 is continuing, and the regulation values mc2 and mp2 are being sent.

ステップSL 、  SB 、  813.  S1B
、  S17〜S19゜END9は第1規制状態r=1
から第2規制状態r=2に移行する状態を示している。
Steps SL, SB, 813. S1B
, S17 to S19° END9 is the first regulation state r=1
This shows a state in which the state shifts from the state to the second regulation state r=2.

各規制値mc2.mp2がセットされ、規制フラグrが
2となり(S18)、上位レイヤ9に対して送信規制通
知BUSYを送出する。
Each regulation value mc2. mp2 is set, the restriction flag r becomes 2 (S18), and a transmission restriction notification BUSY is sent to the upper layer 9.

(発明の効果) 以上説明したように、本発明によれば、各サービス群に
共通の空バッファ数を監視して、且つ共=  11 − 通の所定の空バッファ数との対応によって各規制の段階
に位置づけるようにし、そして各サービス群毎に規制値
を定めているので制御が単純化された上で、サービス群
毎に優先度をつけた制御が可能になる。そして各段階相
互の規制強化への移行の境界値を規制緩和への移行の境
界値より空バッファ数を小に対応させたので、安定して
制御が得られる。また、単位時間当りの空バッファ数を
監視しているので、微小時間に対応させた連応性の制御
が得られる。
(Effects of the Invention) As explained above, according to the present invention, the number of empty buffers common to each service group is monitored, and each regulation is Since the service groups are positioned in stages and regulation values are determined for each service group, control is simplified and control can be performed with priority given to each service group. Since the boundary value for transition to stricter regulation at each stage is made to correspond to a smaller number of empty buffers than the boundary value for transition to relaxed regulation, stable control can be obtained. Furthermore, since the number of empty buffers per unit time is monitored, it is possible to obtain responsive control corresponding to minute time periods.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す制御装置のシステム構
成図、第2図は受信用バッファ規制条件図、第3図は各
規制状態間の移行の条件図、第4図は第1図の回路の受
信用バッファ数規制動作のフローチャートである。 6A・・・規制設定回路 11 ・・・空バッファ管理部
Fig. 1 is a system configuration diagram of a control device showing an embodiment of the present invention, Fig. 2 is a reception buffer regulation condition diagram, Fig. 3 is a condition diagram of transition between each regulation state, and Fig. 4 is a diagram of the first 3 is a flowchart of an operation for regulating the number of reception buffers of the circuit shown in the figure. 6A... Regulation setting circuit 11... Empty buffer management section

Claims (1)

【特許請求の範囲】 データリンクアクセスプロトコル制御装置に複数のサー
ビス群の通信相手装置が接続され該各通信相手装置から
の送受信用情報を蓄積するためのバッファの割当数を管
理するバッファ管理方式において、 通信相手装置との送受信用情報の蓄積に使用可能な単位
時間当りの空バッファ数を管理する空バッファ管理部と
、 通信相手装置からの信号受信に必要な単位時間当りに使
用する受信用バッファ数の規制値を各サービス群に共通
の所定の空バッファ数に対応させて複数の所定の空バッ
ファ数との対応によって複数の段階をもって各サービス
群毎に設定した規制設定回路とを設け、 前記各段階相互の規制強化への移行の境界値を規制緩和
への移行の境界値より空バッファ数を小に対応させてい
ることを特徴とするデータ交換網のバッファ割当方式。
[Claims] In a buffer management method in which communication partner devices of a plurality of service groups are connected to a data link access protocol control device and the number of allocated buffers for storing transmission/reception information from each of the communication partner devices is managed. , an empty buffer management unit that manages the number of empty buffers per unit time that can be used to accumulate information for transmission and reception with the communication partner device, and a reception buffer that is used per unit time necessary for receiving signals from the communication partner device. a regulation setting circuit in which a regulation value of the number is set for each service group in a plurality of stages in correspondence with a plurality of predetermined numbers of empty buffers in correspondence with a predetermined number of empty buffers common to each service group; A buffer allocation method for a data exchange network, characterized in that a boundary value for transition to stricter regulations at each stage is made to correspond to a smaller number of empty buffers than a boundary value for transition to relaxed regulations.
JP62041469A 1986-12-23 1987-02-26 Buffer assignment system for data exchange network Pending JPS63209347A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP62041469A JPS63209347A (en) 1987-02-26 1987-02-26 Buffer assignment system for data exchange network
US07/127,502 US4845710A (en) 1986-12-23 1987-12-01 Dynamic buffer supervising system for a data link access protocol control
CA000555065A CA1287182C (en) 1986-12-23 1987-12-22 Dynamic buffer supervising system for a data link access protocol control
EP87311414A EP0272939B1 (en) 1986-12-23 1987-12-23 Dynamic buffer supervising system for a data link access protocol control
AU82988/87A AU599183B2 (en) 1986-12-23 1987-12-23 Dynamic buffer supervising system for a data link access protocol control
KR1019870014817A KR920009387B1 (en) 1986-12-23 1987-12-23 Dynamic buffer supervising system for a data link access protocol control
DE3789706T DE3789706T2 (en) 1986-12-23 1987-12-23 Dynamic buffer monitoring system for controlling a data link access protocol.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62041469A JPS63209347A (en) 1987-02-26 1987-02-26 Buffer assignment system for data exchange network

Publications (1)

Publication Number Publication Date
JPS63209347A true JPS63209347A (en) 1988-08-30

Family

ID=12609228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62041469A Pending JPS63209347A (en) 1986-12-23 1987-02-26 Buffer assignment system for data exchange network

Country Status (1)

Country Link
JP (1) JPS63209347A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0715466A (en) * 1993-06-21 1995-01-17 Nec Corp Congestion control system for data processing system
JPH08251226A (en) * 1995-03-14 1996-09-27 Chiyoukousoku Network Computer Gijutsu Kenkyusho:Kk Congestion reporting method
US7580348B2 (en) 2002-11-29 2009-08-25 Fujitsu Limited Communication apparatus, control method, and computer readable information recording medium
JP2011009876A (en) * 2009-06-23 2011-01-13 Nippon Telegr & Teleph Corp <Ntt> Buffer circuit and buffer circuit control method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787260A (en) * 1980-11-19 1982-05-31 Fujitsu Ltd Buffer control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787260A (en) * 1980-11-19 1982-05-31 Fujitsu Ltd Buffer control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0715466A (en) * 1993-06-21 1995-01-17 Nec Corp Congestion control system for data processing system
JPH08251226A (en) * 1995-03-14 1996-09-27 Chiyoukousoku Network Computer Gijutsu Kenkyusho:Kk Congestion reporting method
US7580348B2 (en) 2002-11-29 2009-08-25 Fujitsu Limited Communication apparatus, control method, and computer readable information recording medium
JP2011009876A (en) * 2009-06-23 2011-01-13 Nippon Telegr & Teleph Corp <Ntt> Buffer circuit and buffer circuit control method

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