JPS63209281A - Video signal storing method - Google Patents

Abstract

PURPOSE:To reduce the capacity of a memory by forming a period which is not stored in a memory within the synchronizing signal period of a video signal at the time of storing a composite video signal in the memory. CONSTITUTION:The synchronizing signal of the video signal has three types. During the period A, all levels are synchronizing tip levels, so that this period is not stored in the memory. Thereby, information stored in the field memory 5 includes only a part except the period A. At the time of reading, the same timing as a writing time may be formed from the constantly inputted video signal, the data of the field memory 5 may be read and the synchronizing tip level may be applied to the period A. In such a way, a part of the synchronizing signal period is not stored in the memory, thereby, the capacity of the memory can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for storing composite video signals used in various video equipment such as TVs and VTRs, and in particular to a method for converting video signals into digital signals. The present invention relates to a processing method for storing video images by writing and reading them into a memory.

[Conventional technology]

Recently, in the consumer VTR industry, the function of applying memory to obtain still images has been attracting attention because of its ability to obtain still images without noise bars. This method uses a capacity equivalent to 18 64k DRAMs as a memory, encodes the video signal into a 6-bit composite at a sampling frequency of 3fsc (fsc: color subcarrier frequency), and encodes one field of the video signal. It is a way of remembering.

[Problem that the invention seeks to solve]

The conventional video storage described above is revolutionary for VTRs in that it is possible to create still images without noise bars without using the Q1 special head with variable tape running speed. Furthermore, by implementing a gate array in the digital controller section and using a general-purpose DRAM as the memory, there are many advantages such as simplicity and versatility, but the following points are not taken into consideration.

In the above method, the image data to be written to the memory is 1
One field (262,5H) is used.

When encoding at a sampling frequency of 3 fsc, a memory capacity of 179.157 bits is required to store one field for one bit of the video signal. However, the composite video signal stored here includes a synchronization signal for each line, and the level is constant at the sync chip level during this period, so there is no need to store it in the memory as data.

This point is a factor in increasing the memory capacity for storage.

The present invention is unique in that memory capacity is reduced by not storing part of the synchronization signal period in memory.

[Means for solving problems]

The video signal storage method according to the present invention divides the video signal for one field into lines, and stores each line sequentially in the memory, so that the video signal is stored in the memory during the horizontal synchronization signal period of each line. This creates a long period and reduces memory capacity.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an embodiment of the present invention, which is a block diagram of main parts when configuring a still image. From the input composite video signal 1, the synchronization signal/burst signal separation circuit 2
The composite synchronization signal Sy and the color burst signal fsc are separated, and a horizontal synchronization/vertical synchronization/clock generation circuit 9 generates a horizontal synchronization signal HD.

Vertical synchronization signal VD, sampling clock signal 3fsc
(synchronized with the color burst signal), outputs a signal 4QfH multiplied by 40 of the horizontal synchronization signal. Pulse generator circuit 1
At 0, the timing required for the memory is created by signals HD, VD, 3fsc, and 40fH. on the other hand,
The video signal 1 is sync-chip clamped by a circuit 2, and converted into a digital signal 4 by an A/D converter 3 using a sampling clock SC1 generated by a pulse generator circuit 10. The digital signal 4 is constantly input to the field memory 5, and data writing continues until the read/write control circuit 11 enters the read mode (compatible with still image output). During writing, the digital signal 4 passes through the field memory 5, and the writing to the D/A conversion mudfield memory 5 is stopped, and the data written immediately before continues to be read out, which becomes a still image.

Now, there are three types of synchronization signals for video signals as shown in FIG. 2, but since the human period is all at the sync chip level, this period is not stored in the memory. As a result, the information stored in the field memory 5 is only the part excluding the period A in FIG. At the time of reading, the data of the field memory 5 may be read out using the same timing as the time of writing using the constantly inputted video signal, and the sync chip level may be applied for the period A.

〔Effect of the invention〕

As described above, the present invention makes it possible to reduce memory capacity by not storing part of the synchronization signal period in memory. Set the period A in Figure 2 to the vertical equalization pulse width (
2,3 μs ± 0.1 μS)' (i-considering, 2.14
μs (If the sampling clock is 3fsc and 23 periods are 1, then 9 1 field is stored per 1 bit = 173,239...
...(2)? , 173,239 bits of memory is sufficient. If 6-bit encoding of the video signal is considered, the memory capacity can be expressed as Equation (1) 2
It can be calculated from formula (2), and in the end it is 1074.942-103
,434=35,508<bits).

Furthermore, in the above-described embodiment, the period during which no data is stored in the memory is limited to the period A in FIG. The signal period is 26.98 μs (289 cycles with sampling clock fsc), and the horizontal synchronization signal period is 4.6 μs (49 cycles with sampling clock 3fsc).
period). In this case, the memory capacity is =660X6+394X3+634X253+2
93=165.837 ・
...(3), and when 6-bit encoding is considered, the memory capacity is as follows from equations (1), 9, and (3): 79
, it is possible to reduce the capacity by 920 bits, which is effective for downsizing and lowering the cost of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of the present invention, and FIG. 2 is a waveform diagram of different types of synchronization signals. 1...Input video signal, 2...Sync signal/burst signal separation circuit, 3...A/D converter, 4...Digital video signal, 5...Field memory, 6...Digital video signal, 7
・・・・・・D/A converter, 8・°. ... Output video signal, 9 ... Horizontal synchronization/vertical synchronization/clock generation circuit, 10 ... Pulse generator circuit, 11 ... Read/write control circuit.

Claims (1)

[Claims] A video signal storage method characterized in that when storing a composite video signal in a memory, a period in which the composite video signal is not stored in the memory is created within a synchronization signal period of the video signal, thereby making it possible to reduce memory capacity.