JPS63209227A - Decoder circuit - Google Patents

Abstract

PURPOSE:To decrease the number of configuration transistors by constituting a decoder of logical circuit the same in number as output terminals, and constituting respective logical circuits of a pair of transistors complementarily opened and closed by a clock signal and a transistor controlled by first or second input terminals. CONSTITUTION:For example, when input signals D0 and D1 are both '0', (n) channel transistors n1 and n2 of a first logical circuit 1 are turned on and an output terminal 11 is shifted to a low level. Since second (n) channel transistors n4 and n6 and n8 of second and fourth logical circuits 2-4 are turned off, output terminals 12-14 stay at a high level. Hereinafter, in the same way, second (n) channel transistors n2, n4, n6 and n8 are selectively opened and closed in accordance with the voltage level of the input signals D0 and D1 and outputs X0-X3 are obtained. Since such logical circuits 1-4 are composed of three transistors, for a decoder circuit 15, four transistors can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoder circuit, and particularly to a dynamic decoder circuit.

[Prior Art] Conventionally, as this type of decoder circuit, a 2(n) input 4 (2 to the n power) output dynamic type decoder circuit as shown in FIG. 2 has been known. The decoder circuit will be explained as a conventional example.

In FIG. 2, 21 is a power supply terminal, 22 is a clock terminal, 23 is an input terminal for the input signal DO, 24 is an input terminal for the inverted signal Do (over par) of the input signal DO,
25 is the input terminal of the input signal D1, 26 is the input terminal of the input signal D1
The input terminal of the inverted signal DI' (over par) is connected to 27
indicates a ground (GND) terminal, and 28 to 31 indicate output terminals, respectively.

When decoding an input signal, first, the clock signal φ is shifted to a low level, and each of the four p-channel transistors is turned on to precharge the output terminals 28 to 31. Next, the clock signal φ is shifted to a high level to cut off the output terminals 28 to 31 from the power supply VDD, and the 12 n-channel The transistors are selectively opened and closed to determine the voltage level at output terminals 28-31. That is, the input signal, its inverted signal D
When O to DI (over par) is at a high level, the n-channel transistor to which the signal is applied turns on and the output terminal is grounded, but when it is at a low level, the n-channel transistor remains off and the output terminal is connected to the power supply. Level V
Maintain DD. Therefore, output signals XO to X3 determined based on the voltage levels of input signals DO to DI (over par) are obtained at the output terminals 28 to 31.

As a result, in the case of the decoder circuit shown in FIG.
The relationships shown in Table 1 hold between o, DI and the output signals X1 to X3.

[Problems to be Solved by the Invention] However, the conventional dynamic decoder circuit described above requires the same number of precharging transistors as the number of output terminals in order to precharge the output terminals. 2'X (2
+n) transistors were required. Therefore, there is a problem in that as the number of inputs (n) increases, the number of transistors forming the decoder circuit also increases rapidly.

In particular, when attempting to integrate a conventional decoder circuit, there is a problem in that the area occupied on the semiconductor substrate increases due to the increase in the number of constituent transistors.

Accordingly, an object of the present invention is to provide a decoder circuit with a reduced number of constituent transistors.

[Means for Solving the Problems] The first invention of the present application has a plurality of first input terminals to which a plurality of input signals are respectively supplied, and a second input terminal to which an inverted signal of the plurality of input signals is supplied. , a power terminal to which a power supply voltage is supplied, a clock terminal to which a clock signal is supplied,
A decoder circuit comprising a decoding section for decoding the input signal and an output terminal at which an output signal appears, and generating the output signal after precharging the output terminal in response to a clock signal. A pair of transistors configured with the same number of logic circuits as output terminals, provided in parallel between the power supply terminal and the first input terminal or the second input terminal, and opening and closing each of the logic circuits in a complementary manner according to a clock signal. and a transistor interposed between the pair of transistors and controlled by the first input terminal or the second input terminal to form the output signal.

A second invention linked to the first invention provides a plurality of first input terminals to which a plurality of input signals are respectively supplied, a second input terminal to which an inverted signal of the plurality of input signals is supplied, and a power supply voltage. The device includes a power supply terminal to which a power supply is supplied, a clock terminal to which a clock signal is supplied, a decoding section that decodes the input signal, and an output terminal from which an output signal appears, and the output terminal is precharged in response to the clock signal. In a decoder circuit that later generates the output signal, the decoder section has a plurality of decoder sections, each decoder section having an output node connected to another decoder section or the output terminal, and the power supply terminal and the first input terminal,
A pair of transistors, each consisting of the same number of logic circuits as output nodes, which are provided in parallel with the second input terminal or the output node of another decoder section, and which open and close each of the logic circuits in a complementary manner according to a clock signal. , a transistor interposed between the pair of transistors and controlled by the output note of the first input terminal, the second input terminal, or another decoder section to determine the voltage level of the output node. There is.

[Operation of the Invention] The decoder circuit of the first invention of the present application having the above configuration turns on one of a pair of transistors in response to a clock signal,
When the other is turned off, the output terminal is connected to the power supply terminal and precharged. Next, when one of the pair of transistors is turned off and the other turned on by a clock signal, an output signal corresponding to the open/closed state of the transistor forming the output signal appears at the output terminal. That is, the transistor forming the output signal is connected to the first input terminal or the second input terminal via the other of the pair of transistors that are turned on, and is controlled by the first input terminal or the second input terminal. Therefore, an output signal having a certain relationship to the input signal is obtained at the output terminal.

On the other hand, in the case of the decoder circuit according to the second invention of the present application, each decoder part operates similar to the decoder circuit of the first invention, and the output signal is output from a predetermined decoder part among the plurality of decoder parts. can get.

[Embodiments] Hereinafter, embodiments of the first invention and the second invention of the present application will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the first invention of the present application, and a simplified representation of the circuit of FIG. 1 is shown in FIG. This embodiment is a decoder circuit with two manpower and four outputs, similar to the conventional example.

In FIG. 1, 1 is a logic circuit constructed by connecting a p-channel transistor 1 and n-channel transistors nl, n2 in series, and 2 to 4 are also composed of one p-channel transistor 2 to p4 and two p-channel transistors. Each of the figures shows a logic circuit constructed by connecting n-channel transistors n3 to n8 in series. The drains of the p-channel transistors are commonly connected to the power supply terminal 5, and therefore the p-channel transistors 1 to p4 are supplied with the power supply voltage VDD. Furthermore, since the gates of p-channel transistors 1 to p4 are commonly connected to clock signal terminal 6, p-channel transistors 1 to p4 are opened and closed under control of the voltage level of clock signal φ. First n-channel transistors nl, n3 . of logic circuits 1 to 4; n5. Since the gate of n7 is also commonly connected to clock signal terminal 6, I
O- first n-channel transistor nl, n3. n
5°nl and the p-channel transistors 1 to p4 operate in a complementary manner. Therefore, the p-channel transistors 1 to p4 and the first n-channel transistor nl,
n3. n5. nl constitutes a pair of transistors in each logic circuit.

Among the first n-channel transistors, the sources of nl and n5 are connected to the input terminal 7 of the input signal DO, and the sources of n3 and nl are connected to the input terminal 8 of the inverted signal DO (over par) of the input signal DO. On the other hand, the second n-channel transistor n2. of each logic circuit 1 to 4.
n4. n6. Of n8, the gates of n6 and n8 are connected to the input terminal 9 of the input signal D1, and the gates of n2 and n4 are connected to the input terminal 10 of the inverted signal DI (over par) of the input signal D1. There is. Furthermore, p-channel transistors 1 to p4 and second n-channel transistors n2. n4. n6. A connection node with n8 is connected to output terminals 11 to 14. Therefore, the voltage levels of the output terminals 11 to 14 are changed by the second n-channel transistor n2. n4゜n6. Since it is determined by the state of n8, the second
The n-channel transistor constitutes a transistor that forms an output signal in each logic circuit 1 to 4.

Next, the operation of the decoder circuit 15 shown in FIG. 1 will be explained. First, when the clock signal φ is shifted to a low level, the p-channel transistors 1 to p4 are turned on, and the first
N-channel transistors nl, n3. n5. nl turns off. As a result, the output terminals 11 to 14 are connected to the power supply voltage V
DD is precharged.

Next, when the clock signal φ is shifted to a high level, the p-channel transistors 1 to p4 are turned off, and the output terminal 1 is turned off.
1 to 14 are cut off from the power supply terminal 5. Moreover, the 1st n
Channel transistor nl.

n3. n5. nl is turned on, the first and second n-channel transistors n1 to n8 are opened and closed according to the voltage levels of the input signals DO to DI (over par), and the results appear at the output terminals 11 to 14. For example, input signal D
When both o and DI are "0" (low level), both n-channel transistors nl and n2 of the first logic circuit 1 are turned on, and the output terminal 11 shifts to a low level, but the second to fourth logic second n-channel transistor n4 of circuits 2 to 4; n6. Since all of n8 are off, output terminals 12 to 14 all remain at high level. Similarly, the second n-channel transistors n2, n4, . . . n6. n8 is selectively opened and closed to produce the same outputs XO to X as shown in Table 1 above.
3 is obtained.

Since the logic circuits 1 to 4 of the decoder circuit 15 are composed of three transistors, the decoder circuit 15 is composed of a total of 12 transistors, and four transistors are required to obtain the same result as the conventional example. can be reduced.

FIG. 4 is a block diagram showing the configuration of the first embodiment of the second invention of the present application. In FIG. 4, 41 to 43 are decoder parts having the same configuration as the decoder circuit 15 shown in FIG. are input signals DO to D2
This is a 0 inverted signal. Also, YO to Y3 are decoder parts 4
1, and XO to X7 are output signals of the decoder circuit according to this embodiment. Therefore, in this embodiment, the decoder parts 41, 42, and 43 constitute a decoder circuit that can be powered by three people and has eight outputs.

Since the operation of the decoder portions 41, 42, and 43 of this embodiment is the same as that of the decoder circuit 15, detailed explanation will be omitted.
Table 2 shows the relationship between input signals DO to D2 and output signals YO to Y3.
Table 3 shows the relationship with 7.

(Hereinafter, blank space) −14=5λ” Therefore, the decoder circuit according to the first embodiment of the second invention of the present application can be configured with a total of 36 transistors, and the same result can be obtained with the conventional decoder circuit. The number of transistors can be reduced by four compared to the case.

Next, a second embodiment of the second invention of the present application will be described with reference to FIG. A second embodiment of the second invention has a decoder portion 515.5 having the same configuration as the decoder circuit 15 shown in FIG.
2.53.54.55.56.57 constitutes a 4-person powered 16-output decoder circuit. In this embodiment as well, the operation of each decoder portion 51 to 57 is determined by the decoder circuit 1.
Since it is the same as 5, the detailed explanation is omitted, and inputs DO to D
3 and the outputs XO to X15 can be expressed by the following logical formula % Formula % Therefore, in the second embodiment of the second invention of the present application, a four-man power 16-output decoder circuit can be constructed with 84 transistors, and the conventional decoder 12 transistors compared to the circuit
We were able to reduce the number of items.

[Effects of the Invention] As described above, in the decoder circuit according to the first invention of the present application, the number of transistors is equal to the number of output terminals x 3, and the number of constituent transistors can be reduced compared to the conventional decoder circuit.

Further, in comparison with the conventional example, in the input 2 output decoder circuit (k=n+1) according to the present invention, the number of constituent transistors is 12 (2'-'-1), compared to the conventional example. The difference in the number of transistors becomes significant as the value of k, that is, the value of n, increases.

Therefore, the present invention also has the effect of facilitating integrated circuit implementation.

[Brief explanation of the drawing]

1 is a circuit diagram showing the configuration of an embodiment of the first invention of the present application; FIG. 2 is a circuit diagram showing the configuration of a conventional example; FIG. 3 is a block diagram showing a simplified representation of the circuit in FIG. 1; The figure is a block diagram showing the structure of the first embodiment of the second invention of the present application, and FIG. 5 is a block diagram showing the structure of the second embodiment of the second invention of the present application. 1.2.3.4...Logic circuit, 5...Power terminal, 6...Clock terminal, 7.9...・
...Input terminal (first input terminal), 8.10...Input terminal (second input terminal), 11.12. 13.14...Output terminal, pi, p2゜p3. p4...◆...p channel transistor, nl, n3゜n5. n7...First n-channel transistor, n2. n4゜n6. n8... Second n-channel transistor, 41.42.43. 51.52.53. 54.55.56.57 ・・・・・・Decoder part. Figure 1 1 Figure 2

Claims (2)

[Claims] (1) A plurality of first input signals each supplied with a plurality of input signals.
an input terminal; a second input terminal to which an inverted signal of the plurality of input signals is supplied; a power supply terminal to which a power supply voltage is supplied; a clock terminal to which a clock signal is supplied; and a decoding unit that decodes the input signal. and an output terminal at which an output signal appears, and generates the output signal after precharging the output terminal in response to a clock signal, wherein the decoder circuit is connected to the power supply terminal and the first input terminal or It consists of the same number of logic circuits as output terminals provided in parallel between two input terminals, and a pair of transistors that open and close each of the logic circuits in a complementary manner according to a clock signal, and a pair of transistors interposed between the pair of transistors. A decoder circuit comprising: a transistor controlled by the first input terminal or the second input terminal to form the output signal. (2) a plurality of first input signals each supplied with a plurality of input signals;
an input terminal; a second input terminal to which an inverted signal of the plurality of input signals is supplied; a power supply terminal to which a power supply voltage is supplied; a clock terminal to which a clock signal is supplied; and a decoding unit that decodes the input signal. and an output terminal at which an output signal appears, the decoder circuit generating the output signal after precharging the output terminal in response to a clock signal, the decoder section having a plurality of decoder parts, Each decoder section has an output node connected to the other decoder section or the output terminal, and is arranged in parallel between the power supply terminal and the first input terminal, the second input terminal or the output node of the other decoder section. a pair of transistors that are configured of the same number of logic circuits as output nodes, each of which is opened and closed in a complementary manner by a clock signal; and the first input terminal and the second input terminal that are interposed between the pair of transistors. or a transistor that is controlled by an output node of another decoder section and determines the voltage level of the output node.