JPS63209218A - Bidirectional interface circuit - Google Patents

Bidirectional interface circuit

Info

Publication number
JPS63209218A
JPS63209218A JP62043351A JP4335187A JPS63209218A JP S63209218 A JPS63209218 A JP S63209218A JP 62043351 A JP62043351 A JP 62043351A JP 4335187 A JP4335187 A JP 4335187A JP S63209218 A JPS63209218 A JP S63209218A
Authority
JP
Japan
Prior art keywords
data
terminal
circuit
type
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62043351A
Other languages
Japanese (ja)
Inventor
Sanae Okamoto
岡本 早苗
Shiro Nishijima
西嶋 史郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62043351A priority Critical patent/JPS63209218A/en
Publication of JPS63209218A publication Critical patent/JPS63209218A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018592Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

PURPOSE:To convert data from the logical level of a certain level to other logical level with bidirectionality by connecting the titled circuit with plural integrated circuits each different in power source potential, and setting in output terminal at an I/O control terminal. CONSTITUTION:A low voltage type output circuit 108 is turned off and a high voltage type output circuit 107 is turned on. The data of a low potential level inputted from an I/O terminal 102 are converted through a level shifter due to an inverter G4, P-type FETs Q3 and Q5 and N-type FETs Q4 and Q5 to a P-type FETG1 and a high voltage type voltage amplitude and given through gates G1 and G2 to a P-type FETG1 and an N-type FETQ2. The data are outputted from these FETQ1 and Q2 to an I/O terminal 101 as the data of the high voltage type. When the high voltage type data are converted to low voltage type data, an 'H' level signal is set to an I/O control terminal 103. Thus, the low voltage type output circuit 108 is turned on, the high voltage type output circuit 107 is turned off and as the result, the flow of the data is converted reversely, inputted and outputted.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はインターフェイス回路に関し、特に異電源で駆
動される複数の集積回路のデータ転送を、電圧変換回路
を用いる事によって双方向で行なうインターフェイス回
路に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interface circuit, and particularly to an interface circuit that bidirectionally transfers data between multiple integrated circuits driven by different power sources by using a voltage conversion circuit. Regarding.

〔従来の技術〕[Conventional technology]

従来、この種のインターフェイス回路は、第3図に示す
様にI10端子を二つ組み合わせ、I10コントロール
端子303により、302で示すI10端子からデータ
を取り込み、301で示すI10端子からそのデータを
出力するか、又は301を入力端子として、302より
データを出力するかを選択する様になっていた。尚、3
01゜302.303及び集積回路の論理レベルは同一
である。
Conventionally, this type of interface circuit combines two I10 terminals as shown in FIG. 3, receives data from the I10 terminal indicated by 302 using the I10 control terminal 303, and outputs the data from the I10 terminal indicated by 301. Alternatively, the user could select whether to use 301 as an input terminal and output data from 302. In addition, 3
01°302.303 and the logic level of the integrated circuit are the same.

これを何段か積み重さねて第4図に示す様に、401.
402の端子によって404から40′3へデータを転
送するか、又は403がら404にデータを転送するか
を選択できる事を利用し、マイクロコンピュータのRO
M、RAMとデータ・バスとのインターフェイス用に用
いられる等の従来技術がある。
By stacking these in several stages, as shown in Fig. 4, 401.
The microcomputer's RO
There are conventional techniques such as M, used for interfacing RAM and data buses.

〔発明か解決しようとする問題点〕[Problem that the invention attempts to solve]

上述した従来のインターフェイス回路は、自身の回路の
論理レベルを集積回路の論理レベルと同一にし、コント
ロール信号によってI10切り替えを行ない、複数の集
積回路間のデータのやりとりを行っている為、異電源を
もつ複数の集積回路間のデータ転送を双方向で行なう事
が不可能であるという欠点がある。
The conventional interface circuit described above makes the logic level of its own circuit the same as the logic level of the integrated circuit, switches I10 using a control signal, and exchanges data between multiple integrated circuits, so it is difficult to use different power supplies. A drawback is that it is impossible to transfer data bidirectionally between multiple integrated circuits.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のインターフェイス回路は、高電圧の論理レベル
に入出力するI10端子、及び前記論理レベルにより振
幅の小さい低電圧の論理レベルに入出力するI10端子
を各々の論理レベルにて駆動する集積回路に接続し、レ
ベル・シフターを介して異電圧の論理レベルに変換し、
■/○コントロール端子にて出力端子を選択する機能を
持つ。
The interface circuit of the present invention is an integrated circuit that drives an I10 terminal that inputs and outputs at a high voltage logic level and an I10 terminal that inputs and outputs an input and output at a low voltage logic level with a smaller amplitude depending on the logic level. connected and converted to a different voltage logic level via a level shifter,
■/○ Has the ability to select the output terminal using the control terminal.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例を示す回路図である。1
01はある電源系を持つ集積回路と、データの受は渡し
を行なう為のI、10端子である。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. 1
01 is an integrated circuit with a certain power supply system, and I and 10 terminals are used for receiving and passing data.

102は101より低い電源系を持つ集積回路と、デー
タの受は渡しを行なうI10端子であ。104は101
に接続する集積回路と同一の電源電位が与えられる端子
であり、105は102に接続する集積回路と同一の電
源電位が与えられる端子である。106はグランドであ
る。103はI10コントロール端子である。なお、同
一の電圧系の集積回路間のインターフェイスを可能にす
ること、および、生産性を考えると各回路の耐電圧特性
は同一とすることが望ましい。
102 is an integrated circuit having a power supply system lower than that of 101, and an I10 terminal which receives and transfers data. 104 is 101
105 is a terminal to which the same power supply potential as the integrated circuit connected to 102 is applied. 106 is a ground. 103 is an I10 control terminal. Note that, in order to enable an interface between integrated circuits of the same voltage system, and considering productivity, it is desirable that each circuit have the same withstand voltage characteristics.

インターフェイスの例として低電源系(例えば3V系)
の集積回路と、工/○端子102を接続しこれにより入
力したデータを高電源系(例えば5V系)の集積回路に
接続したI10端子101に出力するに至るまでの動作
を述べる。この場合、I10端子101をOUT端子と
し、I10端子102より入力したデータを出力する為
にI10コントロール端子103にロー(以下“′L′
′とする)レベルを設定する。
An example of an interface is a low power system (e.g. 3V system)
The operation up to connecting the integrated circuit and the I10 terminal 102 and outputting the input data to the I10 terminal 101 connected to the integrated circuit of a high power supply system (for example, 5V system) will be described. In this case, the I10 terminal 101 is set as the OUT terminal, and in order to output the data input from the I10 terminal 102, the I10 control terminal 103 is set to a low level (hereinafter referred to as "'L").
’)) Set the level.

I10コントロール端子103に設定されたL ”レベ
ル信号はNANDゲートイーおよび、インバータG7を
介してNORゲートG6に入力され、ANDゲーイー5
 、NORゲートG6の出力によってP形F E T 
Q 7およびN形FETQ8をOFFの状態にするとと
もに、NORゲートG2およびインバータG3を介して
NANDゲートG1に入力され、各イー)Gt、Gzの
他の入力端子に入力されるデータを通過させる。すなわ
ち、低電圧系出力回路108をOFFとし、高電圧系出
力回路107をONとする。I10端子102より入力
された低電位レベルのデータはインバー−5= りG4、P形FETQ3.G5およびN形FETQ4.
G6によるレベルシフタを介して高電圧系の電圧振幅に
変換され、イーT’G 1.G2を経て出力用P形FE
TG、およびN形FETQ2に与えられ、これらFET
Ql、G2から高電圧系のデータとしてI10端子10
1へ出力される。
The L'' level signal set to the I10 control terminal 103 is input to the NOR gate G6 via the NAND gate E and the inverter G7, and
, P-type FET by the output of NOR gate G6
Q7 and N-type FET Q8 are turned off, and the data that is input to the NAND gate G1 via the NOR gate G2 and inverter G3 and input to the other input terminals of each of Gt and Gz is passed. That is, the low voltage output circuit 108 is turned off and the high voltage output circuit 107 is turned on. The low potential level data input from the I10 terminal 102 is input to the inverter-5=G4, P-type FET Q3. G5 and N-type FET Q4.
It is converted into a voltage amplitude of a high voltage system through a level shifter by G6, and E T'G 1. P type FE for output via G2
TG, and N-type FETQ2, and these FETs
I10 terminal 10 as high voltage system data from Ql, G2
Output to 1.

高電圧系のデータを低電圧系のデータに変換する場合、
I10コントロール端子103に゛H″レベル信号を設
定することにより、低電圧系出力回路108がONとな
り、高電圧系出力回路107がOFFの状態になり、そ
の結果データの流れは前述と逆に変換されて入出力され
る。
When converting high voltage system data to low voltage system data,
By setting a "H" level signal to the I10 control terminal 103, the low voltage system output circuit 108 is turned ON and the high voltage system output circuit 107 is turned OFF, and as a result, the data flow is converted in the opposite manner as described above. input and output.

第2図は第2の実施例を示す回路図である。206をグ
ランドとし、204は201に接続する集積回路と同一
の電源電位であり、低電位側を共通にしている第1の実
施例に対し、高電位側を共通にしたインターフェイス回
路であって機能としては第1の実施例と全く同じである
FIG. 2 is a circuit diagram showing a second embodiment. 206 is the ground, and 204 is the same power supply potential as the integrated circuit connected to 201. This is an interface circuit that has a common high potential side, and functions as opposed to the first embodiment, which has a common low potential side. This is exactly the same as the first embodiment.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は異なる電源電位の複−6= 数の集積回路と、本発明のインターフェイス回路を接続
しI10コントロール端子にて出力端子を設定する事に
より、あるレベルの論理レベル′を他の論理レベルに双
方向性を持ってデータを変換できる効果がある。
As explained above, the present invention connects multiple integrated circuits with different power supply potentials to the interface circuit of the present invention and sets the output terminal using the I10 control terminal, thereby achieving a certain logic level. It has the effect of bidirectionally converting data to other logical levels.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例を示す回路図、第2図は
本発明の第2の実施例を示す回路図、第3図は従来のイ
ンターフェイス回路の一例を示す図、第4図は従来のイ
ンターフェイス回路を積み重ねて複数の集積回路のデー
タを双方向に転送するブロック図である。 101.201は高電圧系集積回路とのI10端子、1
02,202は低電圧系集積回路との■10端子、10
3,203はコントロール端子、104は高電圧系の+
側電源端子、105は低電圧系の+側電源端子、106
,206はグランドレベル、107.207は高電圧系
の出力回路、108.208は低電圧系の出力回路、1
09゜209はレベルシフタ、204は高電圧系の一側
電源端子、205は低電圧系の一側電源端子。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, FIG. 3 is a diagram showing an example of a conventional interface circuit, and FIG. The figure is a block diagram in which conventional interface circuits are stacked to transfer data from multiple integrated circuits in both directions. 101.201 is the I10 terminal with the high voltage integrated circuit, 1
02, 202 is ■10 terminal with low voltage integrated circuit, 10
3, 203 is a control terminal, 104 is a high voltage system +
side power supply terminal, 105 is the + side power supply terminal of the low voltage system, 106
, 206 is the ground level, 107.207 is the high voltage output circuit, 108.208 is the low voltage output circuit, 1
09° 209 is a level shifter, 204 is a high voltage system one side power supply terminal, and 205 is a low voltage system one side power supply terminal.

Claims (1)

【特許請求の範囲】[Claims] 複数の集積回路間のインターフェイスを行なう双方向性
インターフェイス回路において、第1の電圧振幅系の集
積回路に入力、もしくは出力する第1の入出力端子に出
力が接続されレベル変換されたデータを外部より入力さ
れたコントロール信号に従って出力する第1の出力回路
と、前記第1の電圧系より低い第2の電圧振幅系の集積
回路に入力もしくは出力する第2の入出力端子に出力が
接続され前記第1の入出力端子より入力されたデータを
前記コントロール信号に従って出力する第2の出力回路
と、前記第2の入出力端子に接続され前記第2の電圧振
幅系の集積回路より入力されたデータをレベル変換し前
記第1の出力回路に入力するレベルシフタとを含み、前
記コントロール信号に従って前記第1および第2の出力
回路の出力状態を切り換え、異電圧系集積回路間の論理
インターフェイスを行なうことを特徴とする双方向性イ
ンターフェイス回路。
In a bidirectional interface circuit that interfaces between multiple integrated circuits, the output is connected to a first input/output terminal that inputs or outputs to a first voltage amplitude system integrated circuit, and level-converted data is input from the outside. The output is connected to a first output circuit that outputs according to an input control signal, and a second input/output terminal that inputs or outputs to an integrated circuit of a second voltage amplitude system lower than the first voltage system. a second output circuit that outputs data input from the first input/output terminal in accordance with the control signal; and a second output circuit that outputs data input from the second voltage amplitude system integrated circuit connected to the second input/output terminal. and a level shifter that performs level conversion and inputs the level to the first output circuit, and switches the output states of the first and second output circuits according to the control signal to provide a logical interface between different voltage system integrated circuits. bidirectional interface circuit.
JP62043351A 1987-02-25 1987-02-25 Bidirectional interface circuit Pending JPS63209218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62043351A JPS63209218A (en) 1987-02-25 1987-02-25 Bidirectional interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62043351A JPS63209218A (en) 1987-02-25 1987-02-25 Bidirectional interface circuit

Publications (1)

Publication Number Publication Date
JPS63209218A true JPS63209218A (en) 1988-08-30

Family

ID=12661429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62043351A Pending JPS63209218A (en) 1987-02-25 1987-02-25 Bidirectional interface circuit

Country Status (1)

Country Link
JP (1) JPS63209218A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100963A (en) * 2004-09-28 2006-04-13 Mitsumi Electric Co Ltd Transmission/reception circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123259A (en) * 1973-03-28 1974-11-26
JPS49127558A (en) * 1973-04-06 1974-12-06
JPS59225422A (en) * 1983-06-03 1984-12-18 Toshiba Corp Bidirectional bus buffer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123259A (en) * 1973-03-28 1974-11-26
JPS49127558A (en) * 1973-04-06 1974-12-06
JPS59225422A (en) * 1983-06-03 1984-12-18 Toshiba Corp Bidirectional bus buffer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100963A (en) * 2004-09-28 2006-04-13 Mitsumi Electric Co Ltd Transmission/reception circuit

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