JPS63209212A - Latch driver circuit - Google Patents

Abstract

PURPOSE:To determine a prescribed output signal level at an output buffer circuit as a high speed by setting initially the output of an initial condition recovering output means to a level to be able to give an output signal level which needs the early determination and latching the output signal to a latch means. CONSTITUTION:In response to the non-output timing of data due to an output buffer circuit DOBUFF, the output of an initial condition recovering output means IMO is initially set to a level to be able to give an output signal level to need the early determination of the output level for the output buffer circuit DOBUFF. By latching the output signal of the initial condition recovering output means IMO to a latch means LAT, the initial condition recovering output means IMO is controlled so as to adopt the output condition of the level in response to the input signal level. At this time, the output signal level obtained in response to the output timing of the output buffer circuit DOBUFF is made into the level to need first the early determination of the output level. Thus, the delaying of a desired output signal level determining timing in the output buffer circuit DOBUFF is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to signal output technology and early determination technology for output signal levels. It's about technology.

[Prior art]

A signal line for propagating the output data is coupled to the output terminal of the output buffer circuit, and other circuit elements (semiconductor devices) are coupled to the signal line. Such signal lines and circuit elements become undesirable capacitance and resistance components for the output buffer circuit, and constitute a non-negligible load for the output of the output buffer circuit. Such a load causes the output buffer circuit to delay the determination of its output, especially the determination of a high level output.

As a means to reduce the output determination delay in such an output buffer circuit, for example, the data line balancing technique described in the rLSI Handbook J P2O3 published by Ohm Co., Ltd. on November 30, 1980, can be applied to It is conceivable to make the complementary output data line for driving the circuit leak at a timing corresponding to the non-output period of data and set it to an intermediate level in advance.

[Problem that the invention seeks to solve]

However, according to the experiments and studies conducted by the inventor, even if a technique is adopted in which the complementary output data line for driving the output buffer circuit is set to an intermediate level in advance as described above, undesired output side load Therefore, it has not been possible to satisfactorily improve the tendency for the output determination timing on the high level side to be delayed than the low level determination timing.

An object of the present invention is to provide a technique that can prevent delays in determining the desired output signal level in an output circuit.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the first level of the reset signal takes the output state at a level corresponding to the input signal level, and the second level of the reset signal forces the output signal level to a predetermined level regardless of the input signal level. The device includes initial state recovery output means that takes an output state, and latch means that latches the output signal of the initial state recovery output means, and the output terminal of the latch means is coupled to the input terminal of the output buffer circuit.

[For production]

According to the above means, it is possible to provide the output of the initial state recovery output means in response to the non-output timing of data by the output buffer circuit to an output signal level that requires early determination of the output level for the output buffer circuit. By latching the output signal of the initial state recovery output means in the latch means, the initial state recovery output means can take an output state at a level corresponding to the input signal level. When controlled, the output signal level obtained in response to the output timing of the output buffer circuit is first set to a level that requires early determination of the output level, thereby determining the desired output signal level in the output buffer circuit. This is to prevent timing delays.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of a latch driver circuit according to the present invention. The latch driver circuit LATD shown in FIG. 1 is applied to a data output buffer circuit DOBUFF of an SRAM (static random access memory), although it is not particularly limited thereto.

The data output buffer circuit DOBUFF has a power supply terminal Vd
It has a pair of N-channel type output MO8FETQI and Q2 connected in series between d and the ground terminal of the circuit as its output stage, and a coupling node of the pair of output MO8FETQI and Q2 is the data output buffer circuit DOBUF.
It is assumed that the output terminal of F is Dout. Output MO8FETQI
Amplifying inverter circuits INVI and INV2 are coupled to the respective gate electrodes of Q2 and Q2, and input terminals of the inverter circuits INVI and INV2 are coupled to each other.
Two-person type Nant gate circuit NANDI and NAND
2 are combined. A data output control signal φdoc is supplied to one input terminal of each of the NAND gate circuits NAND1 and NAND2. Data output control signal φdOC
When is brought to low level, a pair of output MO8FETs always
Q1 and Q2 are turned off, thereby placing the output buffer circuit DOBUFF in a high output impedance state. Actually, it is a data output terminal.

ut is commonly connected to an input terminal of a data input buffer circuit (not shown), and when the data output control signal φdoc is set to a low level, write data is allowed to be input from the data input buffer circuit. When the data output control signal φdoc is set to a high level, the outputs of the NAND gate circuits NAND1 and NAND2 are changed according to the signal level supplied to the other input terminal of each of them. Circuit NA
By supplying complementary level signals to ND1 and NAND2 from the latch driver circuit LATD, the details of which will be explained later, the pair of outputs MO8FETQI- and Q2
are switched in a complementary manner, and the output terminal D o u
At t, a high level or low level signal can be obtained.

The latch driver circuit LATD has an input terminal SR
A pair of data output lines DOL and DO are supplied with complementary level data read from a memory cell (not shown) of the AM and amplified by a sense amplifier via a common data line.
It is connected to L.

When reading data, a pair of data output lines DOL,
DOL is set to a complementary level in response to the read data level, but when the previous and subsequent read data levels are different, the data output line (D
It is necessary to invert the potential difference between OL and DOL by reading the next data. Such a data output line (DOL.

In order to shorten the time required to invert the level of DOL, the pair of data output lines DOL and DOL are coupled to the source/drain electrodes of the P-channel type MO8FETQ3. The gate electrode of the leak MO8FET Q3 is supplied with a precharge control signal φp that is set to a low level in response to a predetermined timing before the start of a memory read operation. As a result, the leakage MO3F is turned on almost at the same timing as the precharging operation of the complementary data line and the complementary common data line (not shown).
Due to the action of ETQ3, the pair of data output lines DOL and DOL are balanced to an intermediate level.

The latch driver circuit LATD includes a two-man type NOR gate circuit N0RI, one input terminal of which is coupled to the data output line DOL via an N-channel cutoff MO8FETQ4 whose gate electrode is supplied with the precharge control signal φp; N-channel cutoff MO8FE whose gate electrode is supplied with the precharge control signal φP
A two-man type NAND gate circuit NAND3 with one input terminal connected to the data output line DOL via TQ5.
and has. The other input terminal of the NOR gate circuit N0RI is supplied with the address change detection signal φa 1; d, and the other input terminal of the NAND gate circuit NAND3 is supplied with an inverted level signal of the address change detection signal φa t, d. is supplied. The above NOR gate circuit N0R
In response to the low level (first level) of the address change detection signal φatd as a reset signal, the NAND gate circuit NAND3 adopts an output state at a level corresponding to the input signal level supplied from the data output lines DOL and DOL. The high level (second level) of the address change detection signal φatd causes the output signal level to be set to a predetermined level (NOR gate circuit N0R) regardless of the input signal level supplied from the data output lines DOL and DOL.
The output level of I is set to low level, and the Nant gate circuit N
This is an initial state recovery output means IOM that forces the output level of AND3 to a high level to take an initial output state.

The address change detection signal φatd is, although not particularly limited, a signal formed by an address signal change detection circuit (not shown) that detects changes in an external address signal supplied to the SRAM and forms various internal timing signals. , is kept at a high level for a predetermined period in response to a change in the level of the address signal in the SRAM chip selection state.

The above NOR gate circuit N0RI and NAND gate circuit NA
Inverter circuits INV3 and INV4 are coupled to the output terminal of ND3, respectively.
and INV4 configure a latch circuit LAT by cross-coupling their respective input and output terminals. The output terminal of the inverter circuit INv3 is coupled to one input terminal of the NAND1 gate circuit NAND1, and the output terminal of the inverter circuit IN'V4 is coupled to one input terminal of the NAND2 gate circuit NAND2. .

Next, the operation of the latch driver circuit LATD will be explained with reference to the time chart shown in FIG.

When an address signal for a memory read operation is supplied to the SRAM, an address signal change detection circuit (not shown) that detects it detects it at time t at a predetermined timing with respect to the address signal detection timing. At the same time, the precharge control signal φp is changed to low level, and the address change detection signal φatd is changed to high level.

Then, the leak MO8FET Q3 is turned on and the pair of data output lines DOL and DOL are precharged to an intermediate level, while the latch driver circuit LATD is turned off at that time.
A pair of data output lines DOL are connected by FETs Q4 and Q5.
, electrically isolated from DOL. At this time, the initial state recovery output means IOM to which the high level address change detection signal φatd is supplied forces the output level of the NOR gate circuit N0RI side to a low level and the output level of the NAND gate circuit NAND3 side to a high level. hand,
Takes the initial output state. The latch circuit LAT thereby latches its output state. The output state latched by the latch circuit LAT is the data output buffer circuit DOBU.
This is a signal state sufficient to obtain a high level output at the data output terminal Dout of the FF.

Then, at time t□, which is a predetermined timing before the output data lines DOL and DOL are forced to start level due to the memory read operation, the precharge control signal φ
P is inverted to high level and leak MO8FETQ3
is changed to the off state, and the cutoff MO8FET
Q4 and Q5 are turned on. Next, at time t2, which is substantially synchronized with the data output timing at which the data output control signal φdoc is set to high level, the address change detection signal φatd is changed to low level. At this time, the latch circuit LAT has the data output terminal D of the data output buffer circuit DOBUFF.
Since data sufficient to obtain a high level output is latched in advance at the data output terminal Dout, high level data is instantly obtained at the data output terminal Dout regardless of the level of the read data, and the read data at that time is If the level is low, the low level read data is latched in the latch circuit LAT, and then the data output terminal D is output.
out is set to low level.

Therefore, the signal lines and circuit elements coupled to the data output terminal Dout are connected to the data output buffer circuit DOBUF.
Even if an undesirable capacitive component and a resistive component are formed on F, resulting in a non-negligible load, the data output buffer circuit DOBUFF can quickly determine the output of high-level data without causing any delay. Can be done. The determination of the output of low level data is delayed compared to the determination of the output of high level data, but the delay time is small and substantial due to the nature of changing the high level data output terminal Dout to the low level via MO8FETQ2. is not a problem.

According to the above embodiment, the following effects can be obtained.

(1) Before the output of memory read data starts, by the reset operation of the initial state recovery output means IOM, the latch circuit LAT has sufficient data to obtain a high level output to the data output terminal Dout of the data output buffer circuit DOBUFF. is latched in advance, so at the start of outputting memory read data, the corresponding data output terminal D
Since high-level data can be obtained instantly regardless of the read data level, the data output terminal D
Even if the signal line or circuit element coupled to out constitutes an undesirable capacitance component and resistance component for the data output buffer circuit DOBUFF and becomes a non-negligible load, the data output buffer circuit DOBUFF will not be affected in any way. It is possible to quickly determine the output of high-level data without causing any delay.

(2) From the above effects, at the start of outputting memory read data, the data output terminal Dout has:
If high level data is instantaneously obtained regardless of the read data level and the read data at that time is low level, the low level read data is latched in the latch circuit LAT, and then the data output terminal Do
Since ut is set to low level, the circuit configuration of SRAM.

It is only necessary to consider ways to improve the read access of low-level data, thereby making it possible to simplify each component circuit.

Although the invention made by the present inventor has been specifically described above based on Examples, the present invention is not limited to the above-mentioned Examples, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, the address change detection signal φa t,
d is used, but the control signal is not limited thereto and can be changed to various other control signals. In addition, in the above embodiment, the cutoff MO8FETs Q4 and Q5 are set in consideration of preventing the reset operation from becoming unstable due to the input signal of the initial state recovery output means IOM becoming an intermediate level during the precharge period. Although such a cutoff element is provided, it is not always necessary to provide such a cutoff element.In addition, in the above embodiment, the data reset to the latch driver circuit LATD is transferred to the output buffer circuit DOBUFF for high level data output. Although it was data,
The above latch driver circuit L is used in a signal output circuit such as an output buffer circuit that requires early determination of low level data.
When applying ATD, NOR gate circuit N0
The connection positions of R1 and the NAND gate circuit NAND3 may be exchanged. Further, the specific circuit configuration of the initial state recovery output means IOM is not limited to the combination of the NOR gate circuit and the Nant gate circuit of the above embodiment, but can be modified in various ways.

In the above description, the invention made by the present inventor was mainly applied to a data output buffer circuit in SRAM, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and can be applied to other applications. It can be applied to various semiconductor integrated circuits such as semiconductor memory devices and output circuits. The present invention can be applied to at least conditions that require early determination of the output level in a signal output circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, the first level of the reset signal takes the output state at a level corresponding to the input signal level, and the second level of the reset signal forces the output signal level to a predetermined level regardless of the input signal level. The output is provided with an initial state recovery output means that takes an output state and a latch means that latches the output signal of the initial state recovery output means, and the output terminal of the latch means is coupled to the input terminal of the output cover sofa circuit. In response to the non-output timing of data by the cover sofa circuit, the output of the initial state recovery output means is initially set to a level that can provide an output signal level that requires early determination of the output level for the output buffer circuit. , when the output signal of the initial state recovery output means is latched by the latch means, the output buffer is controlled so that the initial state recovery output means can take an output state at a level corresponding to the input signal level. The output signal level obtained in response to the output timing of the circuit is first set to a level that requires early determination of the output level, thereby making it possible to quickly determine the desired output signal level in the output buffer circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the latch driver circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation of the latch driver circuit. LATD...Latch driver circuit, DOBUFF...
・Data output buffer circuit, Work○M...Initial state recovery output means, LAT...Latch circuit, D out...
...Data output terminal, Q4 and Q5...Cutoff M
O8FET, φatd...address change detection signal, φ
doc...Data output control signal.

Claims (1)

[Claims] 1. The first level of the reset signal takes an output state corresponding to the input signal level, and the second level of the reset signal sets the output signal level to a predetermined level regardless of the input signal level. What is claimed is: 1. A latch driver circuit comprising: initial state recovery output means for forcing an initial output state to a certain level; and latch means for latching an output signal of the initial state recovery output means. 2. The initial state recovery output means is supplied with data read from the memory cell of the semiconductor memory device and amplified by the sense amplifier, and the latch means is supplied with the data read from the memory cell of the semiconductor memory device and amplified by the sense amplifier, and the latch means is supplied with the input terminal of the data output buffer circuit of the semiconductor memory device. 2. The latch driver circuit according to claim 1, wherein the latch driver circuit is coupled to a latch driver circuit. 3. The latch driver circuit according to claim 2, wherein the initial state recovery output means takes an initial output state that can control the output level of the output buffer circuit to a high level.