JPS63209171A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS63209171A
JPS63209171A JP4135587A JP4135587A JPS63209171A JP S63209171 A JPS63209171 A JP S63209171A JP 4135587 A JP4135587 A JP 4135587A JP 4135587 A JP4135587 A JP 4135587A JP S63209171 A JPS63209171 A JP S63209171A
Authority
JP
Japan
Prior art keywords
patterns
sides
type emitter
anode
cathode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4135587A
Other languages
Japanese (ja)
Inventor
Takashi Shinohe
孝 四戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4135587A priority Critical patent/JPS63209171A/en
Publication of JPS63209171A publication Critical patent/JPS63209171A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H01L29/745—Gate-turn-off devices with turn-off by field effect
    • H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure

Abstract

PURPOSE:To form a semiconductor element bearing high element characteristics in stable yield even if the alignment accuracy of both sides is unfavorable by a method wherein rectangular patterns are used to arrange both side patterns orthogonally to each other. CONSTITUTION:Striped p type emitter layers 1 are arranged to be orthogonal to striped patterns on a cathode 8 side. Thus, the p type emitter layers 1 are formed evenly in the direction (x direction) orthogonal to the striped patterns on the cathode 8 side. Through these procedures, one side channel shall not be supplied with more current during turn off process even if the alignment accuracy of both sides is unfavorable to increase the anode current to be turned off.

Description

【発明の詳細な説明】 （竜梁上の利用分野） ′＄宅明は半導体橋体の両面にパターンが形状されてな
る半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Application of Longliang) '$Takumei relates to a semiconductor element having a pattern formed on both sides of a semiconductor bridge body.

（従来の技術） 半４本基本の両面にパターンが形成され１なる半！Ｊ本
素子の列としてアノードショート部ａを用いた絶縁ゲー
ト盟自己ターンオフサイリスタ（以下、Ｍ（ＪＳＧＴ（
Ｊ）を取り上げて説明する。(Conventional technology) Patterns are formed on both sides of the basic 4-half pattern, making it 1 half! Insulated gate self-turn-off thyristor (hereinafter referred to as M (JSGT)) using anode short part a as a row of J elements
Let us take up and explain J).

＠　２　＋４　（ａ）はｐチャネル４３１　Ｍ　（Ｊ　
Ｓ　Ｇ　’Ｉ’　Ｕの素子構造を示す子面図であジ、同
図（ｂ）はｆａ）のＡ−Ａ’断面図である。ｐ型エミッ
タ１６１．ｎａベースｌ１１２．ｐをベース９３および
ｎｔｌｌエミッタ１１４によりてｐｎｐｎ構造を形成し
ており、ｐ型エミッタ１１２、ｆｉ　沢拡￥１杉成する
′ことによりてアノードショート部５を設けている。ｐ
型エミッタ１】およびアノードショート部５にはアノー
ド電極７が、ｎをエミッタ１４にはカソード′４極８が
それぞれ形成さ几ている。また、この従来列では、この
ナイリスタをターンオフさせるｔめにｐチャネルａＭＯ
８ＦｇＴをモノリシックに形成している。すなわち、ｐ
型ベース１３と１口をエミツタ層４の中に拡散形成され
たｐ　層重６との間に挟りｎ、、ｉｎ型エミッタ層４の
挽面をチャネル領域として、この上にゲート他縁膜９を
介しエデートＫＬ極１０を形成してターンオフ用ｐチャ
ネル型Ｍｕ８ＦｇＴを構成している。１１はゲート電極
１０とカソード成極８を絶縁する絶縁膜である。カソー
ド成極８叫のパターンとアノード４極７側のパターンは
ストライプ形状で互いに千行になるように配置されてい
る。@ 2 + 4 (a) is p channel 431 M (J
FIG. 2 is a side view showing the element structure of S G 'I'U; FIG. p-type emitter 161. na base l112. A pnpn structure is formed by the p type base 93 and the ntll emitter 114, and the anode short portion 5 is provided by forming the p type emitter 112 and the fi type emitter 112. p
An anode electrode 7 is formed on the type emitter 1 and the anode short portion 5, and a cathode 4 is formed on the emitter 14, respectively. Also, in this conventional array, in order to turn off this Nyristor, the p-channel aMO
8FgT is formed monolithically. That is, p
The mold base 13 and one opening are sandwiched between the p-layer layer 6 which is diffused into the emitter layer 4, and the ground surface of the in-type emitter layer 4 is used as a channel region, and a gate and other edge films are formed on this. An edited KL pole 10 is formed through the electrode 9 to constitute a turn-off p-channel type Mu8FgT. Reference numeral 11 denotes an insulating film that insulates the gate electrode 10 and the cathode electrode 8 . The pattern of the 8 cathode poles and the pattern of the 4 anode poles 7 are arranged in stripe shapes in 1,000 rows from each other.

このＭ　ＯＳ　Ｇ　’Ｉ’　０のゲートターンオフは次
のようにして行なわれる。いま、ＭｕＳＧＴＯが導通状
態にある時、ゲート電極１０　ＶｃＭＯ８ＦＥＴのしき
い直′１圧以上の負電圧を印７ＪＯするとＭＯＳＦＥＴ
が導、山する。この時、アノード電流の一部は、このＭ
Ｕ　８　Ｆ　ｇＴをｊりて流れ、カソード’を極８から
外部に排出される。アノード電流の通常の経路、すなわ
ち、ｐ啜ベース１傍３からエミッタ饗会を＋想ってｎ型
エミクダ轡４に流れる径幅では、約０．８　Ｖの電圧降
下が生じるので、ＭＯＳＦＥＴを通る経絡の抵抗が十分
に小さくその電圧降下がＯ，Ｓ　Ｖよりも小さい′ＪＪ
Ｊ会には、アノード４流の大部分がＭＵ８−ＦＥＴを４
る経路を＾りてカンード鑞極８に流れ込む。この結果、
ｎ型エミッタ嗜４から注入される成子の量が城少し、Ｍ
ｕＳＧＴＯは導通状恨を保てなくなり、非導通状態へ移
行する。This gate turn-off of MOS G'I'0 is performed as follows. Now, when MuSGTO is in a conductive state, if a negative voltage of 1 voltage or more is applied to the gate electrode 10VcMO8FET's threshold voltage 7JO, the MOSFET
Leads and climbs. At this time, part of the anode current is
It flows through the U 8 F gT and the cathode' is discharged to the outside from the pole 8. In the normal path of the anode current, that is, the diameter width where it flows from the p-type base 1 side 3 to the emitter plate 4 to the n-type emitter 4, a voltage drop of about 0.8 V occurs, so the meridian passing through the MOSFET resistance is sufficiently small and its voltage drop is smaller than O,SV'JJ
In J-kai, most of the anode 4 types use MU8-FET 4.
The water flows through the path that flows into Cando Rizukoku 8. As a result,
The amount of Naruko injected from the n-type emitter 4 is a little small, M
The uSGTO is no longer able to maintain continuity and transitions to a non-conduction state.

Ｍ（ＪＳＧＴ（Ｊのターンオフ時間を短くする之めに＠
２図に示し九従米列ではアノードショート構造を採用し
ている。このアノードショート構造はｐ型エミッタ１１
１を選択拡散することによりＦｆ４）Ｅするｔめ半４本
累子両面のパターンの位置会わせ作業が必要になる。こ
の際、両面の位置会わせずれ△Ｘの分だけパターンが午
行移切したとするとｎ型エミッタ！４４の下に流れるア
ノード４流は左側の方が多くなる。このようなＭｕＳＧ
ＴＯをターンオフしようとするとＣＨ，を流れるアノー
ド電流の方がＣＨｌを流れるアノード′１ｔＩ５１！よ
りも多くなりてしまりので、Ｃｋ−１，の電圧降下が大
きくな几ばＣＨｌの電圧降下が小さくてもＭｕＳＧＴＯ
はターンオフ時間することになる。このように両面のス
トライフハターンを平行に配置し九従来のＭｕＳＧＴＯ
では、両面の位！を汁わせ精度の分だけパターンが相互
にずれることになり、その結果、ターンオフできるアノ
ード１ｔ０１が小さいという間４がありた。M(JSGT(To shorten the turn-off time of J＠
The anode short structure is adopted in the nine-column array shown in Figure 2. This anode short structure has a p-type emitter 11
By selectively diffusing Ff4)E, it is necessary to align the patterns on both sides of the t-th half of the 4-piece transceiver. At this time, if the pattern is shifted in the meridional direction by the amount of misalignment △X on both sides, then it is an n-type emitter! The amount of anode 4 flowing below 44 is greater on the left side. MuSG like this
When an attempt is made to turn off TO, the anode current flowing through CH is higher than the anode current flowing through CHl! Therefore, if the voltage drop of Ck-1 is large, even if the voltage drop of CHl is small, MuSGTO
will be the turn-off time. In this way, by arranging the strife patterns on both sides in parallel, nine conventional MuSGTO
Now, on both sides! As a result, the anodes 1t01 that can be turned off are small.

（比例が解決しようとする間゛４点） 以上のように、両面のストライプパターンを互いに平行
に配置した従来の半４体素子では、両面の泣１置曾υせ
積度が悪いと素子特性が低下するという間遣があう之。(While the proportionality is about to be resolved (4 points)) As mentioned above, in the conventional half-quad element in which the stripe patterns on both sides are arranged parallel to each other, if the density of the two sides is poor, the element characteristics will change. There is a chance that the amount will decrease.

本沌明は両面の位！［廿わせ精度が悪くても素子特注が
低下しないようなパターンの配置を改良した半導体素子
を提供することを目的とする。The real chaos is both sides! [An object of the present invention is to provide a semiconductor device with an improved pattern arrangement so that the customization of the device does not deteriorate even if the alignment accuracy is poor.

〔発明のＳ４成〕 （問題点を解決する之めの手段） 本発明にかかる半導体素子は、半導体基体の両面に形成
されるパターンをほぼ矩形状とし、両面のパターンを互
いに直交して配置することを特徴とする。[S4 of the invention] (Means for solving the problem) In the semiconductor element according to the present invention, the patterns formed on both sides of the semiconductor substrate are approximately rectangular, and the patterns on both sides are arranged orthogonally to each other. It is characterized by

（作用） 本発明の半導体素子では、両面の矩形状パターンを互い
に直交して配（蔵しているので、たとえ両面の位置会わ
せ精度が悪くても、パターンずれは問題にならず、χ子
持性の低下は起こらない。(Function) In the semiconductor device of the present invention, the rectangular patterns on both sides are arranged orthogonally to each other, so even if the alignment accuracy of both sides is poor, pattern misalignment will not be a problem and the chi No reduction in sex occurs.

（央ｌ泡ｌｖｌり 以下本発明のχ施列を、従来列と同じアノードショート
構造を用いたＭｏｌＧＴＯについて説明する。(Central foam lvl) The χ array of the present invention will be described below for MolGTO using the same anode short structure as the conventional array.

第１図１ａ）は実施列の素子１４造を示す午面図であり
、同図（ｂ）　、　（Ｃ）はそれぞ’ｎ（ａ）ノＡ　−
Ａ’　、　Ｂ　−８’断面図である。従来列として示し
次第２図と対応する部分は同じ符号を符して詳細な説明
は省く。この実施列では、ストライプ状のｐ型エミッタ
９１をカソード？［極８１ＱＩｌのストライプ状パター
ンと直交するように配置している。この実Ｍ！Ａ列によ
れば。1a) is a mercurial view showing the 14 elements of the practical row, and FIG. 1(b) and (C) are respectively
A', B-8' sectional view. As long as it is shown as a conventional column, parts corresponding to those in FIG. In this implementation row, the striped p-type emitter 91 is used as a cathode? [Pole 81 is arranged perpendicular to the striped pattern of QIl. This fruit M! According to column A.

カソード４極８利のストライプ状パターンと直交する方
向（Ｘ方向）Ｋ関しては、ｐ型エミッタ層１は均一に形
成されているので、九とえ両面の位１准廿わせ指度が悪
くでも、ターンオフの際に片方のチャネルに１ａが多く
流れるようなことはなく。Regarding the direction (X direction) perpendicular to the cathode 4-pole 8-pole striped pattern, since the p-type emitter layer 1 is uniformly formed, the alignment index on both sides is poor. However, at turn-off, there is no case where a large amount of 1a flows into one channel.

ターンオフできるアノードを流は大きなものになる。With an anode that can be turned off, the current will be large.

本発明は上記した実施列に限られるものではない。列え
ば、アノード゛Ｉｔ　１１７　＋Ｕｌの工面に通常のア
ノードショート構造の代りにｎチャネル型ＭＯ８−ＦＥ
Ｔを用いてセＩＪ−可能なアノードショート構造として
もよいし、本体素子がＭｕｌＧＴｏ以外の列えばＭ（Ｊ
Ｓサイリスタやゲートターンオフナイリスタ、トランジ
スタ、ＭＵ８１”ＷＴ、バイポーラ截Ｍ（ＪＳＩ：Ｔ等
の矩形状パターンを用いる半導体素子であって％本発明
を１遁用して安定し九歩留りで高い素子特性を実現する
ことができる。The invention is not limited to the embodiments described above. For example, instead of the usual anode short structure, an n-channel type MO8-FE is installed on the surface of the anode It 117 +Ul.
It is also possible to use T to create an anode short structure that is possible to set IJ, or if the main body elements are arranged in a row other than MulGTo, M(J
S thyristors, gate turn-off Nyristors, transistors, MU81" WT, bipolar cut M (JSI: T, etc.) semiconductor devices that use rectangular patterns, and which are stable and have high device characteristics with a yield of 9% by using the present invention. can be realized.

〔清明の幼果〕[Young fruit of Seimei]

以上述べたように本色間によれば、矩形状のパターンを
用いて両面のパターンを互いＩＣ直交して配置すること
により、ｔとえ両面の位僅合わせ精度が悪くても安定し
た歩留りで高い素子特性を持つ半導体素子を実現するこ
とができる。As mentioned above, according to Honshikima, by using rectangular patterns and arranging the patterns on both sides perpendicular to each other, a stable and high yield can be achieved even if the alignment accuracy of both sides is poor. A semiconductor device having device characteristics can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

＠１図は′＄伯清明央権列のＭｏ　８　ＧＴ　Ｏを示す
子面図とそのＡ−Ａ’、Ｂ−Ｂ’断面図、第２図ツメ、
ｌは従来列のＭ（ＪＳＧＴＯを示す千面図とその人−Ａ
’、ｆｒ面図である。 １・・・ｐ型エミクタ層、２・・・ｎ型ベース層、３・
・・ｎ型ベース層、４・・・ｎ型エミッタ看、５・・・
アノ−トンヨード部、６・・・ｐ　戚慢、７・・・アノ
ード電極。 ８・・・カソード電極、９・・・ゲート絶縁膜、１０・
・・ゲート絶縁膜、１１・・・絶縁膜。 代理人　弁理士　　則　近　廠　右 同　　　　　　　　竹　　花　　喜久男第　　１　　図 第　　１　　図 （ａ） 第　　２　図@ Figure 1 is a small side view showing the Mo 8 GT O of the Boqing Ming central government series, its A-A' and B-B' cross-sectional views, and Figure 2's tabs.
l is the conventional column M (thousand-sided map showing JSGTO and its person-A
', fr side view. 1...p-type emitter layer, 2...n-type base layer, 3...
... n-type base layer, 4... n-type emitter layer, 5...
Anoton iodine moiety, 6...p arrogance, 7... anode electrode. 8... Cathode electrode, 9... Gate insulating film, 10.
...Gate insulating film, 11... Insulating film. Agent Patent Attorney Noriyuki Kikuo Takehana Figure 1 Figure 1 (a) Figure 2

Claims (1)

【特許請求の範囲】[Claims] 半導体基体の両面にパターンが形成されてなる半導体素
子において、パターンはほぼ矩形状であり、両面のパタ
ーンは互いに直交して配置されることを特徴とする半導
体素子。1. A semiconductor device in which patterns are formed on both sides of a semiconductor substrate, wherein the patterns are substantially rectangular, and the patterns on both sides are arranged orthogonally to each other.
JP4135587A 1987-02-26 1987-02-26 Semiconductor element Pending JPS63209171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4135587A JPS63209171A (en) 1987-02-26 1987-02-26 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4135587A JPS63209171A (en) 1987-02-26 1987-02-26 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS63209171A true JPS63209171A (en) 1988-08-30

Family

ID=12606186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4135587A Pending JPS63209171A (en) 1987-02-26 1987-02-26 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS63209171A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03136372A (en) * 1989-10-23 1991-06-11 Fuji Electric Co Ltd Mos control thyristor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03136372A (en) * 1989-10-23 1991-06-11 Fuji Electric Co Ltd Mos control thyristor

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