JPS6320800A - Semiconductor memory - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to error detection and correction of information stored in a semi-consolidated memory.

[Conventional technology]

With advances in semiconductor technology, particularly in the field of semiconductor memory, the degree of integration of chips has increased and their chip structures have become more complex. As a result, dimensional constraints have become more severe, and related problems have arisen in the manufacturing process, resulting in problems such as malfunction of bit cells in the array. The pathology of these malfunctions is often "column" related (as opposed to "row") related malfunctions resulting in column defects in the play's bit cells. However, even if a single bit failure occurs in a large capacity memory array, for example a memory array with 64,000 memory cells, the entire device will fail.
It turns out to be a big deal.

In order to increase the yield in semiconductor memory arrays, redundancy schemes and error detection/correction schemes are used. Among these, the point redundancy method is particularly suitable for a circuit having a repetitive structure such as a memory array in which a part of the circuit, for example, a memory cell column appears repeatedly on a chip. In this system, when checking for the error, it is sufficient to open a Rade type fuse and insert a redundancy circuit in place of the defective circuit, or to perform a similar complete replacement with the electronic switching interface active. The above-mentioned redundancy circuit is described in, for example, U.S. Patent Application No. 4,471,472.
An example of this is shown in No. 1, Texas Instruments, Inc., all assignees. However, the redundancy circuit requires a certain area of the silicon surface, i.e., the "overhead area", to be specifically reserved for this purpose, and the redundancy circuit is not only activated only at the manufacturing stage, but is also It is necessary to keep the redundancy within the range of the redundancy circuit.
Partial redundancy is sufficient for read-write memories, but full redundancy is required for read-only memories (ROM).

A second approach to increasing yield in highly integrated semiconductor memory arrays uses error detection and correction codes. This type of code usually has two types of digits,
That is, it includes information or message digits, check or parity digits, and money. However, since the probability of an error occurring is much lower when 24F1 or more errors occur simultaneously than when an error occurs alone, much attention is focused on detecting and correcting 1-bit errors. In order to obtain an error detection/correction code, it is necessary not only to store all of the information digital digits, but also to store parity information corresponding to each of these information digits. The most widely used code for detecting single errors is the odd/even parity code, in which every code word has one parity bit. is added.

In order to perform a parity check using the odd/even method, select all the relevant additional bits so that the sum of all logic 1s including this parity bit is either an odd number or an even number. I'll keep it.

This all-8/even parity error detection code requires an additional <Kl bit for this purpose and is referred to as a "horizontal" parity check method. However, in such horizontal parity checking schemes, if a relatively long message is arranged in an array of 1 row and m columns, in addition to the n horizontal parity bits added to each row, an additional "vertical" parity bit is added to each column. □ May be added. This type of code is called a block parity error correction code, and in this case, errors can be detected from either the horizontal or vertical parity bits. It is.

The sixth type of error detection code is called a norming code, and is one of the more important codes for detecting and correcting all single errors in this code. According to this Hamming code, it is possible to detect not only the above-mentioned single error but also multiple errors, and devices with such codes can be developed as devices with external semiconductor memory. has been done. In this type of device, the data word output from the memory, together with the parity information also output from the memory, is input to an error detection/correction circuit to detect whether an error is present.

If an error exists, the error is corrected and a corrected data word is output from the circuit. Examples of such error detection/correction circuits include those commercially available from American Microdevices (product number,
/162960) Gaji, Mano, and other application examples of error detection/correction codes include, for example, U.S. Patent No. 4.47.
No. 9,214, No. 4,494,234, No. 4.497
, No. 058, No. 4,498.175, Wu 4.506,
There are descriptions thereof in No. 365, No. 4,468,769, etc.

[Means for solving the problem] 7D) Is the present invention a semiconductor memory with integrated error detection and correction functions? This semiconductor memo IJ i provides
First, a first memory array is read which stores a plurality of digital data words arranged in sets as collective data words. Each of these generic data words consists of a predetermined number of digital data words.

Check bits for the global data word are stored in a second memory array, and these check bits are generated according to a block error detection/correction code algorithm. In this case, the number of check bits generated is a function of the bit number in the generic data word.

More address decoders? is provided, thereby receiving an external address and fully decoding the address to access and output the global data word and its associated check bits. Further, an error detection/correction code is provided, whereby the accessed sentence generic data words and the total amount of check bits associated with these data words are taken to determine whether an error exists in the generic data word A. , if an error exists, VC corrects that error within the global data word. One of the selected length data words within the corrected global data word is selected for output therefrom.

In one embodiment of the semiconductor memory configured in this manner, the block error detection/correction algorithm is entirely composed of Hamming codes. The generic data word and its associated check bits are combined into a coded data word, with the check bits being arranged in predetermined positions within the word according to the Hamming code. in this case,
Furthermore, the syndrome generator in general generates an error syndrome signature containing information regarding the pit locations of errors detected in the global data word. The error syndrome signal is then decoded to generate a plurality of mutually exclusive bit error signals, each corresponding to a pit position in the global data word. This comprehensive data word is then subjected to an exclusive OR function 1c! of each bit and its corresponding bit error signal. If it is indicated that an error exists at the pit position, the bit is inverted.

Then the corrected comprehensive data word? Select all desired data words by inputting them into DemartePunksa.

Furthermore, in another embodiment of the semiconductor memory according to the invention, the data word is first demultiplexed from the uncorrected comprehensive data word, and the bit error signal corresponding to the demultiplexed data word is also demultiplexed. Demultiplex. Thus demultiplexing′:! The demultiplexed data words and their associated bit error signals are routed to the full error correction circuit, thereby reducing the number of lines between the demultiplexing circuit and the error correction circuit.

[Metal practice]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram illustrating a semiconductor memory device incorporating an error detection and correction circuit according to the present invention. The illustrated memories are first located in an information memory array 10 and a parity memory array 12':'! j.

Each of these arrays 10.12 consists of an array of memory elements arranged in rows and columns. These memory elements are kR exclusive memory (ROM).
) or random access memory IJ (RAM). A typical structure of a ROM-type memory is described in U.S. Patent No. 3,934,233, filed by Texas Instruments, Inc., all assignees, and a structure of a RAM-type memory is also described in U.S. Pat. U.S. Patent No. 4.3
No. 47.587 contains seven statements. However, whatever the structure of the memory arrays 10.12, the only important thing about these arrays is that information is extracted from them.

Data is stored in the i-frontal axis memory array 10 in the form of a set of data words combined into a set of comprehensive data words. In this embodiment, four 8-bit data words complete one of the generic data words, each of which is associated with the generic data word and associated with the parity memory array 12. A predetermined number of "check bits" or "parity bits" stored in the

As described below, one of the global data words and its associated parity bit are accessed, error detection is performed, and error correction is then performed if necessary. Thereafter, the desired data word is selected from the corrected data words.

The information memory array 10 is addressed by column addresses and row addresses. A row address is input to a row address decoder 14 or a row address bus 15 to select one of a plurality of word lines represented by a word line bus 16. The outputs of the row address decoder 14 are mutually exclusive, so only one row is selected from the information memory array 10 and the parity memory array 12.

The column address is divided into two parts, one being an output selection address section consisting of lower order address bits, and the other being an array selection address section consisting of higher order address bits. This address selection address section is input to the semiconductor memory via the bus 18t 3 n , and the input selection address section is input to the bus 20 . The array selection address portion of the column address is transmitted to the column address decoder 22 associated with the information memory array 10 and the parity memory array 12.
and the associated column address decoder 24. Column and row addresses are thus generated and associated with the global data words stored in information memory array 10 and associated with these data words and stored in parity memory array 12, which are accessed when the nine bits are accessed. A generic data word is output on data bus 26t-, and each accessed check bit is output on data bus 28.

Both the global data word on data bus 26 and the parity bit on data bus 28 are output to block code error detection circuit 30.

This block code error detection circuit 30 generates all error detection codes according to a predetermined error detection/correction algorithm, so that if there is an error in the accessed data, it can be determined which bit is the error. It is something. The correction code is then output to the error syndrome bus 32 and input to the error correction/selection circuit 34. The error correction/selection circuit 34 also receives the global data word of the data bus 26. An error correction/selection circuit 34 receives the output address portion divided from the column address of the bus 20;
One of the four data words making up each generic data word is selected as described above. Thus, in the present invention, the bit length of the data stored in information memory array 10 is greater than the bit length of a single data word. By doing so, the block code error detection circuit 30 operates with a greater number of lifts of data bits than is required in conventional error correction schemes. As will be discussed below, this approach according to the present invention requires fewer parity bits and therefore reduces the required storage capacity of the variable array 12 accordingly.

In this embodiment, the information memory array 10
assume that the column address decoder 224C accesses a comprehensive data word of bit length t-N of 32 bits as 1024 bits wide, so that each row of the information memory array 10 has 32 62-bit long comprehensive data words. A word will appear. Also associated with each global data word are six check bits in the corresponding parity memory array 12 row. Therefore, parity memory array 12 is divided into 32 groups, each having a total width of 6 bits, and has a total width of 192 bits. Thus, the information data bus 26
is 62 bits wide, and the parity data bus 28 is 6 bits wide.

In this embodiment, the block code error detection circuit 30 uses a single error detection and correction code based on the Hamming method, but it is also possible to use other types of codes such as Reed-Mueller codes and Golay codes. There is no problem.

The error correction code appearing on the error syndrome bus 32 contains information regarding the error in the form of its relative position within the 62-bit global data word accessed and output on the data bus 26. However, as a last resort, it is only necessary to invert the pits of the data containing the error to output the correct data word.

Further, the error correction/selection circuit 34 is a circuit that easily performs such correction and selects a smaller segment of data for output onto the bus 32 according to the output selection address portion of the column address appearing on the bus 20. Thus, it is possible to perform all error correction on a 62-bit data word while outputting a full 16-bit data word, an 8-bit data word, or a 4-bit data word. As will be explained later, the result of this approach is that fewer parity bits can be used for error correction, for example, only six parity bits are required for a 62-bit word. Thus, in the normal case, a total of four parity bits are required for each of four 8-bit data words, as opposed to a total of 16 parity bits.

Next, the structure of the error detection/correction memory shown in FIG. 1 will be explained with full reference to FIG. 2. In the following figures, the same reference numerals as those used in FIG. 1 indicate the same components.

1, the information memory array 10 is such that all bits corresponding to equivalent bit positions in the global data word in each row of memory elements are arranged in adjacent columns 1oa-1o.
It is configured to be arranged in n. That is, the bits in the first position of each of the eight global data words V of, for example, 62 bits each are arranged mutually in columns 10&, and likewise the parity bits 12a--. They are arranged adjacent to each other in columns indicated by 12n.

In the figure, numeral 38 represents all bit lines output from each of the column groups 10 & -1On, and 40 represents bit lines output from each of the column groups 12a-12n of the parity array 12. Bit line 38 above
are input to separate bit line selection circuits 22a-22H provided in the column address decoder 22, and each of the above bit lines 40 is input to the column address decoder 24.
bit line selection circuits 24a-24H. The bit line selected from the bit line selection circuits 2l-22n is connected to the sense amplifier 46 via the line 42t-.
and is input to the bus 26. Similarly, the bit lines selected from the bit line selection circuits 24a-24n are output to the sense amplifier 48 via all lines 44 and input to the bus 28.

As mentioned above, the word length of the words accessed from the information memory array 10 is 32 bits, and the number of parity bits accessed from the parity memory array 12 in conjunction with these bits is 6 bits. . Therefore, the information memory array 10 includes a column group of 32 columns, and the parity memory array 12 includes a column group of 6 columns! This means that As a result, a word output of 62 pins appears on the bus 26, and a word output of 62 pins appears on the bus 28.
A 6-bit word output appears. By configuring the memory array in this way, even if adjacent bits in a row in the array are defective, the adjacent bits in the accessed word will be 62-bit words, or 7 in each row. are physically separated by bits, so that adjacent bits in the accessed word cannot be defective.

In this embodiment, seven Hamming codes are used as an error detection algorithm, but for this purpose, it is necessary to generate all "error syndromes" by the error syndrome generator 50.

The syndrome generator 50 inputs a digital pulse indicating the position tffi of an error within a word to an error position decoding circuit 54 via a bus 52. This decoding circuit 54 outputs a yellow signal indicating the total amount of erroneous υ pits to the full bus 56. In this case, the output of the decoding circuit is generated one by one for each bit of the 32-pit data word, and these outputs have a mutually exclusive relationship (note that this is not adopted in this embodiment, but if desired, For example, all six pits may be output to indicate an error at the parity bit position.Thus, the error position decoding circuit 54 and syndrome generator 50 constitute the block code error detection circuit 30 shown in FIG. be done.

The error correction circuit 34 receives in its input a global data word from the data bus 26 and a bit error location signal from the bus 56. The correction circuit 34 thus outputs the global data word, with its error bits inverted to become correct bits, to the output selection circuit 60 via bus 58t-. This output selection circuit 6
0 selects one of the four 8-bit data words forming the generic data word and transfers it to said bus 3.
6t-through 8-bit data word DQ'-D7'? Output. As explained below, error correction for 32-bit words requires less parity than four 8-bit words and their associated parity information. The overhead for storing bits is significantly smaller.

Next, the operation of the memory configured as described above will be explained.

First, four 8-bit data words are combined into a 62-bit global data word as described above, and parity information for the Hamming code is generated for the global data word. This global data word, along with its associated six bits of parity information, is stored in respective predetermined locations of the memory arrays 10-12. In order to access the information stored in this way, it is sufficient to simply generate an appropriate address. The address thus generated selects the appropriate 62-bit global data word within memory array 10-12 containing the desired 8-bit data word and its associated six parity billers. These parity bits and the global data word are then input to syndrome generator 50 to generate an error syndrome, followed by error correction circuit 54 to generate a bit error location signal. In this way, the incorrect focus is corrected as necessary, and a corrected data word is output. Note that correction of this error is transparent to needs! 4, and Needy is not informed that these errors have been corrected. By using the error detection/correction circuit according to the present invention configured as described above, it is unnecessary to provide a redundancy circuit and completely replace defective bits and pit rows containing defective bits. Furthermore, defective operations caused by defective bits are also eliminated, and the yield of chips is improved.

Next, the Hamming code used in the memory of the present invention will be explained. As mentioned above, this is a code for detecting and correcting a single error in a Hamming code, and is also called a "distance-6" code, and can also detect duplicate errors. This Hamming code is formed by first determining the number of required check bits or parity bits (seven). In other words, if each binary message to be transmitted now is made up of n information bits (Dn, Dn-0,...), then each binary message has even parity (or odd parity). ) for checking the parity of kll (Pk
*Pk-0*...Pl) is added.

Incidentally, in the case of the present invention, even parity is used. A composite or "encoded" message of n-1-k bits is thus formed. Parity bit P1 (however, 1 is 1°2,...--k)
h, a bit occupying a particular position in these coded messages (n-1-k bit messages); The generic data word and its associated parity bits are also referred to as separate information memory array 10 and parity bit array 12 in the illustrations of FIGS. 1 and 2, respectively.
However, in reality, these bits may be interleaved to form a "coded message" format, which is the case in this embodiment. The position of the parity bit in each coded message is 1°2.4.8.・・・・・・2
1, that is, the rank of 2 to the power of an integral power? It's a good position. Each Pl value has 11 data bits,
As shown in Table 1 for messages of up to 15 bits with 4 bits as parity bits, the parity value at a specific position in the original message is Determined by inspection. Therefore, depending on the parity focus Pl, the odd-numbered tatami positions 1, 3, 5, 7, etc. ...-... was inspected, and the parity pit P2 and the hinge frame were both gold and gold! (2,3), (6,7), (IQ, 11),...
The song is checked, the position of the quaternary digit number set is checked by the parity pit P3, and so on.

The total number of parity pits required for the message length given in Table 1 is shown in Table 2. For example, the original message becomes flk-3 for a code word set in binary coded 1o decimal: l-P (BcD) ten k2, and 31 parity pits are required. For this purpose, it is necessary to insert the parity tick P in the position 1, 2.4 in the coded message Mn+k. The Hamming code message thus transmitted will be 7 bits long and of even parity, as shown in Table 3 for 10 BCD codewords.

Table 2 Table 3 When the inspection of the coded message is completed, the parity is added to the received coded message Mn+k and
Examination number" or "position number", that is, "syndrome number J"'(sk+5k-1tsu"'82t
Sl) is formed such that it is equal to zero when no error is detected. However, if a single error is detected, the binary decimal number of the syndrome number Sk is made to correspond to the position of the message that was received when the error occurred. Table 4 shows aspects of such a parity check. Note that in this Table 4, the bit values Ml, M2, M41 M in the coded word
g is that softP1. P2. P3. This corresponds to P4.

Table 4 (12+J3.M41M1s)...If the blue syndrome number Sk specifies the location where the error appears, then the individual bits sj check a specific location in the coded message Mn+k. Now the odd numbered position (1, 3,
5, 7, 9, 11...), the least significant bit (L
SB) 31 should be equal to 1. Also, all odd numbered positions 1.3.5 in each humming food message
．． 7.9.11... are even parity, a single error in one of these odd positions would be odd parity.

In this case, the value taken by LSB Sl of the syndrome number sk is 1. On the other hand, if no error appears in any of the odd-numbered positions, the parity check is even parity, and the value taken by the LSB Sl is 0.

Similarly, when a single error appears at position 2.3.6.7.10.11..., the syndrome number is 8.
2-1 and 9, and vice versa, 5kS2-0, and so on. Table 4 shows the number of received and each syndrome Sj
This shows a specific pit position within the message Mn to be inspected by K. If the number of bits indicating the number of these positions is k, there is a possibility that 2 different syndrome numbers S are formed. However, if 2≧n+, +1. For example, in a BCD message using the Hamming code shown in Table 6, the digit is 5 = 313.
If it is 283-110, this means that an error has appeared in bit position #M of the received message, and therefore a correction will be made at that position. Also, when it is S-Q, it means that the received message was correct.

In order to check a Hamming code message with even parity, it is necessary to calculate the modulo 2 sum (exclusive OR), ie Sj-Koshi. However, MJ represents each position bit of the received message to which check bit Sj is added. If there is no error in these trapped bits, Sj -0, and vice versa, Sj-1. Perform this procedure for all j-1, 2, 3,...
・Repeat about.

Regarding the Hamming code, Table 5 shows the procedure for generating the Hamming code for the 6♂T message 101011 using even parity.

Original data message beam, Ds...D knee 10
It is 1011. Since n is 6, the required number of bits is k - 4 (P, P3P2 Pl), which is converted into a 10-bit Hamming code message. These parities P4. P3. P2. P-worker,
Bit positions 8 and 4°2.1 of coded message M are respectively assigned. Note that the parity tick P~P4 is determined by taking the sum of modulo 2. The "+" sign in the table indicates this addition.

Table 5 [Coding bit position] MIOM9 M8 M7 M, M5
M, MJ M2 Ml [Original message pit position] D6D5D4D3D2D1 [Even parity pit position] p, p3 p2p1 [Original data message Dn] [Pl -MJ +M5 +M) + M9- 1
] (p2- M3+M, + M7+M10-1) [
:P3- M, + M6+M, -0]11(P4-
+M. -1] 1 oi 1 oioiii [Humming food message M] 1 011010 Now, for example, a message M that has an error value in bit position 6
K and shall be calibrated. At this time, the message is not 1011110111 but 1a1
It will be output as ii oi oi ii i . In this case, the syndrome generation bit is generated as follows.

31 = M1 + M3 + M5 + M7 + M
g −032= M2+ M3+ M, + M7+
It's M. Tomi 133 = M4 + M3 + M6 +
M7 = 184 = Ms + Mg + M. =
0 The number of syndromes thus formed is s - s
, 53S2snee0110, and its 1D value is 6, which indicates that there is an error in bit position 6 of the received message. This error can be corrected by changing bit M6 e from 1 to 0.

FIG. 6 shows the actual arrangement of the data bits Dl to D32 and the parity bits P1 to P6 in said generic data word, with their respective positions relative to the coded message M having bits M to M:ss''e. Since the Hamming code requires parity bits to be inserted at predetermined positions, the interleaving of the information memory array 102 and the parity memory array 12 ensures that the relative positions of the individual bits are Both arrays are assembled in a manner that reflects their physical configuration.
As a common bit position, M29M41M9
, M16. The configuration is such that all 38-bit words representing the coded message M, in which parity bits are interwoven with M32, are selected. Such separation of parity bits and global data bits can be easily accomplished by wiring the inputs of the sense amplifier f46.48 (FIG. 2) to appropriate bit lines.

As mentioned above, in this embodiment, the data information consists of 8-bit words, and in order to perform all error correction, four of these 8-bit words are combined into a 32-bit comprehensive data word, and this comprehensive data hood is A further 6 bits are combined to form a 68-bit coded message M. The position of the parity bit v″i1.2.4.8.16.3 in this coded message vC2″
2, and these parity bits are set to parity ?2 for the relevant bits in the coded message, as shown in Table 6. Setting up VC is a good thing.

The next bit associated with each of the syndrome bits 80-S6 is also combined with an exclusive OR function as shown in Table 7. In Table 7, parity points (Pl-P6) are shown in parentheses after the numbers indicating their respective positions.

Pa 1st victory 8th song,゛%,”〕φ,14,1koma2°・No.
7 Table i 37.38 S4 = 1(P4)l 9.10. 11.12.
13+, 14.15.24゜l 25. 26. 2
7. 28. 29. 30,31□ 35 = 1 (P6): 32.33.34.35.3
6.37.38 ■ If no error is detected in the coded message, error syndrome (Se Ss 843382 Sx)
will take the decimal value of O as described above. Also, if a single bit error exists in the coded message, the error syndrome will specify the defective bit. However, duplicate errors (double errors)
If this is the case, the information read from memory will contain multiple errors and the number of syndromes will be unpredictable. Regardless of the form of the Hamming code, its error correction ability is 1
Equal to bits. In other words, the Hamming code can only correct a 1-bit error. In other words, the Hamming code can detect 21 1-bit errors, but cannot correct them.

FIG. 4 shows the configuration of the output selection and error correction circuit shown in FIG. 2. However, in this figure as well, the same reference numerals as in FIG. 2 indicate the same components. The illustrated syndrome generator 50 generates an error syndrome (S5
Ss 34333231) is output to the bus 52. The error decoding circuit 54 receives and decodes the error syndrome word, and then performs the encoding 38.
Output on one of 62 mutually exclusive outputs corresponding to the bit position of the bit message. However, in this case, since it is no longer necessary to output parity information, only the bit positions corresponding to the original 62-bit comprehensive data word are output.

The bit error indication line is input to a multiplexer 70 whose select input is connected to a four line select bus 72. The multiplexer 70 thus selects one of the four 8-bit sets corresponding to the four data words forming the 62-bit global data word input to the error syndrome generator 50. The 4-line selection bus 72 is connected to the output of a 2-to-4 decoding circuit 74, and the input of this decoding circuit is connected to the 2-line data bus 2.
0 to receive the first two bits of the column address input.

The 62-bit path 26 inputs to a multiplexer 76 whose selection input is also connected to a 4-line selection bus 72. Multiplexer 76 selects one of the four 8-bit data words forming the 62-bit global data word. The multiplexer 7
The output of 0 is input to a group of eight exclusive OR gates 78 via an eight pit pad/S82. Note that these multiplexers 70, 76, together with the exclusive OR date group 78, constitute the output selection circuit 60 of FIG. 2, and are the final stage of column decoding.

FIG. 5 shows a part of the configuration of a syndrome generator 50 that generates the syndrome bits s, 6. From Table 6 above, it can be seen that the syndrome bit S6 is formed by performing an exclusive function on bit positions 32 to 38 of the coded message.

Further, from FIG. 5, it can be seen that P6 is arranged in bit position M32 of the coded message, and data bits D27-D3□ in the generic data word are arranged in bit positions M33-)J38 of the coded message. I understand that. These bit positions M32 and fM33 of the encoded message are both input to the exclusive ○R gate 84ic, and their outputs are input to the exclusive ○R gate 84ic.
The bit positions M34 and M3s input to one input of R date 86 are input to exclusive OR date 88, the output of which is input to one input of exclusive OR date 90. Additionally, bit positions M35 and M37 are input to an exclusive OR date 92 whose output is
It is input to the other input of R gate 86. exclusive OR
The other input of gate 90 is connected to bit position M38. In addition, the outputs of exclusive OR data 86, 90 are respectively connected to the dynamic input of exclusive OR date 94, whose output is connected to bit position M38. This includes:

In addition, other syndrome bits S1t S2+ S
Although the circuit for obtaining the exclusive OR function for 4t S8+S15 is not shown, it has the same configuration as the one described above for the syndrome bit S6 in FIG.

Next, FIG. 6 shows a schematic configuration of the error correction decoding circuit 54 and the multiplexer 70. However, in FIG. 4, it was shown that one bit out of the 62 bits of the output line of the decoding circuit 54, which are in a mutually exclusive relationship, is generated and multiplexed to the bus 80. The embodiment shown in the figure integrates both of these functions. First, the syndrome generator 50 outputs syndrome bits 81 to S6 in inverted and non-inverted formats. Additionally, each bit position in the coded word that corresponds to a data bit in the global data word is decoded into a series of multi-input AND dates. These multi-inputs -Dr-) are arranged in groups of four to constitute a plurality of bit error correction circuits 98, and one of these bit error correction circuits 98 is configured to input eight data of output data words D0' to D7'. It corresponds to each bit. In each of the bit error correction circuits 98, only one of the four multi-input AMD) f'-4 is selected by the 2-to-4 decoding circuit 74.

Thus, the error correction circuit 98 associated with the first D0' of the data word selects one of the bit positions M3, J3, M22, M3o in the coded data word. The selection of bit position M3 is performed by providing a seven-person AND date 100, six of which are connected to the error syndrome bus 52. Furthermore, among these six human forces, two human forces are the non-inverting output line S□.

S2 respectively, and the inputs of the remaining υ are connected to their inverted output lines. Therefore, if the error syndrome generator 50 outputs a 6-bit word in which the first two bits are high and the remaining bits are low, it will represent the decimal number 6. This state corresponds to bit position M3, and the AND date 100 of p1 above selects this bit position. Similarly, bit position M is selected by 7 manual AND date 1
Selection of bit position M22 is performed by providing 7 manual AND date 104, and selection of bit position M3° is performed by providing 7 manual AND date 106t. Thus bit positions M3, M13, as described above.

M22? The first data bit D in each data word V in which M2O consists of a 62-bit global data word. will be responded to.

In order to select one of the above four AND keys 100 to 106, one of the four line decode buses is connected to the remaining seventh input. It becomes possible to select the data bit D0 in the data hood.The above ANDr -) 100 to 10
6 is connected to a four-power exclusive OR/7"-1-108, and the output of this exclusive OR date is connected to one input of an exclusive OR date 110.
By providing eight 9OR dates 110, the exclusive OR date group 78 is constructed. Thus, the exclusive O associated with the first bit in the stored data word
The output of the R gate 110 will be connected to the Do' output of the memory.

The result of combining the above memory arrays is error detection/
The correction circuit has been described, and as mentioned above, in this circuit, 41 8-bit words are combined into 11 62-bit words, and this 62-bit comprehensive data is processed according to the Hamming code error detection algorithm. Generate puffy information consisting of 6 bits for each word. Next, convenience 3 consisting of these bits
Generate an 8-bit coded data word ff and clear the parity of the 6 bits @ hot bit positions 1, 2, 4, 8° 16
．． 32 respectively. The word created in this way is
This is stored at an appropriate location in the memory array.

To access this 38-bit coded data word, the appropriate address is input into the array to cause the '58-bit word to be output to the error syndrome generator 50.

The error syndrome generator 50 uses a Hamming code algorithm to generate a 6-bit error syndrome word. Next, this error syndrome word is decoded to determine whether an x-r error exists or not, and if an error exists, the error is
Determine which bit position in the 8-bit word it exists in. Next, the 32-bit data word is extracted from the 68-bit encoded message and multi-dexed to select all of the four data words contained therein. On the other hand, the error information is multi-sourced and inputted to the exclusive 0R) f-t group, and the logic state of the bit in error is inverted. Thus, an error contained in a group of four data words will be corrected.

As described above, the memory according to the present invention is integrated on a chip together with an error detection/correction circuit, a read-only memory (ROM), etc., and this semiconductor memory first stores data information. Memory array 10 and parity information associated with each word in this information memory? It has a parity memory array 12 for storage.

The data words in the tn information memory array 10 associated with the parity information in the array 12 are comprised of a plurality of digital data words. By grouping them together into a single data word, the total number of bits used in each individual word is less than the total number.

What is the information and parity information stored in this way? By addressing and processing through the block food error detection circuit 30, an error is detected and an error correction signal corresponding to the bit position of the error is generated.

The information addressed from the information memory array 10 and the bit error number fN from the error detection circuit 30 are then demultiplexed by the demultiplexers 70 and 76. The data information thus demultiplexed and the bit error location information associated therewith are input to the error correction/selection circuit 34. This error correction/selection circuit 34 outputs data information at 5Vc.

The following sections are further disclosed in connection with the above description.

(1) In a semiconductor memory having an integrated error detection and correction function, storing a plurality of digital data words arranged in a plurality of sets as comprehensive data words, each comprehensive data word consisting of a predetermined number of digital data words. second first
storage means for storing dizotal error checking information corresponding to each of said generic data words and generated for the bit length of said generic data words according to a block error code algorithm using an error syndrome coding technique; , a second storage means adapted to form a coded data word by said inclusive data word and said data correction information reaching said first and first access means adapted to access one of said coded data words in a second storage means for output from said storage means; Error detection/correction means for determining the presence of an error in said coded data word according to a data code algorithm, and for performing correction of the error thus determined and outputting a corrected generic data word. and second access means for accessing selected data words of the digital data words in the corrected global data word A.

(The 10 error codes listed in 21tfl are the semiconductor memory listed in the first item that includes the Hamming code.)

(3) said first and second storage means having a memory array for storing said coded data words, said error correction first signal bit being generated in accordance with said Hamming code; 3. The semiconductor memory according to claim 2, further comprising a parity bit inserted at a predetermined position in the coded data word.

(4) said error detection/correction means receives said generic data word from said first storage means and said error correction code from said second storage means, and detects errors in said generic data word; Detect if it exists and
The same is configured to generate a signal indicative of the location of an error within the generic data word if an error exists, and further to store from the first storage means the generic data word and the bit position of the error. 2. A semiconductor memory as claimed in claim 1, further comprising error correction means adapted to receive a signal representing a 1 and change the logic state of the bit in the global data word determined to be in error.

(5) The first storage means has a first memory array in which the data words are arranged and stored in rows and columns, and the error correction information is arranged in rows and columns in the second storage means. a second memory array storing
Further, the first access means includes a row decoder for receiving an external address and selecting one row from the first and second memory arrays, and a row decoder for selecting one column from the first and second memory arrays. a column decoder for accessing one of the =9 inclusive data words in the selected column in the first memory array and in the selected column in the second memory array; 2. A semiconductor device according to claim 1, wherein the second access means has a demultiplexer for inputting all data words selected from among the data words. memory.

6. A semiconductor memory according to claim 1, wherein said block code error storage means is adapted to detect a single error in said global data word.

(7) said error detection/correction means and said second access means receive said accessed coded data word from said first access means and determine the location of the detected error within said global data word; error detecting means adapted to generate an error syndrome signal representing the coded data word; and detecting a bit error position No. 1 for each of the bit positions in the coded data word, and assigning bit error position No. 1 mutually exclusively to the bit error position No. 1. bit toilet indicating means which is activated only when an error is detected; a selected one of said digital data words from said coded data words; and said bit position indicating means outputted from said bit position indicating means. demultiplexer means for demultiplexing corresponding ones of the bit error position signals; a demultiplexed one of said digital data words and a pair of said bit error position signals;
error correction means for inverting the bits of the demultiplexed digital data having the corresponding one of the demultiplexed bit error positions No. 1 in the active state upon receiving the corresponding one; The semiconductor memory according to item 1, consisting of:

(8) Error Detection and Correction Function In a semiconductor memory comprising a collection of data words, the data words are arranged in a number of sets as comprehensive data words, each comprehensive data word containing a plurality of digital data words consisting of a predetermined number of digital data words. 1st to remember
storage means for storing parity bits according to a Hamming code error detection/correction hood, these parity bits corresponding to each of said inclusive data words, and the number of parity bits associated with said inclusive data words being equal to said inclusive data word; parity bit storage means, the parity being determined by the number of bits of the data word; and external addresses corresponding to selected n data words of said data word? access means for receiving and accessing one of said global data words in said information array means containing said selected data word and an associated parity bit from said parity bit storage means; receiving the generated inclusive data words and the parity bits associated with these data words and detecting whether an error is present in the inclusive data word according to a Hamming Hood error detection/correction code, and if an error is present; syndrome generating means configured to generate a signal containing information representing the bit position of the error within the generic data word;
generating a bit error location signal for each bit location in the coded data word, the bit error location signals being mutually exclusive and being activated only when an error is detected; indicating means; demultiplexer means for demultiplexing a selected one of the digital data words from the data word and a corresponding one of the bit error position signals output from the bit position indicating means; said digital data word having a corresponding one of said demultiplexed bit error location signals in an active state in response to receiving a demultiplexed one of said digital data words and a corresponding one of said one hundred bit error locations; A semiconductor memory characterized by comprising error correction means for inverting the bits of multiplexed digital data.

9. The semiconductor memory of claim 8, wherein the humming hood detects a single error in the global data word.

aα The information array is the 22 rows of the comprehensive data word?
and a memory array storing the parity bits arranged in rows and columns, the parity bit storage means having a memory array storing the parity bits arranged in rows and columns, and each arranging the rows and columns of the information memory array to correspond respectively to the rows and columns of associated parity bits in the parity bit array; a row decoder for selecting a row and a column decoder for selecting a column from each of the information memory array and the parity bit memory array; 9. The semiconductor memory of claim 8, wherein one of the inclusive data words and the associated parity bit are fully output.

αB The generic data words and the parity bits associated with these data words are combined into a coded data word, and the associated block bits are assigned a predetermined position in the coded data word according to the Hamming code. and wherein said information memory storage means and said parity bit storage means are arranged from a single memory array storing said coded data words arranged in rows and columns; 9. Accessible by said access means, further comprising said error correction means and said demultiplexer means capable of distinguishing between said generic data word and said block bits within said coded data word. The semiconductor memory described.

(1) the error correction means comprises an exclusive-OR correction circuit associated with each of the bits in the demultiplexed digital data word; receiving an associated one of the bit error location signals and determining the associated bit of the demultiplexed digital data word if the logic state of the associated one of the bit error location signals is indicative of an error; 9. The semiconductor memory according to claim 8, wherein the semiconductor memory is inverted.

α3 The syndrome generating means receives and decodes the error syndrome word and assigns each of the bit positions of the accessed global data word A to the associated mutually reciprocal bit error position signal? by generating the Hamming code to indicate the location of the error in the global data word and making it a code that corrects only one error, and further by the demultiplexer means a first demultiplexer for taking and selecting the selected data word according to the external address; and the bit error location fg associated with the selected data word output from the first demultiplexer.
9. The semiconductor memory according to claim 8, further comprising a second demultiplexer for selecting a related one from among the addresses according to the external address signal.

I. said error correction means comprises a series of exclusive OR correction circuits, each of said exclusive OR correction circuits detecting one bit of said selected data word output from said first demultiplexer and one bit of said selected data word output from said first demultiplexer; In conjunction with the associated bit error location signals output from the demultiplexer, the exclusive-OR correction circuitry detects the received one of the selected data words if the associated one of the bit error location signals indicates an error. 14. The semiconductor memory according to claim 13, wherein the logic state of the bit is inverted.

(19) In detecting and correcting errors in information stored in a semiconductor memory, the data words 'a-1 are arranged into sets of data words to form a comprehensive data word, and these data words' are storing on a first storage medium, and storing on a second storage medium parity bits corresponding to each generic data word, the parity bits being generated according to a block code error detection/correction algorithm, a parity bit 'I& for each of the generic data words is such that it corresponds to the bit length of the generic data word 5[t,; accessing a selected one of the data words and its associated parity bit from the second storage medium, wherein the accessed comprehensive data word includes =9 specific to the fg number from the external source; receiving the accessed inclusive data word and parity bits and determining that an error exists in the accessed inclusive data word and parity bits in accordance with said block code data algorithm; ? detecting and generating an error syndrome signal containing error information regarding the bit position in the inclusive data word thus determined to be in error; and receiving the error syndrome signal to detect the bit position in the inclusive data word. generating a bit error location signal for each of said comprehensive data words, said bit location signals being mutually exclusive such that said signals are activated only if an error is detected; Then, one of the bit error position signals corresponding to these words is selected and demultiplexed, and the demultiplexed dizotal data word and bit error position signal are received and activated. An error detection and correction method characterized in that bits of a demultiplexed digital dataword having a corresponding one of a certain demultiplexed bit error position signal are inverted.

(Old) The error detection and correction scheme of claim 1, wherein the block code error detection/correction algorithm comprises a Hamming code for detecting single bit errors in the global data word.

7) The generic data word and its associated parity bits are arranged in coded data words of a metal wheel, and the coded data words are arranged in the first and second storage media of equal capacity. 2. The error detection and correction method of claim 1, wherein the error detection and correction method is stored in a single storage medium.

(1 & The parity bits are all arranged in predetermined bit positions according to the block code error detection/correction algorithm, and the block code error detection/correction algorithm
Error detection and correction method according to item 1, in which the correction algorithm is a h2 Hamming code.

Although non-inventive embodiments have been described above, it goes without saying that the memory and error detection/correction code system according to the present invention may be implemented by making appropriate additions or changes to the described embodiments. do not have.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a read-only memory IJ (ROM) using an error detection and correction circuit according to the present invention, and FIG. 2 is a block diagram showing an enlarged memory array in the error detection and correction circuit shown in FIG. 3 is a diagram illustrating the arrangement of data bits and parity bits in a comprehensive data word used in the present invention; FIG. 4 is a block schematic diagram illustrating the error detection and correction section of the memory array shown in FIG. 2; FIG. 5 is a cooking circuit diagram showing a part of a syndrome generator that generates an error syndrome signal, and FIG. 6 is a block diagram showing a logic circuit forming an error correction circuit and a demultiplexer circuit. DESCRIPTION OF SYMBOLS 10... Information memory array, 12... Parity memory array, 30... Block code error detection circuit, 34...
Error correction/selection circuit, 70.76... Demultiplexer.

Claims (2)

[Claims] (1) In a semiconductor memory having an integrated error detection and correction function, storing a plurality of digital data words arranged in a plurality of sets as comprehensive data words, each comprehensive data word consisting of a predetermined number of digital data words. 1st for
storage means for storing, corresponding to each of said generic data words, digital error checking information generated for the bit length of said generic data words according to a block error code algorithm using an error syndrome coding technique; , second storage means adapted to form a coded data word with said generic data word and said data correction information associated therewith; and said first storage means comprising a selected one of said digital data words. and first access means adapted to access one of said coded data words in a second storage means for output from said storage means; and for receiving said accessed coded data word and said Error detection for determining the presence of an error in said coded data word according to a block data code algorithm, correcting the error thus determined and outputting a corrected generic data word. / correction means; and second access means for accessing selected data words of said digital data words in said corrected global data word. (2) in detecting and correcting errors in information stored in semiconductor memory, arranging digital data words into sets of data words to form comprehensive data words; storing on one storage medium and storing on a second storage medium parity bits corresponding to each global data word, wherein the parity bits are generated according to a block code error detection/correction algorithm. the number of parity bits for each of the generic data words is such that it corresponds to the bit length of the generic data word; accessing a selected one of the data words and its associated parity bits from the second storage medium, the accessed generic data word having a parity bit specified by the external signal; receiving the inclusive data word and parity bits thus accessed and detecting whether an error exists therein according to said block code data algorithm; generating an error syndrome signal containing error information for the bit positions in the generic data word determined to be, and receiving the error syndrome signal to generate a bit error position signal for each bit position in the generic data word. generating bit position signals, the bit position signals being mutually exclusive such that they are activated only if an error is detected; Selecting and demultiplexing one of the position signals, receiving the demultiplexed digital data word and the bit error position signal, and demultiplexing one of the active demultiplexed bit error position signals. An error detection and correction scheme characterized in that the bits of a demultiplexed digital data word with a corresponding one are inverted.