JPS63207219A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To shorten a digital processing time and to reduce an operation speed necessary for a digital circuit by making a circuit to execute a digital processing into two circuits of a digital multiplier and a digital adder, and further, using one circuit of the digital adder for the digital processing, processing in a critical path within one sampling time. CONSTITUTION:By a sampling device 2, an analog input signal 1 is sampled by a sampling frequency and a forecasting analog signal 12 and a difference signal 4 are obtained by an analog subtracter 3. A difference signal 44 is integrated by an analog intergrator 5 and quantized by a multi-bit quantizing device 6. The quantized signal is inputted through a delaying device 7 to an adder 8, added with the output of a delaying device 17 to give the delay of one sampling time and the output is simultaneously inputted with a filter 9 and the delaying device 17. At the filter 9, a noise component is removed, further, a sampling frequency is decreased by a sampling frequency converter 10 and a digital output signal 11 is obtained. On the other hand, the output of the quantizing device 6 is inputted and doubled through the delaying device 7 to a multiplier 15, added with the output of the delaying device 17 by an adder 16 and the analog forecasting signal 12 is obtained by a local digital/analog converter 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog-to-digital converter for code conversion. In particular, the present invention relates to a primary side primary noise shaping oversampling type analog-to-digital converter.

〔overview〕

The present invention is an analog-to-digital converter for code conversion, in which the feedback loop, which is a critical path, is connected to an analog subtracter, an analog multiplier, a multi-bit quantizer, a digital multiplier, a digital adder, and a local digital converter.
It consists of an analog converter and has two circuits for digital processing: a digital multiplier and a digital adder. Furthermore, since the processing of the digital adder is doubled, the wiring shifts one bit to the left and fixes the least significant bit to rOJ. The digital processing is performed as one circuit of the digital adder, and by performing processing within the critical path within l sampling time, it is possible to shorten the digital processing time and lower the operating speed required of the digital circuit. This is what I did.

[Conventional technology]

FIG. 2 is a block diagram of a conventional analog-to-digital converter.

Conventionally, as shown in FIG. 2, an analog-to-digital converter of the -order noise shaping oversampling type uses a sampler 2 to sample an analog input signal l at a sampling frequency, and an analog subtracter 3 to predict the signal. A difference signal 4 from the analog signal 12 is obtained. The obtained difference signal 4 is integrated by an analog integrator 5, and its output is quantized by a multi-bit quantizer 6. A digital delay device 22 applies a delay of one sampling time to the quantized signal. The output from the digital delay device 22 is integrated by the digital integrator 23, and the sum signal 14 of the outputs of the digital delay device 22 and the digital integrator 23 is obtained by the digital adder 24. The obtained sum signal 14 is converted from a digital signal to an analog signal by a local digital-to-analog converter 13 to obtain an analog predicted signal 12. Further, the output of the digital integrator 23 is sent to the digital filter 9.
The noise components outside the band are removed, and the sampling frequency is further lowered by the sampling frequency converter 10 to obtain the digital output signal 11.

The transfer functions of this system are X (Z), Y (Z), Q (
When Zl, Y[Z)=(1-Z-') ・XTZ)+(1-Z-'
)”−Q(Z) −−−−−−−−(11. However, z = e127eTs, e is the base of the natural logarithm, π is pi, f is the signal frequency, and f is the sampling frequency The output Y TZ) of the digital adder 23 is expressed as Y[zl= (X(z)+(1-Z-') ・Q(zl
)・Z−′−−−・−・−−〜−−(2).

[Problem that the invention seeks to solve]

However, in such a conventional first-order noise shaping oversampling analog-to-digital converter, the critical path is shown in Figure 2, consisting of an analog subtracter 3, an analog integrator 5, a multi-bit quantizer 6, and a digital delay. 22, a digital integrator 23, a digital adder 24, a local digital-to-analog converter 13, and an analog subtracter 3 in a feedback loop, and this processing must be performed within one sampling time. Since this process includes two digital additions, there is a drawback that the operating speed required of the digital circuit is high.

The present invention solves the above-mentioned drawbacks and provides analog
The purpose is to provide a digital converter.

[Means for Solving the Problems] The present invention provides a sampler that samples an input analog input signal at a sampling frequency, and an analog subtraction method that obtains a difference signal between the output of the sampler and an analog prediction signal. an analog integrator that integrates this difference signal, a multi-bit quantizer that quantizes the output of this analog integrator, and means for creating a sum signal based on the output of this multi-pint FFI converter. , and a local digital-to-analog converter that manually inputs the sum signal and supplies the analog prediction signal to the analog subtracter, the means for creating the sum signal includes the multi-bit quantization. a digital multiplier that doubles the output of the multi-bit quantizer, and a first digital adder that receives the output of the multi-bit quantizer as a first input and adds it to a second input value every sampling time. and a digital delay device that delays the output of this first digital adder by one sampling time and supplies it to the second input of this first digital adder; and a second digital adder that adds the outputs of the multipliers to create the sum signal.

[Effect]

The output of the multi-bit quantizer is doubled by a digital multiplier. Further, the first digital adder and digital delay device add the output of the multi-bit quantizer and the output one sampling time before. This added result is delayed by one sampling time using a digital delay device. A second digital adder adds the output of the digital multiplier and the output of this digital delay to create a sum signal, which is applied to the local digital-to-analog converter. The above digital multiplier is realized by wiring by shifting the output of the quantizer one bit to the left and fixing the lowest value to "0", reducing the digital processing time by reducing the digital processing on the critical path. This can reduce the operating speed required for digital circuits.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an analog-to-digital converter according to an embodiment of the present invention. In FIG. 1, the analog-to-digital converter includes a sampler 2 that samples an input analog signal 1, and an analog subtracter 3 that obtains a difference signal 4 between the output of the sampler 2 and an analog prediction signal 12. , an analog integrator 5 that integrates this difference signal 4, and a multi-bit quantizer 6 that quantizes the output of this analog integrator 5.

The output of the multi-bit quantizer 6 is passed through a digital delay device 7, and a digital adder 8 is provided for adding this quantized signal to a signal quantized one sampling time before the quantized signal. A digital filter 9 removes noise components outside the signal band of the output of the digital adder 8, and a sampling frequency converter 10 lowers the sampling frequency of the output of the digital filter 9 to output a digital output signal 11. Be prepared. Further, a digital multiplier 15 that doubles the output of the digital delay device 7, a digital delay device 17 that delays the output of the digital adder 8 by one sampling time and supplies it to the digital adder 8; a digital adder 16 that adds the output of the digital multiplier 15 and the output of the digital multiplier 15;
A local digital-to-analog converter 13 is provided.

The delay amount of the digital delay device 7 is adjusted so that the two input signals of the analog subtracter 3 differ by substantially one sampling time.

The operation of the analog-to-digital converter having such a configuration will be explained.

First, in FIG. 2, the output of the multi-bit quantizer 6 is expressed as Y
(Z), the output of the digital integrator 23 is Y (Z), and the input to the local digital-to-analog converter 13 is Y (Z).
', then Y(z)' = Y(zl ・Z-' + Y(z)
-------(3). Formula (3)
When transformed, it becomes 1--------...-C4).

When a circuit is constructed using equation (4), it becomes as shown in FIG.

A sampler 2 samples an analog input signal 1 at a sampling frequency, and an analog subtracter 3 obtains a difference signal 4 from a predicted analog signal 12. The obtained difference signal 4 is integrated by an analog integrator 5 and quantized by a multi-bit quantizer 6.

This quantized signal is simultaneously inputted to a digital adder 8 and a digital multiplier 15 via a digital delay device 7, and is input to a digital delay device 17 by the digital adder 8.
The output is added to the output of the digital filter 9 and the digital delay device 17 at the same time. A digital filter 9 removes noise components outside the band, and a sampling frequency converter 10 lowers the sampling frequency to obtain a digital output signal 11.

On the other hand, the output of the multi-bit quantizer 6 is transferred to the digital delay device 7.
The signal is input to the digital multiplier 15 via the digital multiplier 15, is doubled by the digital multiplier 15, is added to the output of the digital delay device 17 by the digital adder 16, and is added to the local digital multiplier 15.
The analog converter 13 converts the digital signal into an analog signal to obtain an analog predicted signal 12, which is input to the analog subtracter 3. Here, analog subtracter 3
Analog subtraction by analog integrator 5, analog integration by analog integrator 5, quantization by multi-bit quantizer 6, delay by digital delay device 7, digital multiplication by digital multiplier 15, digital addition by digital adder 16, and local digital-to-analog conversion Digital-to-analog conversion processing by the converter 13 is performed within one sampling time.

〔Effect of the invention〕

As explained above, the present invention has the excellent effect of shortening digital processing time and lowering the operating speed required for digital circuits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an analog-to-digital converter according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional analog-to-digital converter. 1...analog input signal, 2...sampler, 3...
・Analog subtractor, 4... Difference signal, 5... Analog integrator, 6... Multi-bit quantizer, 7.17.22.
...Digital delay device, 8.16.24...Digital adder, 9...Digital filter, 10...Sampling frequency converter, 11...Digital output signal, 1
2... Analog prediction signal, 13... Local digital-to-analog converter, 14... Sum signal, 15... Digital multiplier, 23... Digital integrator.

Claims (1)

[Claims] (I) A sampler (2) that samples an input analog input signal at a sampling frequency, and an analog subtracter (3) that obtains a difference signal between the output of this sampler and an analog prediction signal. ), an analog integrator (5) that integrates this difference signal, and a multi-bit quantizer (6) that quantizes the output of this analog integrator.
) and the sum signal (14) based on the output of this multi-bit quantizer.
and a local digital-to-analog converter (
13), the means for creating the sum signal includes a digital multiplier (15) that doubles the output of the multi-bit quantizer; a first digital adder (8) whose output is given to the first input and which adds the second input value every sampling time; a digital delay device (17) that provides a delay and supplies it to the second input of the first digital adder; and creates the sum signal by adding the output of this digital delay device and the output of the digital multiplier. and a second digital adder (16).