JPS63205572A - Error preventing circuit for voltage measurement - Google Patents

Error preventing circuit for voltage measurement

Info

Publication number
JPS63205572A
JPS63205572A JP3890287A JP3890287A JPS63205572A JP S63205572 A JPS63205572 A JP S63205572A JP 3890287 A JP3890287 A JP 3890287A JP 3890287 A JP3890287 A JP 3890287A JP S63205572 A JPS63205572 A JP S63205572A
Authority
JP
Japan
Prior art keywords
voltage
converter
circuit
measurement
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3890287A
Other languages
Japanese (ja)
Inventor
Katsuyoshi Teru
輝 勝義
Shizuo Kamikura
上倉 志津夫
Shuichi Kameyama
修一 亀山
Hidemitsu Saito
齋藤 秀光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3890287A priority Critical patent/JPS63205572A/en
Publication of JPS63205572A publication Critical patent/JPS63205572A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To speed up measuring operation by removing an error in measured voltage due to equivalent stray capacity which is present on the side of the input bus of an A/D converter by a discharging circuit. CONSTITUTION:The discharging circuit 7 is constituted by interposing the series circuit of a resistance R and a relay contact point rs between the ground and a bus 10 connected from a multiplexer MPX to a DC measuring instrument DCM closely to the input terminal 9 of the A/D converter of the bus 10. Then a driving pulse Ps with a period T is applied to the contact point rs at the time of voltage measurement, and consequently the contact point rs is turned on to set the voltage at the terminal 9 to a zero state temporarily. Then the voltage V1 of a measurement object point 11 is inputted to the A/D converter. Even when a voltage V2 at a next measurement object point 12 is inputted to the A/D converter, the contact point rs is turned on with the pulse Ps before the voltage V2 is measured to clear the remaining voltage at the time of the voltage V1 to a zero state temporarily, and a DC voltage is inputted to the measuring instrument DCM. Namely, the contact point rs is operated associatively with the switching of switches RS1-RSN of the multiplexer MPX to clear remaining charges due to the stray capacity of the bus 10.

Description

【発明の詳細な説明】 〔概要〕 ・例えばプリント基板組立体を被試験体とし、マルチプ
レクサと、アナログ−デジタル(A−D)変換器によっ
て被試験体の電源電圧、素子動作電圧等を測定する計測
回路において、A−D変換器の入力母線側に存する等価
的浮遊容量による計測電圧の誤差(残留電圧誤差)を、
放電回路で除去することにより、計測誤差を1/100
0またはそれ以下に抑え。
[Detailed Description of the Invention] [Summary] - For example, a printed circuit board assembly is used as a test object, and the power supply voltage, element operating voltage, etc. of the test object are measured using a multiplexer and an analog-to-digital (A-D) converter. In the measurement circuit, the measurement voltage error (residual voltage error) due to the equivalent stray capacitance existing on the input bus side of the A-D converter is
By removing it with a discharge circuit, the measurement error can be reduced to 1/100.
Keep it to 0 or less.

かつ計測の高速度化をはかることである。In addition, the aim is to speed up the measurement.

〔産業上の利用分野〕[Industrial application field]

本発明はプリント基板テスタまたはICテスタにおける
電圧測定誤差防止回路に関する。
The present invention relates to a voltage measurement error prevention circuit in a printed circuit board tester or an IC tester.

多数の電圧チェックポイントが設定されたプリント基板
組立体を被試験体とする試験にさいし。
When testing a printed circuit board assembly with multiple voltage checkpoints as the test object.

試験ケーブルまたは計測用入力母線の浮遊容量による誤
差をなくして試°験の高速度化、高信頼性をはかるもの
である。
This eliminates errors caused by stray capacitance in test cables or measurement input buses, increasing test speed and reliability.

(従来の技術〕 第3図は従来の電圧計測回路を示すブロック図。(Conventional technology) FIG. 3 is a block diagram showing a conventional voltage measurement circuit.

また第4図は電圧計測時のタイムチャートである。Moreover, FIG. 4 is a time chart during voltage measurement.

第3図において、 11.12.−・−3nはそれぞれ
電源もしくは素子動作の電圧チェックポイントとされる
要部基板回路の計測対象点である。
In Figure 3, 11.12. -.-3n are measurement target points of the main board circuit, which are respectively used as voltage check points for power supply or element operation.

MPXは複数の計測対象電圧を順次走査させるスイッチ
、 RsI Rs2・・−・、Rsnを備えるマルチプ
レクサ。
MPX is a multiplexer equipped with a switch that sequentially scans a plurality of voltages to be measured, RsI, Rs2..., Rsn.

”DCMはマルチプレクサ?IPXの出力側に接続され
る・直流電圧測定器である。該測定器は計測対象のアナ
ログ電圧をデジタル信号に変換し出力する端子Do、D
1 、o2−−Onを具備する。
"DCM is a DC voltage measuring device that is connected to the output side of the multiplexer IPX. This measuring device converts the analog voltage to be measured into a digital signal and outputs it through terminals Do and D.
1, o2--On.

第3図回路の動作を第4図のタイムチャートにより説明
する。
The operation of the circuit shown in FIG. 3 will be explained with reference to the time chart shown in FIG.

即ち計測対象点がマルチプレクサによって順次切り替え
られ、母線10の出力が直流電圧測定器のA−D変換器
に入力される計測電圧波形が示される。
That is, the measured voltage waveform is shown in which the measurement target points are sequentially switched by the multiplexer and the output of the bus 10 is input to the AD converter of the DC voltage measuring device.

タイムチャートは1時間軸上の周期TによりスイッチR
slがONシ、続いてスイッチRs2がON、更にRs
3がONするというような走査が繰り返されるが、先ず
計測対象点11の電圧v1がA−D変換器に入力され、
続いて計測対象点12の電圧v2が入力され、更に計測
対象点13の電圧vコ、が入力され。
The time chart shows the switch R depending on the period T on the 1-hour axis.
sl is turned on, then switch Rs2 is turned on, and then Rs
3 is turned ON, the scanning is repeated, but first, the voltage v1 of the measurement target point 11 is input to the A-D converter,
Subsequently, the voltage v2 at the point to be measured 12 is input, and further the voltage v at the point to be measured 13 is input.

これら電圧がA−D変換されることになる。These voltages will be converted from analog to digital.

然しなからR31R3!−Rsnスイッチの動作期間T
I中において、計測対象点11.12・・−・、nの電
圧が正しく A−D変換器に入力されず次の如き問題点
が指摘される。
However, R31R3! -Rsn switch operating period T
During I, the voltages at measurement points 11, 12, .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

例えば、計測対象点12が断線不良等の障害点であると
すれば、電圧v2は当然観測されないはずであるが1図
示Veで示されるような誤差電圧が検出される。特に、
マルチプレクサによる計測対象点の切り替え周期Tを1
0m5以下として試験速度の高速度化をすれば、第3図
におけるマルチプレクサとA−D変換器間の入力母線1
0に存在する対接地浮遊容量Cに蓄積される残留電圧ν
e(点線で示す前回計測対象点11の残留電圧)が観測
されることである。
For example, if the measurement target point 12 is a failure point such as a disconnection defect, the voltage v2 should not be observed, but an error voltage as shown by Ve in FIG. 1 is detected. especially,
The switching period T of the measurement target point by the multiplexer is 1.
If the test speed is increased to 0m5 or less, the input bus 1 between the multiplexer and the A-D converter in Figure 3
The residual voltage ν accumulated in the stray capacitance C to ground existing at 0
e (residual voltage at the previous measurement target point 11 indicated by the dotted line) is observed.

またこの場合、計測電圧の例えば、vlとv2とが互い
に近似する値であるとすれば、高精度のA−D変換器に
よって直流電圧を計測する必要があり、第3図における
入力母線10に存在する前記浮遊容量は計測精度の向上
に大きな支障となる。
In this case, if the measured voltages, for example, vl and v2, are values that are close to each other, it is necessary to measure the DC voltage with a high-precision A-D converter, and the input bus 10 in FIG. The existing stray capacitance poses a major hindrance to improving measurement accuracy.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明の電圧測定誤差防止回路実施例とするブ
ロック回路図である。図において被試験体の計測対象点
11.12.・−・−1nの直流電圧をマルチプレクサ
MPXによって順次切り替え、これをA−ロ変換して電
圧を計測するに当たり、 A−D変換器に接続される入
力母線10に残存する残留電圧を、マルチプレクサMP
Xの切り替え周gTと同じ周期で動作するリレー接点r
sと、 A−D変換器の入力端子9と接地8間のインピ
ーダンスZinに比べて低い値を有する抵抗Rとを直列
接続した放電回路7によって除去するようにしてなる本
発明の電圧測定誤差防止回路として前記の問題点を解決
したことである。
FIG. 1 is a block circuit diagram of an embodiment of the voltage measurement error prevention circuit of the present invention. In the figure, measurement target points 11, 12 of the test object. -1n DC voltage is sequentially switched by the multiplexer MPX, and when this is A-RO converted to measure the voltage, the residual voltage remaining on the input bus 10 connected to the A-D converter is transferred to the multiplexer MPX.
Relay contact r that operates at the same cycle as the switching cycle gT of X
s and a resistor R having a lower value than the impedance Zin between the input terminal 9 of the A-D converter and the ground 8 are removed by a discharge circuit 7 connected in series. The above problem has been solved as a circuit.

〔作用〕[Effect]

本発明は入力母線10と接地8間に、リレー接点rsと
抵抗Rとからなる放電回路が、電圧計測回路のA−D変
換器の入力端子に直結して挿入され、計測に先立って前
記のリレー接点rsをONすることによって、入力母線
に存在する前回計測時の残留電圧を、一旦ゼロ状態にク
リアーして計測の初期設定を確実とするものである。
In the present invention, a discharge circuit consisting of a relay contact rs and a resistor R is inserted between the input bus 10 and the ground 8, directly connected to the input terminal of the A-D converter of the voltage measurement circuit, and the above-mentioned By turning on the relay contact rs, the residual voltage present in the input bus from the previous measurement is once cleared to zero, thereby ensuring the initial setting of the measurement.

しかして、この初期設定は、多数点の電圧計測を順次お
こなうマルチプレクサのスイッチ動作と連動させて毎回
行うことにより計測誤差のない安定な電圧測定回路が実
現されることになる。
Therefore, by performing this initial setting each time in conjunction with the switch operation of the multiplexer that sequentially performs voltage measurements at multiple points, a stable voltage measurement circuit without measurement errors can be realized.

〔実施例〕〔Example〕

以下9本発明の電圧測定誤差防止回路実施例について、
第1図実施例回路と第2図電圧測定回路のタイムチャー
トに従って詳細に説明゛する。
Regarding the following nine embodiments of the voltage measurement error prevention circuit of the present invention,
A detailed explanation will be given according to the time charts of the embodiment circuit of FIG. 1 and the voltage measuring circuit of FIG. 2.

尚、実施例回路ブロック図において、従来と同一の機能
回路部は同一の記号及び参照番号が付与され本発明の要
部が明確となるようにしである。
In the circuit block diagram of the embodiment, the same symbols and reference numbers are given to functional circuit parts that are the same as those in the prior art, so that the main parts of the present invention can be clearly understood.

回路ブロック図中、7は本発明の要部をなす放電回路で
ある。
In the circuit block diagram, 7 is a discharge circuit that forms the essential part of the present invention.

該放電回路7は、マルチプレクサMPXから直流電圧計
測器DCMへ接続する入力母線10に対して。
The discharge circuit 7 is connected to an input bus 10 connecting the multiplexer MPX to the DC voltage measuring device DCM.

該母線のA−D変換器の入力端子の9に近接せしめて、
抵抗Rとリレー接点rsを直列接続した回路を母線10
と接地間に挿入したものである。
Close to the input terminal 9 of the A-D converter of the bus,
A circuit in which a resistor R and a relay contact rs are connected in series is connected to the bus bar 10.
It is inserted between the ground and the ground.

また、計測入力母線10は、接地8との間に入力の母線
長さに比例する等価的浮遊容量Cが存在するが、該容量
Cに並列して放電回路7が挿入される。
Furthermore, an equivalent stray capacitance C proportional to the input bus length exists between the measurement input bus 10 and the ground 8, and the discharge circuit 7 is inserted in parallel with the capacitance C.

該回路7の抵抗Rは^−D変換器の入力端子9と接地間
のインピーダンスZinに比べて充分に小さいことが必
要である。これと直列接続されるrsはリレー接点と限
定する必要はなく、これは高速動作が可能なかつパルス
駆動が容易なアナログスイッチ(半導体スイッチ素子)
でも構わない。
It is necessary that the resistance R of the circuit 7 is sufficiently smaller than the impedance Zin between the input terminal 9 of the ^-D converter and the ground. The rs connected in series with this does not need to be limited to a relay contact; it is an analog switch (semiconductor switch element) that can operate at high speed and is easy to pulse drive.
But it doesn't matter.

かようなリレー接点rsまたはスイッチ素子の動作によ
り入力母!’iIOに蓄積もしくは残存する容量Cの残
留電荷を迅速に除去することが出来る。
The operation of such relay contact rs or switch element causes input mother! 'The residual charge of the capacitor C accumulated or remaining in iIO can be quickly removed.

第1図実施例回路の動作を第2図タイムチャートによっ
てリレー接点rsの動作方法を説明する。
The operation of the embodiment circuit shown in FIG. 1 and the operation method of the relay contact rs will be explained with reference to the time chart shown in FIG.

第2図はこれを第4図と比較対象すれば明らかなように
、MPにによるスイッチRsl及びRs2の動作に従っ
て計測対象点11の電圧V、ならびに計測対象点12の
電圧v2を計測する例が示される。
As is clear from comparison with FIG. 4, FIG. 2 is an example in which the voltage V at the measurement target point 11 and the voltage V2 at the measurement target point 12 are measured according to the operation of the switches Rsl and Rs2 by the MP. shown.

電圧計測の前または後において9周期Tの駆動パルスI
’s (図は三個のパルスが示される)がリレー接点r
sに印加され、これによって該接点rsをOnしてA−
D変換器の入力端子9の電圧を一度零状態にセットする
。この後、計測対象点11の電圧v1がA−D変換器に
入力される。次の計測対象点12の電圧v2がA−D変
換器に入力される場合でも、該電圧V2の計測前、駆動
パルスPsによって接点rsをonさせ、電圧v11計
測の残留電圧をクリアーして一旦零状態となし、然る後
、直流電圧計測器DCMに直流電圧を取り込むようにし
たことである。
Drive pulse I of 9 periods T before or after voltage measurement
's (three pulses are shown in the figure) is the relay contact r
s, thereby turning on the contact rs and A-
The voltage at the input terminal 9 of the D converter is once set to zero. Thereafter, the voltage v1 at the measurement target point 11 is input to the AD converter. Even when the voltage v2 of the next measurement target point 12 is input to the A-D converter, before measuring the voltage V2, the contact rs is turned on by the drive pulse Ps, the residual voltage of the voltage v11 measurement is cleared, and the voltage is temporarily reset. It is set to zero state, and then the DC voltage is taken into the DC voltage measuring device DCM.

即ち、マルチプレクサのスイッチRsl 、 Rs□−
・。
That is, the multiplexer switches Rsl, Rs□-
・.

Rsnの切り替え動作と連動させて放電回路7のリレー
接点rsを動作させることによって入力母線10の浮遊
容量による残留電荷をクリアーする。 然しリレー接点
rsは、計測対象点の電圧v1計測のTI期間、これに
続く、電圧v2計測のT2期間は、放電回路7のリレー
接点rsをOFFさせる。
By operating the relay contact rs of the discharge circuit 7 in conjunction with the switching operation of Rsn, the residual charge due to the stray capacitance of the input bus 10 is cleared. However, the relay contact rs turns off the relay contact rs of the discharge circuit 7 during the TI period of measuring the voltage v1 at the measurement target point, and during the T2 period of measuring the voltage v2 following this.

前記実施例は被試験体とされる計測対象点が、プリント
基板組立体の場合を引例しているが1本発明の電圧測定
誤差防止回路は、これに限定されず。
Although the above-mentioned embodiment cites the case where the measurement target point, which is the test object, is a printed circuit board assembly, the voltage measurement error prevention circuit of the present invention is not limited to this.

例えば高抵抗の入力インピーダンスを有するA−D変換
器によって多数の電子部品の動作電圧を同時にチェック
するような広汎な試験に適用して有効である。
For example, it is effective when applied to a wide range of tests in which the operating voltages of a large number of electronic components are checked simultaneously using an A-D converter having a high resistance input impedance.

〔発明の効果〕〔Effect of the invention〕

以上説明した本発明の電圧測定誤差防止回路によれば、
直流電圧測定の高信頼化が図られ、また多数のチェック
ポイントを有する動作状態下のプリント基板回路等の試
験が迅速に施行されると云う顕著な効果がある。
According to the voltage measurement error prevention circuit of the present invention explained above,
This method has the remarkable effect of increasing the reliability of DC voltage measurement and quickly testing printed circuit board circuits and the like under operating conditions that have multiple checkpoints.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の電圧測定誤差防止回路実施例とするブ
ロック回路図。 第2図は第1図放電防止回路の動作タイムチャート。 第3図は従来の電圧計測回路ブロック図。 第4図は電圧計測時のタイムチャート。 図中、7は本発明の放電回路。 9は^−D変換器の入力端子。 10は計測入力母線(入力母′fa)。 LL 12.13.・−・・、nは計測対象点。 MPXはマルチプレクサ。 本迄明電斤銀lJ芝訊嗟1方止回望ト寅施イ列のプロ・
・ツク図第 1 図 ィL尤の電圧、8”l’r則固酪プロ・、フb]第 3
 図 電圧11°」時の%ムフヤーヒ 第 48己
FIG. 1 is a block circuit diagram of an embodiment of the voltage measurement error prevention circuit of the present invention. FIG. 2 is an operation time chart of the discharge prevention circuit shown in FIG. 1. FIG. 3 is a block diagram of a conventional voltage measurement circuit. Figure 4 is a time chart during voltage measurement. In the figure, 7 is a discharge circuit of the present invention. 9 is the input terminal of the ^-D converter. 10 is a measurement input bus (input bus 'fa). LL 12.13. ..., n is the measurement target point. MPX is a multiplexer. Until now, Meiden Co., Ltd. has been a professional in the series of
・Tsuku diagram No. 1 Diagram L's voltage, 8"l'r law hard power pro., Fb] No. 3
Figure Voltage 11° % Mukhyahi No. 48

Claims (1)

【特許請求の範囲】[Claims]  被試験体の直流電圧をマルチプレクサによって順次切
り替え、これをA−D変換器に入力して多数の計測対象
点の電圧を計測するに当たり、A−D変換器の入力回路
に開閉素子と抵抗からなる放電回路が設けられ、電圧計
測前、マルチプレクサの切り替え周期と同じ周期で開閉
素子を閉止することにより、入力回路の残留電荷を除去
することを特徴とする電圧測定誤差防止回路。
In order to sequentially switch the DC voltage of the test object using a multiplexer and input it to an A-D converter to measure the voltage at a large number of measurement points, the input circuit of the A-D converter consists of a switching element and a resistor. A voltage measurement error prevention circuit characterized in that a discharge circuit is provided, and residual charge in an input circuit is removed by closing a switching element at the same cycle as a switching cycle of a multiplexer before voltage measurement.
JP3890287A 1987-02-20 1987-02-20 Error preventing circuit for voltage measurement Pending JPS63205572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3890287A JPS63205572A (en) 1987-02-20 1987-02-20 Error preventing circuit for voltage measurement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3890287A JPS63205572A (en) 1987-02-20 1987-02-20 Error preventing circuit for voltage measurement

Publications (1)

Publication Number Publication Date
JPS63205572A true JPS63205572A (en) 1988-08-25

Family

ID=12538123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3890287A Pending JPS63205572A (en) 1987-02-20 1987-02-20 Error preventing circuit for voltage measurement

Country Status (1)

Country Link
JP (1) JPS63205572A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014028027A (en) * 2012-07-31 2014-02-13 Toshiba Corp Ultrasonic diagnostic apparatus, switching control program and switching control method
WO2023139678A1 (en) * 2022-01-19 2023-07-27 株式会社ソシオネクスト Reference voltage generation circuit and semiconductor integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4883891A (en) * 1972-01-21 1973-11-08
JPS6162873A (en) * 1984-09-04 1986-03-31 Yokogawa Medical Syst Ltd Multipoint current measuring apparatus
JPS6179170A (en) * 1984-09-27 1986-04-22 Mitsui Toatsu Chem Inc Method and device for measuring multipoint input

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4883891A (en) * 1972-01-21 1973-11-08
JPS6162873A (en) * 1984-09-04 1986-03-31 Yokogawa Medical Syst Ltd Multipoint current measuring apparatus
JPS6179170A (en) * 1984-09-27 1986-04-22 Mitsui Toatsu Chem Inc Method and device for measuring multipoint input

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014028027A (en) * 2012-07-31 2014-02-13 Toshiba Corp Ultrasonic diagnostic apparatus, switching control program and switching control method
WO2023139678A1 (en) * 2022-01-19 2023-07-27 株式会社ソシオネクスト Reference voltage generation circuit and semiconductor integrated circuit

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