JPS63204919A - Pseudo-random number generation circuit - Google Patents

Abstract

PURPOSE:To generate various pseudo-random numbers having different periods and generation systems in a same pseudo-random number generation circuit by altering the selection control signals of respective selectors so as to change the connection pattern of exclusive 'OR' elements and altering the feedback condition for the lowest rank flip flop in the respective states of flip flops connected in series. CONSTITUTION:At first the specified selection control signals are given to selection control signal input terminals 6a-6g and it is set, for example, that the selectors 5b, 5c and 5e select an (x) side and the selectors 5a, 5d, 5f and 5g select a (y) side. If other selection control signals are given to the selection control signal input terminals 6a-6g, the selectors 5a-5g are set in different selection patterns according to the selection control signals and the signal system of feedback signals which execute the feedback to the lowest rank flip flop 1a corresponding to the set selection patterns of the selectors 5a-5g is decided, so that the period and the generation system of the pseudo-random number outputted from the pseudo-random number output terminal 4 of the highest rank flip flop 1h are decided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pseudorandom number generation circuit that generates a test sequence when testing a large-scale integrated circuit (LSI).

[Prior art] Figure 2 is, for example, "Nikkei Electronics, June 1983.
It is a block diagram showing a conventional pseudo-scattering generation circuit shown in "Monthly 20th issue" (published by Nikkei McGraw-Hill), and in the figure, ■a to 1h are flip-flops connected in series, 2b, 2c, 2e are the flip-flops 1a to 1h
3 is a flip-flop] A clock input terminal to which the clock signal of a=1h is input; 4 is a top flip-flop 1h
This is a pseudo-random number output terminal. These flip-flops are la~! h and exclusive OR elements 2b, 2c, and 2e form a linear feedback shift register.

Next, the operation will be explained. 8 flip flops I
By connecting a to Ih in series, an 8-bit shift register is constructed. Therefore, when a clock signal is input to the clock input terminal 3, the state of each flip-flop Ia to 1g is changed to the north flip-flop 1b to 1h.
will be shifted sequentially. Here, the flip-flop l
The outputs of h and Ie are subjected to an exclusive OR by an exclusive OR element 2e, and then the output of this exclusive OR element 2e is subjected to an exclusive OR by an exclusive OR with the output of the flip-flop Ic. The sum is taken, and the output of this exclusive OR element 2C is further exclusive ORed with the output of the flip-flop lb by an exclusive OR element 2b. The output of the exclusive OR element 2b is fed back to the input terminal of the lowest flip-flop Ia. With such feedback applied, by applying the same clock signal from the clock input terminal 3 to the flip-flops 1a to 1h, the input terminal of the flip-flop la receives the state of the flip-flops lh, lc, and Ib at that time. Corresponding signals are input and are successively shifted to upper flip-flops 1b-1h.

Therefore, a pseudorandom number having a period of (2@-1) is output from the pseudorandom number output terminal 4 of the flip-flop 1h.

[Problems to be solved by the invention] Since the conventional pseudo-random number generation circuit is configured as described above, the period and generation sequence of the generated pseudo-random numbers are fixed, and the period and generation sequence of the generated pseudo-random numbers are fixed. When pseudorandom numbers are required, there are problems such as the need to create separate pseudorandom number generation circuits using linear feedback shift registers each having a predetermined number of bits.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a pseudo-random number generation circuit that can generate pseudo-random numbers with different cycles and generation sequences using a single pseudo-random number generation circuit. do.

[Means for Solving the Problems] A pseudo-random number generation circuit according to the present invention has a plurality of flip-flops connected in series, and the output terminal of the flip-flop is connected to one of the plurality of exclusive OR elements. The other input terminal of each exclusive OR element is connected to the input terminal of the exclusive OR element, and the selector receives either a signal from the upper exclusive OR element or a signal bypassing the exclusive OR element. At the same time, the selector selects and feeds back either the signal from the lowest exclusive OR element or the signal bypassing that exclusive OR element to the input terminal of the lowest flip-flop. It is something to do.

[Operation] In the pseudo-random number generation circuit of the present invention, when the selection control signal of each selector is changed, the connection pattern of the exclusive OR element is changed, and the state of each flip-flop connected in series is changed to the lowest flip-flop. Since the conditions for feeding back to the selector change, pseudorandom numbers with different cycles and generation sequences are generated in response to the selection control signal to the selector.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figure, 1a=1h is the flip 7 connected in series.
Numerals 0 and 2a to 2g are exclusive OR elements whose input terminals are respectively connected to the output terminals of the flip-flops 1a to 1g, 3 is a clock input terminal, and 4 is a pseudorandom number output terminal. The other input terminal of the logical OR element 2g is connected to the output terminal of the flip-flop lh. In addition, 5b to 5g are lower exclusive OR elements 2
Exclusive OR elements 2b to 2f are connected to the other input terminals of 3 to 2f.
A selector for selecting which of the signals output from 2g (X side) and the signal bypassing exclusive OR elements 2b to 2g (y side) is input; 5a is the output from exclusive OR element 2a. The selectors 6a to 6g select which of the input signal (X side) and the signal bypassing the exclusive OR element 2a (y side) is fed back to the input terminal of the lowest flip-flop la. This is a selection control signal input terminal that provides a selection control signal to the selectors 5a to 5g.

Next, the operation will be explained. Prior to the generation of pseudo-random numbers, first a predetermined selection control signal is applied to the selection control signal input terminals 6a to 6g, and for example, the selectors 5b, 5c, and 5e
side, selectors 5a, 5d.

Set so that 5f and 5g select the y side. As a result, the outputs of the flip-flops Ih and le are combined with the exclusive OR element 2e, and the output of the exclusive OR element 2e and the output of the flip-flop lc are combined with the exclusive OR element 2c.
Furthermore, the output of this exclusive OR element 2c and the flip-flop 1b are combined by the exclusive OR element 2b,
An exclusive OR is taken for each, and the output of the exclusive OR element 2b is fed back to the lowest flip-flop 1a. Therefore, this pseudo-random number generation circuit has the same configuration as the conventional one shown in FIG. (
Outputs a pseudo-random number with a period of 2"-1).

Further, if another selection control signal is applied to the selection input terminals 6a to 6g, the selectors 5a to 5g can be controlled according to the selection control signal.
5g is set to a different selection pattern, and a signal sequence of a feedback signal to be fed back to the lowest flip-flop Ia is determined in accordance with the set selection pattern of the selectors 5a to 5g. The period and generation sequence of the pseudorandom numbers output from the pseudorandom number output terminal 4 are determined.

In the above embodiment, the selection control signal input terminals are provided in l-to-l correspondence with the selectors, but the selection control signal input terminals may also be supplied with signals from the output of the encoder or the output of the shift register. Well, in that case, the external terminals can be reduced.

[Effects of the Invention] As described above, according to the present invention, the connection pattern of the exclusive OR element is changed by changing the selection control signal of each selector, and the lowest flip-flop of each state of the flip-flops connected in series is changed. Since the configuration is configured to change the feedback conditions to the selector, it is possible to generate various pseudo-random numbers with different cycles and generation sequences using the same pseudo-random number generation circuit simply by changing the selection control signal to the selector. It has the effect of

[Brief explanation of the drawing]

FIG. 11iii is a block diagram showing a pseudo-random number generation circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional pseudo-random number generation circuit. 1a=1h are flip-flops, 2a to 2g are exclusive OR elements, 3 is a clock input terminal, 4 is a pseudorandom number output terminal, 5a to 5g are selectors, and 6a to 6g are selection control signal input terminals. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. (2 others)

Claims (1)

[Claims] a plurality of flip-flops connected in series; a plurality of exclusive OR elements each having an output terminal of the flip-flop connected to one of its input terminals; and an input to the other input terminal of the exclusive OR element. a selector for selecting whether or not to cause a signal to be fed back to the flip-flop at the lowest level to bypass the exclusive OR element at the lowest level; A pseudo-random number generation circuit includes selectors that select the , and a selection control signal input terminal that provides a selection control signal to these selectors.