JPS63204131A - Apparatus for controlling cumulative time of photoelectric converter element array - Google Patents

Abstract

PURPOSE:To automate control and to make output voltage constant, by feeding back the frequency clock corresponding to the output voltage of an integration circuit to a drive circuit to control the cumulative time of a photoelectric converter element. CONSTITUTION:In order to obtain the max. value of the sensor signal 101 generated from a photoelectric converter element array 1 by a drive circuit 2, a peak holding circuit 3 and a sample holding circuit 4 are reset in synchronous relation to the frame pulse 102 of the drive circuit 2 and the output of the circuit 4 is compared with the optimum reference value 6 by a comparator 5 to send deviation to an integrator 7 and deviation voltage integrated timewise is converted to frequency by a V/F converter 8 to form a fundamental clock which is, in turn, fed back to the drive circuit 2. By this method, the max. value of the sensor signal 101 is controlled so that the difference between the optimum reference value 6 and the output of the circuit 4 becomes min. to bring the output of the circuit 4 to the same value as the optimum reference value 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to the MT of a lens using a photoelectric conversion element array.
The present invention relates to a charge accumulation time control device for a photoelectric conversion element in an F (modulation transfer function) inspection device.

[Prior Art] As a photoelectric conversion element array, a photo array sensor, for example, a CCD array sensor, is usually used.

In the MTF inspection apparatus, images projected by a lens to be tested are formed on a plurality of photo array sensors, and the MTF value of the lens to be tested is measured. At this time, the charge accumulation time of each photoarray sensor is controlled in order to optimize the output of each photoarray sensor.

Conventionally, this type of accumulation time control device was disclosed in Japanese Patent Application Laid-open No. 58
There is one described in JP-92837. In the device described in this Japanese Patent Application Laid-open No. 58-92837, the seventh
As shown in the figure, a new accumulation time T3 is set in the register (prescaler) 28 by the read instruction signal 102,
The data 104 corresponding to the accumulation time T3 is added to the counter 27 to obtain a pulse 105, and the delay type flip-flop D-F-F31 is set.

Following the signal 102, a readout start instruction signal 100 for the CCD sensors 20 to 22 is generated, and this is input to the flip-flop D-F-F19 and output at the timing of the pulse 107, thereby generating the signal 1 synchronized with the pulse 105.
Generate 09. Then, the flip-flop DF-
After delaying the pulse 105 by the pulse interval (one cycle of the accumulation period) by F30, the flip-flop D-F
- F30's Q output causes flip-flop D-F・F3
1, and the Q of flip-flop D-F-F31
A signal 112 is obtained as an output. By inputting the signals 109 and 112 to the AND gate 32, the CCD readout start signal 108 is generated after one cycle of the new accumulation time has elapsed.
is generated and the actual read operation begins. counter 2
The signal 101 supplied to CCD sensor 7 is a shift clock pulse of CCD sensors 20 to 22.

[Problems to be Solved by the Invention] In such a conventional device, an operation (signal 103) for setting the accumulation time is required, and in order to determine the optimum accumulation time, it is necessary to set the optimum accumulation time using a control program or the like. A decision needs to be made. The reason for this is that the amount of COD incident light cannot be known in advance.

The present invention solves the above problems and provides a device that automatically controls the accumulation time so as to obtain the optimal value of the photo array sensor output. An object of the present invention is to provide an accumulation time control device for a photoelectric conversion element array that can control time.

[Means and effects for solving the problems] The present invention provides an accumulation time control device for a photoelectric conversion element array, which uses a charge storage type photoelectric conversion element array and a photoelectric conversion signal from the photoelectric conversion element array in a time-series manner. a peak hold circuit that holds the peak value of the photoelectric conversion output signal; a sample hold circuit that holds the output peak value of the peak hold circuit for a certain period of time; A comparator that compares the output of the sample and hold circuit, an integration circuit that integrates the output of this comparator, and a V/F converter that generates a frequency clock corresponding to the output voltage of this integration circuit. The frequency clock is fed back to the drive circuit, and the accumulation time of the photoelectric conversion element array is controlled by this frequency clock.

The invention will be explained with reference to the drawings.

The storage time control device for a photoelectric conversion element array according to the present invention shown in FIG. Comparator 5 via circuit 4
The frame pulse output side of the drive circuit 2 is connected to the peak hold circuit 3 and the sample hold circuit 4, respectively, and the output side of the comparator 5 is connected to the V /F (voltage/frequency) converter 8, and the output side of this V/F converter 8 is fed back to the drive circuit 2. Further, the other input side of the comparator 5 is supplied with a voltage having an optimum reference value corresponding to a constant output.

FIG. 2 shows the operation timing of the photo array sensor 1 and the drive circuit 2.

The operation of the storage time control device for a photoelectric conversion element array of the present invention constructed as described above is as follows.

The photoarray sensor 1 is driven by a drive circuit 2 and generates a sensor signal 101 (FIG. 2). This sensor signal 10
In order to obtain a peak value of 1, the peak hold circuit 3 and the sample hold circuit 4 that holds the peak value for 1 frame are reset in synchronization with the frame pulse 102 from the drive circuit 2. The sample and hold circuit 4 is used to hold the value of the previous frame until the peaks for one frame are determined. The output of the sample and hold circuit 4 is compared with an optimum reference value 6 by a comparator 5, and the deviation thereof is supplied to an integrator 7. This optimum reference value 6 is set to, for example, 80% of the output range of the photoarray sensor 1. The deviation voltage integrated over time by the integrator 7 is converted into a frequency by the V/F converter 8 to form the basic clock 103 of the photo array sensor l,
This is fed back to the drive circuit 2. This basic clock 103 is important for determining the storage time of the photoarray sensor 1. In this way, in the present invention, a closed loop is constructed using the V/F converter 8, and the maximum value of the sensor signal 101 is adjusted by this closed loop so that the difference between the optimal reference value 6 and the output of the sample and hold circuit 4 is minimized. The value is controlled to be the same as the optimum reference value 6.

Figure 2 shows the waveform. The sensor signal 101 is a time-series signal output in proportion to the amount of light received by the photoarray sensor 1.

Further, the frame pulse 102 is a pulse corresponding to one cycle of the sensor signal, and this one cycle is an accumulation time; if this time is made long, the sensor signal becomes large, and if this time is made short, the sensor signal becomes small.

(First Embodiment) Next, a first embodiment of the storage time control device for a photoelectric conversion element array according to the present invention is shown in FIG. 3.

In this example, the configuration of the peak hold circuit 3, sample hold circuit 4, comparator 5, and integrator 7 among the circuit elements shown in FIG. 1 will be shown in detail.

The photo array sensor 1 is, for example, a device such as a CCD sensor, and the drive circuit 2 generates timing pulses and the like necessary for the photo array sensor 1. The peak hold circuit 3 includes a buffer Bin diode D, a hold H1, and a switch SW1. The buffer B1 is composed of, for example, an OP amplifier, and converts the impedance of the sensor signal 101. Diode D is an element through which only forward current flows,
The hold H1 is composed of a capacitor or the like, and is configured to store voltage for a certain period of time. The switch SW+ is configured with a relay or an analog switch, and thereby resets the voltage of the hold H1. The pulse detector 11 is
It is composed of a mono-multivibrator or the like, detects the falling edge of the frame pulse 102, and supplies a reset pulse to the switch SW1. The sample hole circuit 4 is composed of a buffer B2, a switch sw2, and a hold H2.
Buffer B2 is composed of, for example, an OP amplifier, and performs impedance conversion of the signal from peak hold circuit 3. The hold H2 is composed of a capacitor or the like, and is configured to store voltage for a certain period of time. switch S
W2 is composed of a relay or an analog switch, and can be opened and closed by the output of the pulse detector 12. The pulse detector 12 is composed of a mono-multivibrator, etc., and detects the rising edge of the frame pulse and activates the switch SW.
A signal is supplied to 2. The reference voltage generator IO is composed of a resistor or a Zener diode, and thereby generates a constant voltage. The operational integrator 9 is an OP amplifier OPI.
and an integrating capacitor C, etc., and has the function of comparing and adding the signal from the sample hold 4 and the signal from the reference voltage generator IO using resistors R7 and R2, and further integrating the signal. The V/F converter has a function of outputting a frequency pulse corresponding to the voltage, and generates a basic clock 103 corresponding to the voltage from the arithmetic integrator 9.

The operation of the storage time control device of the present invention constructed as described above is as follows.

The photo array sensor 1 is driven by a drive circuit 2 and generates a sensor signal 101. The peak hold circuit 3 is reset by the output of the pulse detector 11 in order to find the value at which the sensor signal 101 becomes maximum in one frame of the frame pulse 102. Since the peak hold circuit 3 determines the peak at the end of 1 frame, it is necessary to use the sample hold circuit 4 to hold the peak value of one frame before. The timing of this holding is determined by the pulse detector 12. After the sample hold circuit 4 is held by the pulse detector 11 and the pulse detector 12, it is necessary to reset the peak hold circuit 3. Therefore, the falling edge of the frame pulse 102 is detected by the pulse detector 11, and The rising edge is detected by the pulse detector 12. In order to make the value at which the sensor signal 101 obtained from the sample and hold circuit 4 reaches a maximum constant value, the signal from the reference voltage generator 10 (reference value) and the signal from the sample and hold circuit 4 are combined by an arithmetic integrator 9. Subtraction (the arithmetic integrator 9 is an adder, but if the output of the reference voltage generator 10 is made negative, it becomes a subtraction), the deviation is integrated over time, and the V/F
Converter 8 converts voltage to frequency and converts basic clock 10
3 is generated. This basic clock 103
is fed back to the drive circuit 2 so that the signal from the sample and hold circuit 4 becomes equal to the signal from the reference voltage generator 10.

Therefore, according to the present invention, the signal from the photoarray sensor 1 can be automatically made constant.

The peak hold circuit 3 can also be configured with two buffers and two diodes. Further, the sample and hold circuit 4 can also be configured into a feedback loop using two buffers.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In this example, the only difference is the configuration of the reference voltage generator 10 from the first embodiment shown in FIG. 3, and the other configurations are the same as in the first embodiment. Explain. That is, the D/A converter 13 has a function of converting a digital quantity into an analog quantity, and outputs the digital quantity given from the DATA bus as a reference voltage as an analog quantity.

In this example, the D/A converter 13 is used to enable the reference voltage to be set externally, thereby forming an input signal to the arithmetic integrator 90. Other operations are exactly the same as in the first embodiment. Therefore, the sensor signal 101 from the photoarray sensor 1 can be digitally controlled from the outside. Digital sensor signal 102
It can be shown by the voltage corresponding to

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. In the first and second embodiments, the comparator 5 and the integrator 7 process analog signals, but in this example, these circuit elements 5 and 7 process digital signals.

That is, a comparator 16 for A/D conversion is used as a comparator, a counter 14 is connected to its output side, a digital quantity/frequency (D/F) converter 19 is connected to the output side of this counter 14, and the The output side is connected to the drive circuit 2. Further, the frame pulse 102 of the drive circuit 2 is supplied to the clock input terminal of the counter 14. The D/F converter 19 includes a D/A converter 15 and a V/F converter 8. Therefore, in this example, the integrator 7 is configured with a counter 14. The comparator 16 compares the signal from the sample and hold circuit 4 with the signal from the reference voltage generator 10, determines the magnitude thereof, and supplies a corresponding binary output (digital amount) to the counter 14. The counter 14 is composed of an up/down counter,
According to the signal from the comparator 16, the Arab value of the counter value is
Perform down counting. This up/down timing is determined by the frame pulse 102. The counted value here is converted from a digital quantity to an analog quantity by the D/A converter 15 and is supplied to the V/F converter 8. The other configurations are completely the same as the first embodiment.

In this example, in order to compare the reference voltage of the reference voltage generator 10 and the maximum value of the sensor signal 101 of the sample hold circuit 4, both are supplied to the comparator 16 to determine their magnitude. According to this determination, a signal from the comparator 16 is supplied to the up/down counting switching input side of the counter 14 in order to cause the counter 14 to perform an integrating operation. The counting operation is performed using frame pulses 102. The counted value is supplied to the D/A converter 15 to convert it into an analog quantity, and its output is supplied to the V/F converter 8.

- As mentioned above, in this example, the integration operation is performed by a digital circuit synchronized with the frame pulse.

Other operations are similar to those in the first embodiment.

According to this example, there is no need to set the time constant of the integrating capacitor, and the operating range is significantly expanded.

In the third embodiment, the D/F converter 19 consists of the V/F converter 8 and the D/A converter 15, but it can be easily replaced with a structure of a clock generator and a counter.

(Fourth example) Finally, a fourth embodiment of the present invention will be explained with reference to FIG.

This example differs from the third example in that a flip-flop 17 and an AND circuit 18 are provided between the comparator 16 and the counter 14 of the third example shown in FIG. That is, the flip-flop 17 is composed of an R@S flip-flop, etc., and is set (reset) at the rise, rise, and fall of the magnitude signal from the comparator 16, and is reset (set) by the external trigger 104. do it like this.

The output of the flip-flop 17 is supplied to one input side of an AND circuit 18. AND circuit 18 is frame pulse 1
02 is turned on and off of the flip-flop 17 and is supplied to the counter 14. The other configurations are completely the same as the third embodiment.

In this example, in order to control the counter operation input (ck) of the counter 14 with a trigger 104 controlled from the outside, a signal is generated by a flip-flop 17 until it is set by the trigger 104 and reset by a match signal from the comparator 16. . The AND circuit 18 uses this signal to turn on the gate.
OFF, thereby controlling the frame pulse 102. It is only necessary to detect the rise and fall of the pulse based on the coincidence signal from the comparator 16, and the entire operation is performed by the photo array sensor l only when the trigger 104 is applied.
After that, the basic clock (accumulation time) at that point in time can be maintained. The other configurations are completely the same as the third embodiment.

According to this example, the storage time can be changed only when necessary, and therefore it can be used in systems where fluctuations in the storage time are a problem.

[Effects of the Invention] As is clear from the above, according to the present invention, in a device that obtains a constant output by controlling the accumulation time of a photoarray sensor, a desired constant output voltage can be obtained without setting the accumulation time from the outside. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the storage time control device for a photoelectric conversion element array according to the present invention. FIG. 2 is a waveform diagram showing the operation timing of the photoarray sensor and the drive circuit. A connection circuit diagram showing a first embodiment of the storage time control device for a conversion element array, and FIGS. 4, 5, and 6 are connection circuit diagrams showing the second, third, and fourth embodiments, respectively. FIG. 7 is a connection circuit diagram showing the configuration of a conventional storage time control device for a photoelectric conversion element array. 2... Drive circuit 3... Pink hold circuit 4... Sample hold circuit 5.16... Comparator 6... Reference value 7... Integrator 8... V/F converter 9. ...Arithmetic integrator 10...Reference voltage generator 11.12...Pulse detector 13...D/A converter 14...Counter 15...D/A converter 17...Flip-flop 18 ...AND circuit 19... D/F converter patent applicant Olympus Optical Industry Co., Ltd. Procedural amendment (voluntary) May 26, 1985 1, Incident indication 1988 Patent Application No. 36439 2, Name of the invention: Accumulation time control device for photoelectric conversion element array 3, Relationship with the case of the person making the amendment Patent application Location: 2-43-2-4 Hatagaya, Shibuya-ku, Tokyo, Agent 5, Subject of the amendment ( 1) Column 6 of "Claims" of the specification, contents of amendment (1) The claims of the specification are amended as shown in the attached sheet. (2) "Provider" written on page 4, line 15 of the specification is amended to "provide". (3) Correct the ``caranta 14J'' written on page 13, line 14 of the specification as ``r counter 14''. 7. List of attached documents (1) Attachment l Attachment Sheet 2, Claims (1) Charge storage type photoelectric conversion element array and photoelectric conversion signals from this photoelectric conversion element array read in time series a peak hold circuit that holds the peak value of the photoelectric conversion output signal; a sample hold circuit that holds the output peak value of the peak hold circuit for a certain period of time; and a reference value corresponding to the constant output and the sample hold circuit. A comparator that compares the outputs of the circuit, an integration circuit that integrates the output of the comparator, and a V/F converter that generates a frequency clock corresponding to the output voltage of the integration circuit, the frequency clock being driven by the frequency clock. A storage time control device for a photoelectric conversion element array, characterized in that the frequency clock is fed back to a circuit and the storage time of the photoelectric conversion element array is controlled by this frequency clock.

Claims (1)

[Claims] (1) a charge storage type photoelectric conversion element array, a drive circuit that reads out photoelectric conversion signals from the photoelectric conversion element array in time series, and a peak hold circuit that holds the peak value of the photoelectric conversion output signal; a sample hold circuit that holds the output peak value of this peak hold circuit for a certain period of time;
A comparator that compares a reference value corresponding to a constant output and the output of the sample-and-hold circuit, an integrating circuit that integrates the output of this comparator, and a V/F that generates a frequency clock corresponding to the output voltage of this integrating circuit. converter, the frequency clock is fed back to the drive circuit, and the storage time of the photoelectric conversion element array is controlled by the frequency clock.