JPS63202792A - Thin film transistor matrix - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a thin film transistor (TPT) matrix liquid crystal display device in which protective insulation is provided on the drain bus line in order to prevent the voltage of the drain bus line from affecting the pixel electrode. By forming a conductive film through the film,
The potential of the pixel electrode is not affected by the voltage of the drain bus line.

[Industrial application field]

The present invention relates to the structure of a TPT matrix liquid crystal display device, and in particular to a TPT matrix.

[Conventional technology]

To obtain a clear image, it is necessary to accurately control the voltage of the pixel electrode. However, capacitive coupling with the pass line occurs, causing the voltage of the pixel electrode to fluctuate.

Therefore, a structure is required to suppress voltage fluctuations of the pixel electrode.

FIG. 3(a) is a diagram showing the structure of a conventional TPT matrix, in which l is a glass substrate, 2 is a drain bus line,
3 is a gate bus line, 4 is a TFT.

5 is a pixel electrode. As shown in the figure, conventional TPT
The matrix has a structure in which drain bus lines 2 and pixel electrodes 5 are arranged close to each other.

Therefore, a capacitance CDs is generated between the pixel electrode 5 and the drain bus line 2.

As seen in the same figure (b), this capacitance C0 consists of one capacitance component CD31 between the surfaces of the pixel electrode 5 and the drain bus line 2, and a capacitance component Cost between the back surfaces, and therefore, Cos'' It is expressed as Co51 + Co5t.

The drain bus line 2 and the pixel electrode 5 are coupled by the capacitor C83, and the potential of the pixel electrode 5 easily changes due to a change in the voltage of the drain bus line 2.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional TPT matrix configuration, the capacitance COS between the pixel electrode 5 and the drain bus line 2 includes two capacitance components, so its value becomes large, and therefore the potential of the pixel electrode 5 increases. The problem is that it is easily affected by changes in drain voltage.

An object of the present invention is to reduce the capacitance between a pixel electrode and a drain bus line, and to prevent voltage fluctuations of the pixel electrode due to the potential of the drain bus line.

[Means for solving problems]

In the present invention, as shown in FIGS. 1(a) and 1(b), a conductive layer is placed on a drain bus line 2 formed on an insulating substrate such as a glass substrate 1 via a protective insulating film 6. A film 7 is formed, and the conductive film 7 is connected to the ground terminal, so that the conductive film is always kept at a low potential to function as a shield film.

I made it. In addition, 4 is TPT, said FIG. 1 (bl is a sectional view of the part shown by the dashed-dotted line A of the same figure (a).

[For production]

Since the conductive film 7 is connected to the ground terminal, its potential is always maintained at the ground potential. Therefore, the conductive film 7 acts as a shield film between the pixel electrode 5 and the drain bus line 2, and the capacitance component cost disappears from the capacitance C□ between the two, leaving only the capacitance component C02 between the back surfaces.

The magnitude of these two capacitance components is the dielectric constant ε of the glass that constitutes Cost! #4, whereas the dielectric constant ε1 of the liquid crystal constituting cost is J+! Since CaS+ is about three times as large as c' o s *, by eliminating this, the capacitance C9 between the pixel electrode 5 and the drain bus line 2 is reduced to about 1/4 of the conventional value. Decrease. Therefore, the influence of the potential VD of the drain bus line 2 on the potential VtC of the pixel electrode 5 becomes very small.
Undesirable voltage fluctuations are suppressed and good image quality is obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 2(a) to (1).
This will be explained along with its manufacturing process. Note that, like FIG. 1(b), this figure is a sectional view of the portion indicated by the dashed line A in FIG. 1(a).

First, as shown in FIG.
The aluminum substrate is coated with chromium (Cr) with a thickness of approximately 1000 mm.
) layer and about 1000 aluminum (/l) layers, and a gate bus line (not shown) is selectively formed.

Next, as shown in FIG. 2B, a protective insulating film 6 such as a polyimide film having a thickness of about 1 μm is coated thereon.

Next, as shown in FIG. 2C, a resist film 8 is formed on the protective insulating film 6 to cover the upper part of the drain bus line 2.

Next, as shown in +d) of the same figure, using the resist film 8 as a mask, plasma etching is performed using oxygen (0□) to select the exposed parts of the protective insulating film 6, that is, unnecessary parts other than on the drain bus line 2. to remove. After this, the resist film 8 is removed.

Next, as shown in FIG. 5E, a resist film 9 is formed to cover the area other than the area where the pixel electrode 5 is formed.

Next, as shown in the same figure (n), indium tin oxide (
ITO) F! 110 is formed, and then the resist film 9 is
on the resist film 9 by removing.

Unnecessary portions of the deposited 170 layers 10 are removed at the same time.

Next, as shown in FIG. 7G, a resist film 11 for patterning the conductive film 7 is formed on the conductive film 7.

Next, as shown in FIG. 11(1), the exposed portions of the conductive film 7 are selectively removed using the resist film 11 as a mask to separate the conductive film 7 so that it remains only above each drain bus line 2. Although not shown, the separated conductive film 7 is connected to a ground terminal. After this, the resist film 11 used as the mask is removed.

As described above, in the TPT matrix obtained as described above, each drain line 2 is covered with a conductive film 7 via a protective insulating film 6, and this conductive film 7 is connected to the ground terminal. . Therefore, since the conductive film 7 is always kept at O potential, the pixel electrode 5 and the drain bus line 2 are shielded by the conductive film 7. potential v0 of
Clear image quality can be obtained without being affected by fluctuations in the image quality.

Note that the present invention is applicable to both staggered and inverted staggered thin film transistor matrices.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to suppress the voltage fluctuation of the pixel electrode due to capacitive coupling, and it is possible to perform fine voltage control to obtain a clear image.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are diagrams explaining the principle of the present invention. Figure 2 (al~<1) is an explanatory diagram of one embodiment of the present invention;
The figure is a waveform diagram showing voltages at various parts in the above embodiment, and FIGS. 4(a) and 4(b) are explanatory diagrams of a conventional TPT matrix. In the figure, l is an insulating substrate, 2 is a drain bus line, 3 is a gate bus line, and 4 is a TFT. 5 is a pixel electrode, 6 is a protective insulating film, and 7 is a conductive film)Principle of the present invention d light m Figure 1, f invention - Brahma White column question flash Figure 2 present invention - Q? J Kanmei Close Figure 2 Iktada Reidencho ni shape m Figure 3 CD! =CD5 ↑Co52 4White 1zTFT7Lsu7S DramaHereAUaGoFigure 4

Claims (1)

[Scope of Claims] Thin film transistors (4) corresponding to pixels arranged in a matrix on a transparent insulating substrate (1), pixel electrodes (5) of display cells driven by the thin film transistors, and pixel electrodes (5) in the row direction of the pixels. In a thin film transistor matrix comprising a gate bus line (3) arranged in the column direction and a drain bus line (2) arranged in the column direction, a protective insulating film (6) is provided on the drain bus line (2). A thin film transistor matrix, characterized in that a conductive film (7) is formed in a thin film, and the conductive film is connected to a ground potential to serve as a shield film.