JPS6320246U - - Google Patents
Info
- Publication number
- JPS6320246U JPS6320246U JP11201586U JP11201586U JPS6320246U JP S6320246 U JPS6320246 U JP S6320246U JP 11201586 U JP11201586 U JP 11201586U JP 11201586 U JP11201586 U JP 11201586U JP S6320246 U JPS6320246 U JP S6320246U
- Authority
- JP
- Japan
- Prior art keywords
- reset signal
- circuit
- capacitor
- output
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000012544 monitoring process Methods 0.000 claims 2
- 230000002159 abnormal effect Effects 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は従来例を示す回路図である。
１……ＣＰＵ、３１……コンデンサ、３２……
抵抗、３３……バツフア回路、３４……インバー
タ、３５……ダイオード、３６……制御回路、３
７……コンデンサ、３８……インバータ、３９…
…抵抗、４０……リセツト信号出力回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1...CPU, 31...Capacitor, 32...
Resistor, 33... Buffer circuit, 34... Inverter, 35... Diode, 36... Control circuit, 3
7... Capacitor, 38... Inverter, 39...
...Resistor, 40...Reset signal output circuit.
Claims (1)
グラムラン信号を入力し、該プログラムラン信号
の異常時にリセツト信号をＣＰＵに出力してＣＰ
ＵをリセツトするＣＰＵの暴走監視回路において
、ＣＰＵのプログラムラン信号出力端子と基準電
位出力端子との間にコンデンサと抵抗とを直列に
介在させたバツフア回路と、抵抗とインバータと
を並列に接続した回路とコンデンサとを直列に接
続したリセツト信号出力回路と、前記バツフア回
路のコンデンサと抵抗との接続点と前記リセツト
信号出力回路の抵抗及びインバータとコンデンサ
との接続点との間に接続され、ダイオードを含ん
でなる制御回路とを備えて構成され、バツフア回
路のコンデンサと抵抗との接続点の電位が基準電
位出力端子の電位と等しい時には、制御回路がリ
セツト信号出力回路との導通を遮断して、リセツ
ト信号出力回路のコンデンサを充放電を繰り返す
ことによりインバータの出力端子から周期的にリ
セツト信号を出力させ、前記接続点の電位が基準
電位出力端子の電位と異なる時には、制御回路が
リセツト信号回路と導通してリセツト信号出力回
路のコンデンサの端子電圧を一定に保持させて、
リセツト信号出力回路からのリセツト信号の出力
を停止させるようにしたことを特徴とするＣＰＵ
の暴走監視回路。 A program run signal that is periodically output when the CPU is operating normally is input, and a reset signal is output to the CPU when the program run signal is abnormal.
In a CPU runaway monitoring circuit that resets U, a buffer circuit in which a capacitor and a resistor are interposed in series between a program run signal output terminal and a reference potential output terminal of the CPU, and a resistor and an inverter are connected in parallel. A reset signal output circuit in which a circuit and a capacitor are connected in series, and a diode connected between a connection point between the capacitor and the resistor of the buffer circuit and a connection point between the resistor and the inverter of the reset signal output circuit and the capacitor. When the potential at the connection point between the capacitor and the resistor of the buffer circuit is equal to the potential of the reference potential output terminal, the control circuit cuts off conduction with the reset signal output circuit. By repeatedly charging and discharging the capacitor of the reset signal output circuit, a reset signal is periodically output from the output terminal of the inverter, and when the potential of the connection point is different from the potential of the reference potential output terminal, the control circuit outputs the reset signal from the reset signal output circuit. The terminal voltage of the capacitor of the reset signal output circuit is held constant by conducting with
A CPU characterized in that the output of the reset signal from the reset signal output circuit is stopped.
runaway monitoring circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11201586U JPS6320246U (en) | 1986-07-23 | 1986-07-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11201586U JPS6320246U (en) | 1986-07-23 | 1986-07-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6320246U true JPS6320246U (en) | 1988-02-10 |
Family
ID=30992486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11201586U Pending JPS6320246U (en) | 1986-07-23 | 1986-07-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6320246U (en) |
-
1986
- 1986-07-23 JP JP11201586U patent/JPS6320246U/ja active Pending
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