JPS6320109B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for protecting a controlled rectifier that uses a reactor with a large time constant as a load, a controlled rectifier that has a large current capacity, and the like.

Various methods have been used to protect against failures of controlled rectifiers, but the four basic protective operations are gate shift, bypass pair, gate block, and breaker trip. , these are combined to perform protection interlocking operations.

FIG. 1 shows a block diagram of a general controlled rectifier. 1 is an AC busbar, 2 is an AC power switch, 3 is a rectifier transformer, 4 is a unit control rectifier, 5-1 to 5
-6 is a controlled rectifying element constituting the unit controlled rectifier 4, and 6 is a load. Gate shift is an operation in which the firing angle of the unit control rectifier 4 is set to an appropriate angle in the inverse conversion region (the firing angle is 90° to 180°), and the energy on the DC side is quickly regenerated to the AC side. On the other hand, a bypass pair is a pair of controlled rectifying elements (for example, controlled rectifying elements 5-
1 and 5-4) are energized at the same time to short-circuit the DC circuit. Gate blocking is an operation of blocking the ignition pulse applied to the control rectifier.

Conventionally, when a failure is detected in a controlled rectifier, depending on the type of failure, the protection operations described above are combined and interlocked, such as gate shift to gate block, bypass pair to gate block, instantaneous gate block, etc., and the final The control rectifier is protected by tripping the AC circuit breaker.

Incidentally, many large-capacity controlled rectifiers are constructed by connecting a plurality of unit control rectifiers in parallel to form a multiphase controlled rectifier. Also, if the load is a large reactor and a steep current rise is required, a high voltage is required at Ldi/dt when the current rises, but once the current becomes constant, the voltage at R _i is sufficient. Since only low voltages are required, a controlled rectifier is used, which is a cascade of unit controlled rectifiers for power factor correction. FIG. 2 shows a block diagram of a controlled rectifier constructed by connecting two unit control rectifiers in cascade and connecting two groups of cascade-connected unit rectifiers in parallel. Components in the figure that have the same functions as those in FIG. 1 are given the same reference numerals. 7-1~7
-4 is a unit control rectifier group in which unit control rectifiers 4-1 and 4-3 are connected in cascade (for simplicity, A
This is a DC reactor for suppressing the current flowing between the unit control rectifier group (referred to as group B) in which the unit control rectifiers 4-2 and 4-4 are connected in cascade.

In a controlled rectifier having such a configuration, for example, if a ground fault occurs on the high voltage side of the unit controlled rectifier 4-3,
Cascade connected unit control rectifier 4-1, 4
-3 current becomes unbalanced. Further, if the unit control rectifier 4-3 fails in commutation, an imbalance occurs between the A group current and the B group current. Conventional protection methods cannot provide smooth protection against such failures that occur in units of controlled rectifier groups.

For example, if the high voltage side of the unit control rectifier 4-3 has a ground fault, performing a gate shift will cause the load coil 6
All the current that was flowing through the coil, the ground point, the ground fault point, and the unit control rectifier 4-1 flows. Therefore, in the case of 2 groups in parallel, the current is twice as large, and in the case of n groups in parallel, the current is n times the unit control rectifier 4-1.
Concentrate on. The same thing happens when the unit control rectifier 4-3 fails to commutate, and when the output voltage between the A group and the B group becomes unbalanced and the gate shift is performed, the output voltage of the A group becomes 2.
The problem is that twice as much current flows. Furthermore, when a bypass pair protection operation is performed, the DC current attenuates with the L/R time constant of the load coil, resulting in a problem that it takes a long time for the current to become zero.

An object of the present invention is to eliminate the above-mentioned defects and to provide a controlled rectifier configured by connecting a plurality of cascade-connected controlled rectifier groups in parallel. To provide a method for protecting a controlled rectifying device, which can smoothly protect the controlled rectifying device without causing a concentrated flow of the controlled rectifying device.

The present invention will be explained below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention, and 8-1 and 8-2 in the figure represent the ignition of the controlled rectifiers of the A group and B group in the block diagram shown in FIG. 2, respectively. Current control circuit that determines the angle, 9-1, 9-2
10-1 and 10-2 are fault firing angle determining circuits that determine the firing angle at the time of failure based on a protection request signal such as gate shift or gate advance which will be explained later; 10-1 and 10-2 detect a failure and output necessary protection request signals. failure detection circuits 11-1 and 11-2 are OR elements that take an OR between the protection request signal of its own group and the protection request signal of other groups; 12-1 and 12-2 are current control circuits 8-1;
The firing angle signal from 8-2 and the output signal from the failure time firing angle determining circuits 9-1 and 9-2 are connected to the OR element 11.
Multiplexer that switches depending on the output signal of 1
3-1 and 13-2 are phase control circuits that determine the firing phase and firing timing based on the firing angle signals obtained from 12-1 and 12-2. Signals 51, 52
are the failure signals of group A and group B, respectively. Also,
In FIG. 3, a signal line with a width indicates a digital signal having a bit structure.

Hereinafter, the operation of the present invention will be explained with reference to FIGS. 2 and 3. For simplicity, phase control circuit 13-1
It is assumed that the output of the phase control circuit 13-2 is given to the unit control rectifiers 4-1 and 4-3 of the A group, and the output of the phase control circuit 13-2 is given to the unit control rectifiers 4-2 and 4-4 of the B group.

In this configuration, during normal operation, the multiplexers 12-1 and 12-2 are connected to the current control circuit 8-
1, 8-2 is selected, and the current control circuit 8-
The outputs of 1 and 8-2 are phase control circuits 13-1 and 13.
-2 to control the firing angle. In such a state, for example, a ground fault occurs on the high voltage side of the unit control rectifier 4-3, and the unit control rectifier 4-3
If the currents flowing through the circuits 1 and 4-3 become unbalanced, the failure detection circuit 10-1 detects a group A failure and the signal 51 becomes "1". Signal 51 is OR circuit 1
1-1 and 11-2, the multiplexers 12-1 and 12-2 of group A and group B are switched to disconnect the signals of current control circuits 8-1 and 8-2, respectively, and the firing angle determining circuit at the time of failure is activated. Output signals from 9-1 and 9-2 are output to phase control circuits 13-1 and 13-2. At the same time, the signal 51 is the failure detection circuit 9 of the failure group.
-1, and the firing angle determining circuit 9-1 at the time of failure outputs the firing angle corresponding to the gate shift.
On the other hand, the signal 51 is also input to the firing angle determination circuit 9-2 for the healthy group at the time of failure, and fixes the firing angle of the healthy group to an appropriate angle in the forward conversion region (firing angle 0° to 90°). (This is called gate advance) After a certain period of time has elapsed or when zero current is detected in the failure group, the firing angle is shifted to an angle corresponding to gate shift. FIG. 4 shows an embodiment of the firing angle determination circuit at the time of failure shown in FIGS. 9-1 and 9-2. In Figure 4, 14-1, 14-2
is a digital pattern generation circuit composed of a read-only memory, etc., and by appropriately selecting an address on the input side, it is possible to output the firing angle when the gate is shifted, and the firing angle when the gate is advanced.
16-1, 16-2 are delay circuits that delay the signals of the failure detection circuits of other groups for a certain period of time, 15-1, 15-
Reference numeral 2 denotes an OR circuit that ORs the output signals of the delay circuits 16-1 and 16-2 and the signals 51 and 52, respectively.

First, when the signal 51 is input to the fault firing angle determining circuit 9-1, the digital pattern generating circuit 14
-1 gate shift address is specified, a firing angle signal at the time of gate shift is output from the firing angle determining circuit 9-1 at the time of failure, and the A group is gate shifted.
On the other hand, the signal 51 is also input to the firing angle determining circuit 9-2 at the time of failure, designating the gate advance address of the digital pattern generating circuit 14-2, and outputting an appropriate firing angle in the forward conversion area. The signal 51 is also input to the delay circuit 16-2, and after a certain period of time, the OR circuit 15-2 is inputted to the delay circuit 16-2.
2 to the digital pattern generation circuit 14-2.
Specify the address of the gate shift. For this reason, group B advances the time gate determined by the delay circuit 16-2 and operates in the forward conversion region, and
The gate is shifted after the group current is reduced to zero.

To summarize the above actions, the control rectifier group in which the fault has occurred will gate shift and attenuate the current after detecting the fault, and the remaining healthy groups will operate at an appropriate firing angle in the forward conversion region for a certain period of time, and the current in the fault group will be After reducing to zero,
Gate-shifts the healthy group and regenerates energy on the load side. FIG. 5 shows another embodiment of the circuit for determining the firing angle at the time of failure. Components with the same functions as those in FIG. 4 are given the same reference numerals. 17-1 and 17-2 are zero current detection circuits that detect the current zero point of the failure group;
8-2 is an AND circuit. In this embodiment, after directly detecting that the current in the faulty group has become zero, the healthy group is shifted to gate shift.

As explained above, in a controlled rectifier configured by connecting a plurality of cascade-connected controlled rectifier groups in parallel as in the present invention, a failed controlled rectifier group is immediately gate-shifted, and a healthy controlled rectifier group is immediately gate-shifted. The group operates in the forward conversion region, and by gate shifting after a certain period of time or after detecting the zero point of the current in the fault group, the current does not concentrate on a specific control rectifier group, and it can be gate blocked or bypassed. It becomes zero faster than in the case of a pair, and the time for operating a healthy control rectifier group in the forward conversion region can be shortened, and the control rectifier can be promptly protected.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a general controlled rectifier.
Fig. 2 is a block diagram of a controlled rectifier constructed by cascading two unit control rectifiers and connecting two groups in parallel, Fig. 3 is a block diagram of an embodiment of the present invention, and Figs. 4 and 5 are FIG. 4 is a configuration diagram showing different embodiments of the firing angle determination circuit at the time of failure shown in FIG. 3; 1...AC bus line, 2...AC line disconnector, 3,3
-1~3-4... Rectifier transformer, 4,4~1~
4-4... Unit control rectifier, 5-1 to 5-6...
Control rectifying element, 6...Load, 7-1 to 7-4...
DC reactor, 8-1, 8-2... Current control circuit, 9-1, 9-2... Failure time firing angle determining circuit,
10-1, 10-2... Failure detection circuit, 11-
1, 11-2...OR circuit, 12-1, 12-2
... Multiplexer, 13-1, 13-2 ... Phase control circuit, 14-1, 14-2 ... Digital pattern generation circuit, 15-1, 15-2 ... OR circuit, 16-1, 16-2 ...Delay circuit, 17-
1, 17-2...Zero current detection circuit, 18-1, 1
8-2...AND circuit.

Claims (1)

[Claims] 1 In a polyphase controlled rectifier configured by connecting multiple groups of controlled rectifiers in parallel, each of which is configured by cascading at least two unit controlled rectifiers, a failure occurs in a group of controlled rectifiers connected in series. In this case, the failed control rectifier group performs protection interlocking from gate shift to gate block or gate shift to bypass pair, and the healthy control rectifier group operates in the forward conversion region, and after a certain period of time or the current of the failed control rectifier group 1. A method for protecting a controlled rectifier, characterized in that when the voltage becomes zero, the protection interlocking of a gate block is performed from a gate shift.