JPS5936510B2 - Protection method of controlled rectifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a controlled rectifier, and particularly to a protection method for a controlled rectifier suitable for application to L loads with large time constants and large-capacity DC power transmission.

Conventionally, multi-phase large capacity rectifiers are known in which multiple unit controlled rectifiers are connected in parallel, but when it comes to controlled rectifiers that are configured by controlled rectifying elements, there are problems such as arm short circuits and commutation failures. In case of failure, protection methods such as gate shifting, bypass pairs, gate blocks, etc. are known.

Here, the gate shift is an operation in which the firing angle of the control rectifier is greatly delayed to operate in a reverse conversion region (firing angle 900 to 1800), and energy on the DC side is regenerated to the AC side.

On the other hand, a bypass pair is one in which a pair of controlled rectifier elements connected to the same phase on the AC side are simultaneously energized to short-circuit the DC circuit. Furthermore, gate blocking is a protective operation based on blocking the ignition pulse given to the control rectifier. The protection method for a controlled rectifier usually involves combining these operations depending on the type of failure, and interlocking protection from gate shift to gate block, bypass pair to gate block, instantaneous gate block, etc., and finally The most common method is to trip the AC circuit breaker. Figure 1 shows the main circuit wiring diagram of a well-known 12-phase control rectifier in which two unit control rectifiers are connected in parallel. , 3-1, 3-2 are rectifier transformers, magnetic conductor 1, magnetic conductor 2 are unit control rectifiers that convert the outputs of the rectifier transformers 3-1, 3-2 into direct current, 5-1, 5 -2 is a DC reactor that suppresses the current flowing between the unit control rectifiers 4-1 and 4-2, and 6 is a load.

In this configuration, during normal operation, DC power is supplied to the load 6, but the unit control rectifier 4-1,
4-2 If a failure occurs such as an arm short circuit or commutation failure that prevents the output from being properly controlled, the conventional protection interlocking method described above cannot smoothly protect it. .

For example, if an arm short circuit occurs in the unit control rectifier conductor 1, according to the conventional protection method, the protection is linked to the circuit breaker trip from the instantaneous gate block.
As shown in the figure, when the load is multiphase, has a large capacity, and has a large time constant, it takes a long time for the DC current to decay, so the DC current continues to flow for a long time.

For this reason, problems such as the expansion of the failure of the faulty unit control rectifier magnetic conductor 1 and the occurrence of a failure in the healthy unit control rectifier magnetic conductor 2 occur. In other words, when you perform a gate block,
The output voltage of the unit control rectifier is a positive voltage and a negative voltage that occur periodically, but the average value is zero, so the DC current attenuates approximately according to the time constant of the load. In such a case, the flow will continue to flow to two specific arms for a long time. In addition, if only the faulty unit control rectifier is set to an instantaneous gate block or a bypass pair, and only the healthy unit control rectifier is gate shifted, the DC current will concentrate on the faulty unit control rectifier due to the unbalance of the output voltage between the unit control rectifiers. This will cause a problem. Figure 2A shows the phase voltage waveform when the U phase of the unit control rectifier causes an arm short circuit at tl, and the healthy unit control rectifier is gate shifted at TO. The phase voltage waveform is shown when the unit control rectifier in which an arm short circuit occurs is instantaneously gate-blocked at T2.

As is clear from the figure, a healthy unit control rectifier generates a constant negative voltage, whereas a faulty unit control rectifier periodically generates positive and negative voltages, so it is a failure. Current flows in the loop of the unit control rectifier, DC reactor, and healthy unit control rectifier, and the current in the healthy unit control rectifier decreases, causing the current to concentrate on the faulty unit control rectifier. Therefore, an object of the present invention is to eliminate the drawbacks of the above-mentioned prior art, and to solve the problem of a polyphase controlled rectifier in which a plurality of unit controlled rectifiers are connected in parallel, so that when one or more of the unit controlled rectifiers fails, it can be smoothly handled. The object of the present invention is to provide a new protection method for a controlled rectifier that makes it possible to protect this device.

FIG. 3 is a block diagram of a controlled rectifier according to an embodiment of the present invention, in which 56-1 and 56-2 are the control circuits of the unit controlled rectifiers 4-1 and 4-2 in FIG. The corresponding rectifier control circuits, T-1 and T-2, are control circuits that perform current control or voltage control based on the difference between the reference value and the detected value and determine the firing angle of the rectifier, and 8-1 and 8-2 are normal control circuits. is set near the minimum firing angle that can normally fire, and in the event of a failure, a firing angle determination circuit 9-1, 9 outputs the firing angle at the time of failure of the other unit control rectifiers 4-2, 4-1. - 2 is a gate shift phase determining circuit, 10-1, 10-2 is a control circuit T-1, 7-2, firing angle determining circuit 8-1, 8-2
or a phase control circuit that generates firing timing for each phase of the corresponding unit control rectifier 4-1, 4-2 based on the output signal of either of the outputs of the gate shift phase determining circuit 9-1, 9-2; 12-1, 12-2 are delay circuits that delay the failure signals of other unit control rectifiers 4-2, 4-1, and 13-1, 13-2 are other unit control rectifiers 4-2, 4-1. The flip-flop circuits 14-1 and 14-2 are set by the fault signals of the unit control rectifiers 10-1 and 10-2, and the flip-flop circuits 14-1 and 14-2 are set by the fault signals of the unit control rectifiers 10-1 and 10-2. Inhibit circuits 11-11 and 11-21 block the outputs of control circuits T-1 and T-2, respectively, and control circuits 7-1 and T-2 with failure signals of other unit control rectifiers 4-2 and 4-1. 11-12, 11-22 are flip-flop circuits 1
The firing angle determining circuit 8 - is determined by the outputs of 3-1 and 13-2.
1, 8-2 are analog switch circuits that turn on and off the outputs, 11-13, 11-23 are delay circuits 12-1, 1
2-2 An analog switch circuit that turns on and off the output of the gate shift phase determining circuit according to the output signal of 2, 51-1
, 51-2 are failure signals of the unit control rectifiers 4-1, 4-2, and 52-1, 52-2 are the delay circuits 12-1, 12.
-2 output signals 53-1 and 53-2 are output signals of the flip-flop circuits 13-1 and 13-2.

In this configuration, if the unit control rectifier 4-1 fails now, the failure signal 51-1 becomes logic 1'' and is output to the phase control circuit 10-1 by the inhibit circuit 14-1.
The ignition pulse signal from 4-1 is blocked and the unit control rectifier 4-1 is gate-blocked.

At the same time, the fault signal 51-1 is sent to the control circuit 56-2 of the unit control rectifier 4-2, which turns off the analog switch 11-21 and cuts off the control signal from the control circuit T-2. 2, and the analog switch 11-22 is turned on by the output signal 53-2 of the flip-flop circuit 13-2. the result,
The output signal of the firing angle determining circuit 8-2 is transmitted to the phase control circuit 10-.
2, and the unit control rectifier 4-2 is operated in the forward conversion region. The failure signal 51-1 is also sent to the delay circuit 12-2, and when a suitably set time elapses from this time in the delay circuit 12-2, the output 5 of the delay circuit 12-2
2-2 becomes logic 1''. As a result, this output 5
The flip-flop circuit 13-2 receiving the flip-flop 2-2 is reset and its output signal becomes logic "o".
Therefore, the output 53 of the flip-flop circuit 13-2
-2 is turned off, and at the same time, the analog switch 11-23 receiving the output 52-2 of the delay circuit 12-2 is turned on, and the output signal of the gate shift phase determining circuit 9-2 is turned on. is the phase control circuit 10
-2, so that the unit controlled rectifier 4-2 is gate shifted. FIG. 4 shows the fault signal 51-1 of the unit control rectifier 4-1 and the output signal 5 of the flip-flop circuit 13-2.
3-2 and the time sequence of the output signal 52-2 of the delay circuit 12-2. To summarize the above operation, when the unit control rectifier 4-1 fails, the unit control rectifier 4-1 instantaneously gate-locks the unit control rectifier 4-2, and the unit control rectifier 4-2 maintains the firing angle for the time set by the delay circuit 12-2. The determining circuit 8-2 operates in the forward conversion region, and gate shifts after a delay time.

As described above, when a healthy unit control rectifier is operated in the forward conversion region for a certain period of time at the time of a failure, current flows from the healthy unit control rectifier to the DC reactor and then through the loop of the failed unit control rectifier. becomes zero.

Therefore, the faulty unit control rectifier is immediately stopped, and then the normal unit control rectifier is gate-shifted, so that the DC current is regenerated to the AC side. By the way, the delay time set for the delay circuits 12-1 and 12-2 is set to the time until the current of the failed unit control rectifier reliably reaches zero, depending on the maximum fault current, rated voltage, and DC reactor value. Of course. In the embodiment shown in Fig. 3, an analog switch is used to switch the firing phase and gate shift phase in the forward conversion region immediately after a failure. Similar effects can also be obtained with a configuration in which the phase is gradually changed from the forward conversion region to the gate shift phase. FIG. 5 shows a partial block diagram of a controlled rectifier according to another embodiment of the present invention, in which 15-1 is a current zero detection circuit of a unit controlled rectifier 4-1, and 54-1 is a unit This is the current value flowing through the controlled rectifier 4-1.

That is, the configuration of FIG. 5 is the same as the delay circuit 1 in the configuration of FIG.
2-1 and 12-2 are each unit system (goods) rectifier 4-2
, 4-1, and all other configurations are the same as those shown in FIG. 3. In such a configuration, after a failure occurs, as mentioned above, the unit control rectifier that is healthy is operated in a forward conversion manner, and the current zero detection is performed to detect that the current of the unit control rectifier that has failed and is gate-locked has become zero. After checking the circuit, the unit control rectifier is gate shifted.

According to the configuration shown in Fig. 5, since the gate shift is performed on a healthy unit control rectifier after confirming that the current in the faulty unit control rectifier has become zero, reliability is high, and energization in the event of a failure is reduced. This has the effect of being able to cope with differences in the time required to reach zero current due to differences in current.

In addition, in the configuration of FIG. 5, the same result can be obtained even if a signal based on the AND condition of the failure signal 51-1 and the output signal 55-2 is used instead of the output signal 55-2 of the zero current detection circuit 15-1. It is something that can be effective. FIG. 6 is a block diagram of a controlled rectifier according to still another embodiment of the present invention.
In the figure, 16-1 and 16-2 are bypass pair control circuits,
17-1 and 17-2 are OR circuits.

In this configuration, if the unit control rectifier 4-1 fails, the failure signal 51-1 becomes logic "1", and the phase control circuit 10 is output by the inhibit circuit 14-1.
Block the output signal from -1.

At the same time, the fault signal 51-1 is transmitted to the bypass pair control circuit 16.
-1, the control circuit 16-1 generates an ignition command for the phase to be a bypass pair, and outputs it through the OR circuit 17-1. As a result, the faulty unit control rectifier 4
-1 is in a bypass pair state. The protective movement of the healthy unit control rectifier 4-2 is the same as in the case of FIG. That is, the faulty unit control rectifier 4-1 is not in a gate block state but in a bypass pair state, the DC circuit is short-circuited, and the faulty unit control rectifier 4-1 is not affected by the AC side. Furthermore, if the zero current detection circuit shown in FIG. 5 is applied instead of the delay circuit shown in FIG. 6, it is possible to obtain the same effect as in the embodiment shown in FIG. As a bypass pair control method when an arm is short-circuited, the gate block signal may be delayed by an appropriate time and the gate block may be performed after the bypass pair is established, without the need to provide a bypass pair control circuit.

The phase voltage waveform of the faulty unit control rectifier in this case is
(TO, tl, t2 indications are the same as in Fig. 2). Further, in each of the above embodiments, a 12-phase controlled rectifier using two unit controlled rectifiers is illustrated, but the implementation of the present invention is not limited to this.
Furthermore, it goes without saying that it is also applicable to polyphase cases.

As described above, according to the present invention, in a polyphase controlled rectifier in which a plurality of unit controlled rectifiers are connected in parallel, when one or more of the unit controlled rectifiers fails, the failed unit controlled rectifier is instantly replaced. In addition to gate protection or bypass pairing, we have adopted a protection method that allows a healthy unit control rectifier to operate in the forward conversion region for a certain period of time or until the current of the failed unit control rectifier becomes zero, so that the current of the failed unit control rectifier can be reduced. After confirming that the current has become zero and stopping the rectifier, the normal unit control rectifier can be gate-shifted and the DC current can be regenerated to the AC side. Accordingly, it is possible to obtain a new protection method for a controlled rectifier that eliminates inconveniences such as long-term current continuation due to the time constant of , and can take prompt protective action.

[Brief explanation of the drawing]

Figure 1 shows a well-known 12-unit rectifier in which two unit control rectifiers are connected in parallel.
Figure 2 is a main circuit wiring diagram of the phase control rectifier, and Figure 2 is a waveform diagram showing the phase voltage waveform when a failure occurs in the control rectifier in Figure 1.
The figure is a block diagram of a controlled rectifier according to one embodiment of the present invention, FIG. 4 is a time sequence explaining the operation of the configuration of FIG. 3, and FIG. 5 is a controlled rectifier according to another embodiment of the present invention. FIG. 6 is a partial block diagram of a controlled rectifier according to still another embodiment of the present invention, and FIG. T is a waveform diagram illustrating the operation of the configuration of FIG. 6. 4-1, 4-2...Unit control rectifier, 56
-1,56-2... Rectifier leg circuit, T-1,
T-2... Control circuit, 8-1, 8-2...
... Firing angle determination circuit, 9-1, 9-2...
Gate shift phase determining circuit, 10-1, 10-2...
...Phase control circuit, 12-1, 12-2...
・Delay circuit, 13-1, 13-2...Flip head knob circuit.

Claims (1)

[Claims] 1. In a controlled rectifier that connects at least two unit-controlled rectifiers in parallel and performs multiphase rectification, when at least one unit-controlled rectifier fails, the failed unit-controlled rectifier is connected to a gate block or a bypass pair. A protection method for a controlled rectifier, characterized in that a healthy unit controlled rectifier is operated in a forward conversion region for a certain period of time or until the current of the failed unit controlled rectifier becomes zero.