JPS63200924U - - Google Patents

Info

Publication number
JPS63200924U
JPS63200924U JP9234287U JP9234287U JPS63200924U JP S63200924 U JPS63200924 U JP S63200924U JP 9234287 U JP9234287 U JP 9234287U JP 9234287 U JP9234287 U JP 9234287U JP S63200924 U JPS63200924 U JP S63200924U
Authority
JP
Japan
Prior art keywords
waveform
detector
electronic tuner
amplifier
measured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9234287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9234287U priority Critical patent/JPS63200924U/ja
Publication of JPS63200924U publication Critical patent/JPS63200924U/ja
Pending legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路構成図、
第2図は第1図におけるDCアンプの入力波形図
、第3図は同DCアンプの出力波形図、第4図は
従来例を示す回路構成図、第5図は第4図におけ
るDCアンプの入力波形図、第6図は同DCアン
プの出力波形図である。 1……スイープジエネレータ、2……被測定電
子チユーナー、3……検波器、4……DCアンプ
、6……オシロスコープ、7……コントロールc
pu。
FIG. 1 is a circuit diagram showing an embodiment of the present invention;
Figure 2 is an input waveform diagram of the DC amplifier in Figure 1, Figure 3 is an output waveform diagram of the same DC amplifier, Figure 4 is a circuit configuration diagram showing a conventional example, and Figure 5 is a diagram of the DC amplifier in Figure 4. The input waveform diagram and FIG. 6 are the output waveform diagrams of the same DC amplifier. 1...Sweep generator, 2...Electronic tuner to be measured, 3...Detector, 4...DC amplifier, 6...Oscilloscope, 7...Control c
pu.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 被測定電子チユーナーのテストポイントよりピ
ツクアツプした応答波形を検波する検波器と、該
検波器の波形を増幅するDCアンプとを有してな
り、前記検波後の波形にDCバイアスを強制的に
加える手段を設けたことを特徴とする電子チユー
ナーの波形調整回路。
A means for forcibly applying a DC bias to the detected waveform, comprising a detector that detects a response waveform picked up from a test point of the electronic tuner to be measured, and a DC amplifier that amplifies the waveform of the detector. A waveform adjustment circuit for an electronic tuner, characterized in that it is provided with.
JP9234287U 1987-06-15 1987-06-15 Pending JPS63200924U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9234287U JPS63200924U (en) 1987-06-15 1987-06-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9234287U JPS63200924U (en) 1987-06-15 1987-06-15

Publications (1)

Publication Number Publication Date
JPS63200924U true JPS63200924U (en) 1988-12-23

Family

ID=30953964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9234287U Pending JPS63200924U (en) 1987-06-15 1987-06-15

Country Status (1)

Country Link
JP (1) JPS63200924U (en)

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