JPS6320077B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division multiplex transmission control device having a delay switch function.

Conventional delay switches for the purpose of delay control include those that use mechanical timers using oil dart pots or springs, and those that use electrical timers that use crystal oscillation, etc., but the former are generally inexpensive. However, there is a problem in that the time accuracy is poor and it is difficult to change the set time, and the latter has good time accuracy and it is easy to change the set time, but it is expensive.

The present invention has been provided in view of the above-mentioned points, and the delay time setting control for each switch is performed on the main operation panel of a time division multiplex transmission control system, and has high time accuracy and easy control. It has a delay switch function that allows you to change the set time, and
It is an object of the present invention to provide a time division multiplex transmission device that can obtain a delay switch function at a substantially low cost by realizing the delay switch function for a plurality of switches on the main operation panel of the main unit.

An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing an outline of a system according to an embodiment of the present invention, and the circuit configuration itself is essentially no different from a conventional time division multiplex transmission control apparatus. However, in the block diagram of FIG. 1, the main operation panel 5 and each control and switch terminal device 2, 3 are connected to the signal line 10, and each terminal device 2, 3 is connected to each terminal device individually or in duplicate. The addresses of channels 1 to n are assigned, and by setting the addresses of channels 1 to n on the main operation panel 5, the terminals 2 and 3 of the corresponding channels are called, and the switch terminal 3 is used to call the terminals 2 and ₃ of the corresponding channels. 6 ₂ ... is sent back to the main operation panel 5 as a monitoring signal, and further sent to the main operation panel 5.
A control signal for controlling the loads 4 ₁ , 4 ₂ . . . is sent back to the control terminal 2 from the control terminal 2 . In the figure, 11 is a commercial power source, and 12 is a power line.

Fig. 2 shows a block diagram of the main operation panel 5, and shows the clock of the microcomputer (hereinafter referred to as CPU) 1 built in it, or the oscillation clock of the microcomputer (hereinafter referred to as CPU) 1 when a separate crystal oscillator is provided. A frequency divider circuit 13 that divides the frequency appropriately to create an appropriate time interval, and a frequency divider circuit 13 that divides the frequency appropriately to create an appropriate time interval, and this clock
A counting memory 14 that counts the number programmed in the CPU 1, a setting memory 7 that stores in advance information on which load of each channel is to be controlled and how much delay, and a It has a configuration in which a key input section 9 for keying in data is added to the conventional main operation panel 5. Thus, the conventional main operation panel 5 includes the CPU 1 as the center, the control memory 15, the control data memory 16, the display section 17, the reception processing section 18, the reception signal detection section 19, the transmission signal generation section 20, the transmission section 21, etc. The frequency dividing circuit 13 and the counting memory 14 constitute a clock section 8 that performs a timekeeping operation for setting a delay time.

The operation of one embodiment of the present invention will be described below with 4 monitors (4 switches 6 ₁ , 6 ₂ . . . input monitoring) and 4 controls (4 independent relays 22 ₁ , 2
A system for controlling 2 _{2 .} . . ) will be explained as an example. First, in the conventional time-division multiplexing load control and monitoring system, which is the premise of the present invention, each terminal device is assigned a unique address (electrically) in advance, and from the main operation panel 5, an "address signal +
A signal containing a "control signal" + "reply waiting signal" as one unit signal is sent, and each address (for example, 1 to
In the nCh system, each address from 1 to n) is sequentially
The signals are set cyclically or regularly, such as 1Ch→2Ch→3Ch→...→nCh→1Ch, and the signals of each of the above units are sent out based on this. The terminal devices in this system include a switch input terminal device 3 and loads 4 ₁ , 4 ₂ ...relays 22 ₁ , 22 ₂ for control.
There is a control terminal device 2 that controls ..., and each terminal device 2 and 3 switches the switch 6 ₁ , 6 ₂ ... to return the input waiting signal band only when the unit signal of its own address is sent. to the main operation panel 5 [switch terminal 3] or according to the control signal (for example, "1" signal is ON control, "0" signal is OFF control)
The control terminal 2 is configured to control the relays 22 ₁ , 22 ₂ . . . For example, if the current control state of 1Ch is 1φ1φ, this data of 1Ch is stored in the control data memory 16 of the main operation panel 5, and when the signal of 1Ch is sent out, this data is followed by the address signal of 1Ch, and then a reply is waited for. The period signal is transmitted through the transmitter 21. At this time (actually before)
(from immediately after the 1Ch signal was sent to the present),
Switch input terminal 3 addressed to 1Ch [There may be multiple terminals for the same Ch]
If one of _the switches 6 ₁ to 6 ₄ or _a plurality of switches 6 ₁ , 6 ₂ . The signal is transmitted from the switch terminal 3 to the main operation panel 5 as a reply signal during the period. For example, if switches 6 ₁ and 6 ₂ of 1Ch switches 6 ₁ , 6 ₂ .
Exclusive logic operation is performed on this reply signal and data 1φ1φ in the control data memory of 1Ch in the logic operation section of CPU 1, and bits 1, 2,
3 and 4 perform an exclusive OR operation on the old control data of 1φ1φ and the reply signal of 11φφ, respectively, to create new control data of φ11φ. In this way, the φ11φ data is stored in the control data memory 16 as new control data for 1Ch, and is sent out when the next 1Ch control data is sent out. The 1Ch control terminal 2 controls the loads 4 ₁ and 4 ₂ based on such control data, with the load 4 ₁ being controlled off and the load 4 ₂ being controlled on.

In the system as described above, the present invention further includes the setting memory 7 and the counting memory 1 shown in FIG.
4 and a frequency dividing circuit 13, a key input section 9, etc., and the operation of the main part of this invention will be explained below.
That is, in the circuit shown in Fig. 2, the key input section 9 is used to delay, for example, 1Ch for 1 minute (this time must be an integral multiple of the divided clock), 5Ch for 30 seconds, and so on. Controlled Ch number (also bit-specified number if necessary)
and delay control time data information are keyed in and stored in the setting memory 7 in advance. Now, for example, bit 1 of 1Ch is 30 seconds, bit 3 is 1 minute,
Assume that bits 1 to 3 of 5Ch are programmed for 2 minutes and stored in the setting memory 7, and the control state of 1Ch is φφφφ, that is, the loads 4 1 to 4 4 corresponding to bits ₁ to ₄ are completely off. Suppose that the condition is . At this time, if switch 6 ₁ of the switch terminal 3 of 1Ch is pressed,
When a 1Ch signal is sent from the main operation panel 5, a return signal of 1φφφ is transmitted from this switch terminal 3 to the main operation panel 5 in the return waiting signal band of this signal, and the main operation panel 5 receives it. After passing through the signal detection section 19 and the reception processing section 18, the CPU 1, which is a logical operation section, performs an exclusive OR operation on the previous control data φφφφ and the received data 1φφφ, stores the new control data 1φφφ in the control data memory 16, and stores the new control data 1φφφ in the control data memory 16. In addition to preparing for the control signal transmission of 1Ch, the change of each bit from φ to 1 is detected, and the setting memory 7 is searched to see if the corresponding bit of the Ch having this change is programmed to be delayed-controlled. As a result of the search, bit 1 of 1Ch is programmed to be 30 seconds, so this data is stored in the counting memory 14 in one-to-one correspondence with bit 1 of 1Ch. on the other hand
The CPU 1 is configured to subtract the pulses generated by the frequency dividing circuit 13 from the counting memory 14 at fixed time intervals during transmission and reception processing, and in the above example, the bits of 1Ch are subtracted. The data in the counting memory 14 corresponding to 1 counts down to "0" after 30 seconds. The CPU 1 detects this change and forcibly changes the corresponding control data "1" in the control data memory 16 to "φ", so that the desired delay control (here, the load corresponding to bit 1 of 1Ch that is once turned on) is executed. automatically turns off after 30 seconds). In other words, in the case of this embodiment, if the control data memory 16 is "1", it means that the timer is being set if the delay control program is programmed, and if it is "φ", it means that the timer is being reset. Therefore, with a switch terminal programmed in advance for delay control, it can be easily reset by pressing the switches 6 ₁ , 6 _{2 .} . . again within the delay control time after being turned on (timer set input). In addition, in the above embodiment, the delay control was explained in which the switch is turned on when it is normally _off and then turned off _again after a certain period of time. Delay control in which the power is turned off and then turned back on again after a certain period of time can also be performed in the same manner. Furthermore, although the configuration of the counting memory 14 has been explained using a countdown method, a method may also be used in which counting up is performed every pulse output from the frequency dividing circuit 13 and comparing it with a set value each time. The clock section 8 may be of any type as long as it has a timekeeping function.

Since the present invention is configured as described above, it is possible to easily eliminate delays in a conventional time division multiplex transmission control device by simply adding some circuit components to its main operation panel and making slight changes to the program operation. In addition, many delay switch functions can be easily changed just by changing the program, and no modification is required on the switch side, so the delay switch function can be effectively changed at a much lower cost. can be obtained,
In addition, the presence or absence of a delay switch function for each switch and the delay time of the delay switch function can be easily changed and set, and highly accurate time accuracy can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the basic configuration of a time division multiplex transmission control device, and Fig. 2 is a block diagram of a main operation panel according to an embodiment of the present invention, where 1 is a microcomputer (CPU) and 2 is for control. Terminal device, 3 is terminal device for switch, 4 ₁ , 4 ₂ ... is load, 5 is main operation panel, 6 ₁ , 6 ₂ ... is switch, 7 is setting memory,
8 is a clock section, and 9 is a key input section.

Claims (1)

[Claims] 1. A built-in microcomputer that sequentially sends out address signals for each terminal device, and transmits the address signals of each terminal device in sequence to the terminal device having a matching address among the terminal devices whose addresses are individually set in advance. A main operation panel that sends and receives control signals or monitoring signals, and when the main operation panel sends its own address, it subsequently receives a control signal from this main operation panel and becomes subordinate based on the control data. A plurality of control terminals that control loads, and a switch input terminal that returns data about the switch input status as a monitoring signal to the main operation panel during the signal return time when the main operation panel sends out its own address. As a result, the main operation panel receives the monitoring signal from the switch input terminal, and controls each subordinate load of the control terminal associated with each switch of the switch input terminal based on a preset program. In a time division multiplexing transmission control device that creates and sends control signals to be controlled, the correspondence relationship between the switch of a switch input terminal device that should perform a delayed operation and the dependent load of the control terminal device, and the delay of the delayed operation The main operation panel is equipped with a setting memory that stores time data and content data of its delayed operation, and a clock section that measures the time length by dividing and counting an appropriate clock signal. When creating control data for a dependent load that corresponds to a corresponding relationship between a switch and a dependent load, data is stored in the setting memory until the delay time data stored in the setting memory matches the time length measured by the clock unit. 1. A time division multiplex transmission control device, characterized in that it is configured to control dependent loads based on stored delay operation content data. 2. The time division multiplex transmission control device according to claim 1, further comprising a key input section for inputting data stored in the setting memory.