JPS63199467A - Photodiode - Google Patents
PhotodiodeInfo
- Publication number
- JPS63199467A JPS63199467A JP62032998A JP3299887A JPS63199467A JP S63199467 A JPS63199467 A JP S63199467A JP 62032998 A JP62032998 A JP 62032998A JP 3299887 A JP3299887 A JP 3299887A JP S63199467 A JPS63199467 A JP S63199467A
- Authority
- JP
- Japan
- Prior art keywords
- region
- photodiode
- conductivity type
- layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 230000003287 optical effect Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001443 photoexcitation Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、逆バイアス動作で使用するフォトダイオード
に関し、特に低容量化に優れたフォトダイオードに関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a photodiode used in reverse bias operation, and particularly to a photodiode that is excellent in reducing capacitance.
(従来技術とその問題点)
半導体光検出器としてアバランシ降伏近傍で使用し内部
増倍効果を利用するアバランシ・フォトダイオード及び
増倍効果は伴なわないが、低バイアスで使用するフォト
ダイオードがよく知られており、光通信システムの受光
素子としてその研究・開発が、光源である半導体レーザ
、発光ダイオードと共に進められている。(Prior art and its problems) Avalanche photodiodes, which are used near avalanche breakdown and utilize internal multiplication effects as semiconductor photodetectors, and photodiodes, which do not have multiplication effects but are used at low bias, are well known. Research and development is progressing on it as a light-receiving element for optical communication systems, along with semiconductor lasers and light-emitting diodes, which are light sources.
現在の光通信システムは、光の伝送媒体である光ファイ
バーの低損失領域が1,3〜1.6gm波長域にありこ
れに対応して、1.31Jmあるいは1.5hmで特徴
づけられる波長での光伝送が主流となっている。この波
長域での光源としてはInPに格子整合するInGaA
sP混晶を用いたレーザタイオードが、また光検出器と
してはInGaAsP混晶の全ての波長域をカバーでき
るInPに格子整合したI nGaAs三元混晶材料で
のフォトタイオードあるいはアバランシ・フォトタイオ
ードか中心的である。また当然のことながら、経済性を
考えて、長距離、大容量の可能性を追及しており、超高
速な光検出器の開発が待たれている。In current optical communication systems, the low loss region of optical fiber, which is the optical transmission medium, is in the 1.3 to 1.6 gm wavelength range, and correspondingly, the low loss region of optical fiber, which is the optical transmission medium, is in the wavelength range of 1.3 to 1.6 gm. Optical transmission has become mainstream. The light source in this wavelength range is InGaA, which is lattice matched to InP.
A laser diode using an sP mixed crystal, and a photodiode or an avalanche photodiode using an InGaAsP ternary mixed crystal material lattice-matched to InP, which can cover the entire wavelength range of the InGaAsP mixed crystal, are used as a photodetector. ode or central. Naturally, considering economic efficiency, the possibility of long-distance and large-capacity is being pursued, and the development of ultra-high-speed photodetectors is awaited.
現在実用化か進められているアバランシ・フォトタイオ
ードは内部増倍作用を利用しているから高感度化が期待
できるが、一方この内部増倍作用を有するか故に、高増
倍域での応答劣化を伴なうという特徴がある。そこで、
超高速を目的とした光検出器としてのフォトダイオード
の研究開発か行なわれており、例えば、エレクトロニク
ス・レターズ、21巻、 262−263ページにその
一例が報告されている。第2図はそのフォトダイオード
の概略を示す断面図である。このフォトダイオードでは
、n十−I’nP基板11上にn −InGaAs層
13を結晶成長し、その主表面を不純物拡散手法を用い
てp+−InGaAs層15とすることによりその基本
形を得ている。ここでn −InGaAs層13を最
終的に1.5pm程度と薄くすることが特徴であり、こ
の領域において、逆バイアスが印加されているときにお
ける光励起キャリアの走行時間を短くすることにより3
dB降下遮断周波数として約20 GHzという高速変
調特性を得ている。この様な高速性は、n −InG
aAs層13を薄くして光励起により発生したキャリア
の走行時間が短くしであると共に第2図に示すようにメ
サ構造にすることによりpn接合の容量が低減しである
ことによる。Avalanche photodiodes, which are currently being put into practical use or are being put into practical use, can be expected to have high sensitivity because they utilize internal multiplication. It is characterized by deterioration. Therefore,
Research and development of photodiodes as photodetectors aimed at ultra-high speed is being carried out, and one example is reported in, for example, Electronics Letters, Vol. 21, pp. 262-263. FIG. 2 is a cross-sectional view schematically showing the photodiode. In this photodiode, its basic form is obtained by crystal-growing an n-InGaAs layer 13 on an n+-I'nP substrate 11 and forming a p+-InGaAs layer 15 on its main surface using an impurity diffusion method. . The feature here is that the n-InGaAs layer 13 is finally made thin to about 1.5 pm, and in this region, by shortening the travel time of photoexcited carriers when a reverse bias is applied,
A high-speed modulation characteristic with a dB drop cutoff frequency of approximately 20 GHz has been obtained. Such high speed is due to n-InG
This is because by making the aAs layer 13 thinner, the transit time of carriers generated by photoexcitation is shortened, and by forming it into a mesa structure as shown in FIG. 2, the capacitance of the pn junction is reduced.
しかしながら、この様なメサ構造は、信頼性。However, such a mesa structure is not reliable.
実用性、実装上などから必ずしも望ましい構造ではなく
、プレーナ構造での高速フォトダイオードが望まれてい
る。プレーナ構造のフォトダイオードの例としては、第
3図に示すような構造かある。A high-speed photodiode with a planar structure is desired, although this structure is not necessarily desirable from the standpoint of practicality and mounting. An example of a photodiode with a planar structure is the structure shown in FIG.
本図のフォトダイオードでは、n→−InP基板11上
にn”−InP層12.n−−I nGaAs光吸収層
13.n−1nPキャップ層14を有する結晶を用いて
選択的にp(領域15を形成した後に、絶縁ai7.
n型電極18及びn型電極19により構成されている。In the photodiode shown in the figure, a crystal having an n''-InP layer 12, an n--InGaAs light absorption layer 13, and an n-1nP cap layer 14 on an n→-InP substrate 11 is used to selectively form a p (region). After forming the insulation ai7.
It is composed of an n-type electrode 18 and an n-type electrode 19.
ここで特徴は、プレーナ構造である点から取扱いやすい
、高信頼であるなどの利点は多いが、本図の例では、n
型電極として大きな面積を有する領域をバイアス印加用
リード線との接触用に設けておく必要があり、低容量化
が困難であるという難点かある。The feature here is that it has a planar structure, which has many advantages such as ease of handling and high reliability.
It is necessary to provide a region having a large area as a mold electrode for contact with a lead wire for bias application, which poses a problem in that it is difficult to reduce the capacitance.
そこで、本発明の目的は、構造を工夫することにより、
プレーナ構造でしかも低容量化が容易で、ひいては高速
性能に優れたフォトダイオードを提供することにある。Therefore, the purpose of the present invention is to improve the structure by devising the structure.
The object of the present invention is to provide a photodiode that has a planar structure, can easily reduce the capacitance, and has excellent high-speed performance.
(問題点を解決するための手段)
前述の問題点を解決するために本発明が提供する手段は
、半絶縁性基板の−1表面上に第1の導電型を示す第1
の半導体層を有し、該第1の半導体層の一領域を選択的
に第2の導電型の領域に転換することによりpn接合が
形成してあり、このpn接合に入射する光の信号を電気
の信号に変換するフォトタイオードであって、前記光の
入射に関与しない前記第2の導電型領域の少なくとも一
部分が前記半絶縁性基板にまで達していることを特徴と
する。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a means for solving the above-mentioned problems by forming a first conductivity type on the -1 surface of a semi-insulating substrate.
A pn junction is formed by selectively converting a region of the first semiconductor layer into a region of a second conductivity type, and a light signal incident on the pn junction is The photodiode converts into an electric signal, and is characterized in that at least a portion of the second conductivity type region that does not participate in the incidence of light reaches the semi-insulating substrate.
(実施例)
以下、本発明の実施例について、図面を参照にして説明
する。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第1図は本発明のフォトダイオードの一実施例を示す概
略横断面図である。この実施例の製造においては、まず
(ioo)面を有する鉄ドープ半絶縁InP基板10上
に、例えば気相成長法によりi厚0.51Im、不純物
濃度5 X 10”cn−3のn”−1nP層12を成
長後、膜厚1,5μm、不純物濃度I X 10”■−
3のn −InGaAs層13を成長する。次に膜厚
14+m、不純物濃度8X 10” an−3のn−I
nP層14を形成する。このようにして得られたウェー
ハの表面に、例えば5i02Jl(を形成した後、フォ
トレジスト工程により選択的に一領域を除去する。次に
、この5i02膜を不純物拡散用のマスクとして、例え
ばZn5P’2を拡散源として高真空排気した閉管中に
上記ウェーハを配して封管後、520℃前後で数分の熱
処理を施すことによりZnの選択拡散p+領領域5を形
成する。ここでp十領域15の先端がn−−InGaA
s層13に達するように熱処理時間を調整する。次に再
度5102Mを形成した後、上記p十領域15の一領域
に重なる5i02の一領域を上記と同様にフォトレジス
ト工程により除去しな後、上記と同様に5i02を拡散
マスクとして例えばZnの拡散を行なう。FIG. 1 is a schematic cross-sectional view showing an embodiment of the photodiode of the present invention. In the manufacturing of this embodiment, first, an n''- layer with an i thickness of 0.51 Im and an impurity concentration of 5 x 10''cn-3 is deposited on an iron-doped semi-insulating InP substrate 10 having an (ioo) plane by, for example, vapor phase growth. After growing the 1nP layer 12, the film thickness is 1.5 μm and the impurity concentration is I x 10” -
3 n-InGaAs layer 13 is grown. Next, film thickness 14+m, impurity concentration 8X 10" an-3 n-I
An nP layer 14 is formed. After forming, for example, 5i02Jl on the surface of the wafer thus obtained, one region is selectively removed by a photoresist process. Next, using this 5i02 film as a mask for impurity diffusion, for example, Zn5P' The wafer is placed in a closed tube that is evacuated to a high vacuum using 2 as a diffusion source, and after sealing, heat treatment is performed at around 520° C. for several minutes to form a p+ region 5 for selective diffusion of Zn. The tip of region 15 is n--InGaA
The heat treatment time is adjusted so that the s-layer 13 is reached. Next, after forming 5102M again, a region of 5i02 overlapping with a region of the p10 region 15 is removed by the photoresist process as above, and then, for example, Zn is diffused using 5i02 as a diffusion mask in the same manner as above. Do this.
ここで上記ウェーハを使用した場合、例えば、520°
Cで45分程度の熱処理により半絶縁性基板10に達す
るように深いp+領域16を形成する。この様な工程を
経たウェーハに絶縁膜として、例えば、Si3N4膜1
7を形成する。この絶縁膜にフオトレジスl−目合せ工
程により電極取り出し窓を上記深いp十領域16上に設
け、n型電極18を設ける。If the above wafer is used here, for example, 520°
A deep p+ region 16 is formed so as to reach the semi-insulating substrate 10 by heat treatment with C for about 45 minutes. For example, a Si3N4 film 1 is applied to the wafer that has undergone such a process as an insulating film.
form 7. In this insulating film, an electrode extraction window is provided on the deep p region 16 by a photoresist alignment process, and an n-type electrode 18 is provided.
最後に、n型電極を取り出すなめに、受光領域を形成す
るp十領域15に近接する領域のn−InP層14及び
n〜−I nGaAs層13を選択的に除去した後、n
”−1nP12上にn型電極19を設けることにより本
実施例のフォトダイオードが得られる。Finally, in order to take out the n-type electrode, after selectively removing the n-InP layer 14 and the n-I nGaAs layer 13 in the region close to the p-type region 15 forming the light-receiving region,
The photodiode of this example is obtained by providing an n-type electrode 19 on the ``-1nP12.
上述しな、本発明の一実施例により得られた素子により
、次のような特性が得られた。即ち、光電変換に関与す
る有効p+拡散径(これは、深いp十領域16と重なっ
ていないP十領域15の有効径に相当する)25pmφ
の素子の一5■バイアス下での素子容量は0.08pF
程度ときわめて低容量であり、波長1.3μmの光パル
スに対する3dB降下の遮断周波数が20GHz以上で
あるという高速性能が得られた。第1図の実施例では、
プレーナ構造での電極領域下のpn接合容容量るいは絶
縁膜を介しての寄生容量が素子容量を大きく限定してい
た従来例と較べて、電極形成域下のpn接合域が半絶縁
基板と接することにより大巾に低減されて低容量化が達
成でき、さらにこの低容量化により光パルスに対する応
答が光励起キャリアの走行時間、即ち、n−−I nG
aAs層13中での走行時間にのみ限定される限界特性
に近い高速性能が得られたものと理解できる。As mentioned above, the following characteristics were obtained from the device obtained according to one embodiment of the present invention. That is, the effective p+diffusion diameter involved in photoelectric conversion (this corresponds to the effective diameter of the P10 region 15 that does not overlap with the deep P10 region 16) is 25 pmφ
The element capacitance under bias is 0.08 pF.
High-speed performance was achieved, with a cut-off frequency of 3 dB drop of 20 GHz or more for optical pulses with a wavelength of 1.3 μm. In the embodiment of FIG.
Compared to the conventional example in which the pn junction capacitance under the electrode region in the planar structure or the parasitic capacitance through the insulating film greatly limits the element capacitance, the pn junction region under the electrode formation region is a semi-insulating substrate. By contacting each other, it is possible to significantly reduce the capacitance and achieve a lower capacitance, and furthermore, due to this lower capacitance, the response to the optical pulse is reduced by the transit time of the photoexcited carriers, that is, n-I nG
It can be understood that high-speed performance close to the limit characteristic limited only by the transit time in the aAs layer 13 was obtained.
(発明の効果)
以上に詳しく説明したように、本発明によれば、プレー
ナ構造であってしかも低容量化が容易であり、ひいては
高速性能に優れたフォトダイオードが提供できる。(Effects of the Invention) As described in detail above, according to the present invention, it is possible to provide a photodiode which has a planar structure, can easily reduce the capacitance, and has excellent high-speed performance.
第1図は本発明によるフォトダイオードの一実施例を示
す断面図、第2図は従来の高速フォトダイオードを示す
断面図、第3図は従来のプレーナ型フォトダイオードを
示す断面図である。
10・・・半絶縁InP基板、11・・・n”−InP
基板、12・・・n十−I nP層、13・・・n−−
InGaAs屑、14−・−n−InP層、15−p+
領領域16−・・深いp十領域、17・・・絶縁膜、1
8・・・n型電極、19・・・n型電極。FIG. 1 is a sectional view showing an embodiment of a photodiode according to the present invention, FIG. 2 is a sectional view showing a conventional high-speed photodiode, and FIG. 3 is a sectional view showing a conventional planar photodiode. 10... Semi-insulating InP substrate, 11... n''-InP
Substrate, 12...n+I nP layer, 13...n--
InGaAs scrap, 14-・-n-InP layer, 15-p+
Territory region 16--deep p region, 17--insulating film, 1
8...n-type electrode, 19...n-type electrode.
Claims (1)
半導体層を有し、該第1の半導体層の一領域を選択的に
第2の導電型の領域に転換することによりpn接合が形
成してあり、このpn接合に入射する光の信号を電気の
信号に変換するフォトダイオードにおいて、前記光の入
射に関与しない前記第2の導電型領域の少なくとも一部
分が前記半絶縁性基板にまで達していることを特徴とす
るフォトダイオード。A first semiconductor layer exhibiting a first conductivity type is provided on one main surface of a semi-insulating substrate, and a region of the first semiconductor layer is selectively converted to a region of a second conductivity type. In a photodiode that converts a light signal incident on the pn junction into an electrical signal, at least a portion of the second conductivity type region not involved in the incidence of light is formed in the semi-insulating region. A photodiode characterized by reaching down to the conductive substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62032998A JPS63199467A (en) | 1987-02-16 | 1987-02-16 | Photodiode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62032998A JPS63199467A (en) | 1987-02-16 | 1987-02-16 | Photodiode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63199467A true JPS63199467A (en) | 1988-08-17 |
Family
ID=12374519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62032998A Pending JPS63199467A (en) | 1987-02-16 | 1987-02-16 | Photodiode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63199467A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2737609A1 (en) * | 1995-07-31 | 1997-02-07 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE OF THE PHOTODIODE TYPE AND METHOD FOR MANUFACTURING THE SAME |
-
1987
- 1987-02-16 JP JP62032998A patent/JPS63199467A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2737609A1 (en) * | 1995-07-31 | 1997-02-07 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE OF THE PHOTODIODE TYPE AND METHOD FOR MANUFACTURING THE SAME |
US5880489A (en) * | 1995-07-31 | 1999-03-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor photodetector |
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