JPS6319909B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a drawing device such as a graphic display device, and in particular to an electronic computer (hereinafter referred to as a CPU).
The present invention relates to a graphic data generation circuit that generates graphic data for drawing an array graphic from a compressed data string of the array graphic transferred from a computer.

In graphic processing such as computer graphics, for example, figures in which a group of figures are arranged in an array, such as an array figure or an array figure, can be Graphics arranged in an array, that is, nested array graphics, are often processed. Such an array figure can be expressed by removing redundant data by introducing array data that defines the arrangement rules, so that significant data compression can be achieved by expressing the array figure. Actually for the integrated circuit mask design
The CAD system handles array figures efficiently by introducing the above array data. The array data consists of four types of data (M, N, △X, △Y). The data shall be arranged in M rows and N columns. In the following description, an array figure of M rows and N columns is defined as the 1st row, 2nd row, . . . Mth row in the X direction, and the 1st column, 2nd column, . . . Nth column in the Y direction.

When the array data (M, N, △
X, ΔY) and one bit of graphic data, and therefore the amount of data is compressed to about 1/M×N. Also, if the array is nested, that is, the array data (M ₂ , N ₂ , △X ₂ , △Y ₂ )
The figures obtained by arranging the shapes are further arranged as data (M ₁ ,
N ₁ , △X ₁ , △Y ₁ ), the amount of data is approximately (M ₂ ×N ₂ ) × (M ₁ ×N ₁ )
It can be seen that the data can be compressed to 1/2 of the original size, resulting in significant data compression.

The aforementioned data compression representations are currently being considered in computer graphics graphics processing software. However, the hardware of plotting devices such as graphic display devices is not configured to be able to process the compressed data representations described above, that is, it does not have circuitry for expanding arrays. For this reason, the software has to expand the compressed expression, which places an extra burden on the software and prevents the reduction of processing time.
In addition, since the expanded results are transferred to the hardware mentioned above, most of the transfer time is spent transferring data that is originally redundant.
This prevents speeding up of drawing time.

An object of the present invention is to reduce the amount of transferred data by generating a figure data position for drawing a nested array figure from a nested array data string, thereby speeding up the drawing process. The purpose is to provide circuits.

Another object of the present invention is to provide a graphic data generation circuit that reduces unnecessary burden on software by adopting a circuit configuration that can handle compressed expression in software as is.

According to the present invention, in order to draw a nested array figure from a compressed representation by nesting of array data, data that defines the arrangement rules for array figures that are nested to L levels and arranged in an array, that is, array data, is an array circuit that sequentially calculates the placement positions of all array elements of the nested array figure based on the array data of the array memory under the control of a nesting circuit described below; a state memory for temporarily storing an intermediate state of array expansion of each array data; and the array memory;
By having the state memory and the nesting circuit that controls the array circuit, it is possible to obtain a graphic data generation circuit that develops array data nested up to the maximum L level and generates the arrangement positions of all array elements.

The figure data generation circuit of the present invention can generate the figure data arrangement position for drawing the array figure from a data string compressed and expressed using the nested array data of the nested array figure. The amount of data can be significantly reduced, and therefore, compared to conventional hardware, transfer time can be shortened and drawing speed can be increased.

This graphic data generation circuit can also be configured to handle compressed expressions as they are, which reduces the burden on software and shortens processing time compared to the prior art.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is an example of a nested array figure. There are two levels of nesting. In other words, the diagonally lined rectangle represents level 2 array data (2, 2, △
X ₂ , △Y ₂ ) are arranged in 2 rows and 2 columns, and the whole is further divided into level 1 array data (2, 3, △X ₁ ,
ΔY ₁ ) and arranged in 2 rows and 3 columns. In this case, the compressed representation is [(level 1 array data)(level 2
array data) (figure data)], that is, [(2,
3, △X ₁ , △Y ₁ ) (2, 2, △X ₂ , △Y ₂ ) (XA,
YA, WA, HA)]. However, one example of rectangular representation is graphic data XA, YA, WA, HA.
That is, it is expressed by the coordinates of the lower left vertex (XA, YA), width (WA), and height (HA). Now, assuming that each data requires one word, in the case of non-compressed representation, (2 × 2) × (2 × 3) × 4 = 96 words are required, whereas in the case of compressed representation, in this example, There are 4 words of data and 2 x 4 = 8 words of array data, so 12
Words are sufficient and have a significant compression effect.

The placement position of each rectangle in Figure 1 is the array element position at array level 1 (m ₁ , n ₁ ) and array level 2
If the array element position in is (m ₂ , n ₂ ), then (Equation 1)
It can be expressed as

[(m ₁ -1)△X ₁ + (m ₂ -1)△X ₂ , (n ₁ -1)△Y ₁ + (n ₂ -1)△Y ₂ ]
...(Formula 1) However, 1≦m ₁ ≦2, 1≦m ₂ ≦2 1≦n ₁ ≦2, 1≦n ₂ ≦3 For example, the arrangement position of the dotted rectangle is array level 1
The array element position is (2, 1) at array level 2, and (2, 3) at array level 2, i.e. m ₁ = m ₂ = 2, n ₁ = 1, n ₂
=3, and (Formula 2) is obtained.

(△X ₁ +△X ₂ , 2△Y ₁ ) ...(Formula 2) Therefore, when the array level is generally up to L level, this compressed expression is [(M ₁ , N ₁ , △X ₁ , △Y ₁ )
(M ₂ , N ₂ , △X ₂ , △Y ₂ )…(M ₁ , N ₁ , △X _L ,
△Y _L )], and the arrangement positions where the element positions at each array level are (m ₁ , n ₁ ), (m ₂ , n ₂ ), ... (m _L , n _L ) are given by (Equation 3). Express.

[(m ₁ -1)△X ₁ +...+(m _L -1)△X _L , (n ₁ -1)△Y ₁ +...+(n _L -1)△Y _L ]
...(Equation 3) However, 1≦m ₁ ≦M ₁ , ...1≦m _L ≦M _L 1≦n ₁ ≦N ₁ , ...1≦n _L ≦N _L m ₁ , ..., M _L , n ₁ ,...n _L are all integer values.For simplicity, only the X part of (Equation 3) will be considered in the following explanation. In the X part of (Formula 3), if the sum up to level j (j is an integer value satisfying 1≦j≦L) is written as X _j , it can be rewritten as (Formula 4).
From (Equation 4), it can be seen that the arrangement position Xj when expanded from level 1 to level j can be obtained by adding the arrangement positions of each level. Therefore level 1
The arrangement position Xj when expanded from level to level j is rewritten as shown in (Equation 5) using the arrangement position Xj _-1 when expanded from level to level j-1.

X _j = ₍ m ₁ -1)△X ₁ + (m ₂ -1)△X ₂ + ...+ (m _j -1)△X _{j ...} (Formula 4 ₎ −1) △X _j other X ₀ = O
...(Formula 5) 1≦j≦L Based on (Formula 5), the L-level nesting array is expanded as follows. Based on (formula 5),
The development of L-level nesting in the X part of (Formula 3) will be described below.

In the X part of (Formula 3), the number of array elements at each level is M ₁ at level 1, M 2 at level ₂ , etc.
At level L, there are M _L pieces. Therefore, the number of possible arrangements of the X portion is M ₁ ×M ₂ ×...× _ML . That is, to expand the L-level nesting array, it is sufficient to create all the combinations of _{m 1} , m ₂ . That is, after determining one position of each element of m ₁ , m ₂ ...m _L , (m ₁ -1)△X ₁ , (m ₂ -1)△X ₂
It turns out that all you have to do is add them all.

(Formula 5) is (m ₁ -1)△X ₁ , (m ₂ -1)
All additions of △X ₂ , ..., (m _L −1) △X _L are
This shows what can be done using one adder.
That is, the sum up to level j, i.e. (m ₁ -1)
△X ₁ + (m ₂ -1) △X ₂ +...+ (m _j-1 -1) △X _j-1
+(m _j -1)△X _j is the sum up to level j-1, that is, (m ₁ -1)△X ₁ + (m ₂ -1)△X ₂ +...+
The sum of (m _j-1 −1)△X _j-1 and (m _j −
1) Obtained by adding △X _j .

In the above explanation, level j (j is 1≦j≦
The state data of the X _part ( _{m j} , X _j-1 ).
The same applies to the Y part of (Formula 3), and therefore,
The state data of level j is (m _j , n _j , X _j , Y _j ).

FIG. 6 shows a processing flow for creating all combinations of m ₁ , m ₂ . . . m _L and calculating the X part of (Equation 3) each time. In the following explanation, determining the element position at levels other than level L is called partial expansion, and level L
Changing the element position m _L from 1 to M _L is called complete expansion.

Furthermore, the memories that store the above-mentioned state data and array data during expansion are called state memory and array memory, respectively. These memories have a capacity to store at least L pieces of state data, and are capable of reading and writing the state data of that level using the level value as an address. Furthermore, it is assumed that the array memory 12 stores L array data prior to L-level nesting expansion.

Expansion of the L-level nesting array will be explained below based on FIG. 6. The status data is the status data of the X portion.

First, the values of element positions are determined to 1 in the order of m ₁ , m _{2 .} . . , m _L- 1 up to level L-1. Then, the value of (Equation 5) is calculated each time. That is, m ₁ is 1
Make it. From (Equation 5), X ₁ at this time is X ₀ + (m ₁
-1) △X ₁ . m ₁ = 1, △X ₁ and X ₀ = 0 of the array data to the level read from the array memory
to obtain X ₁ =0. Level 1 state data (m ₁ =1, X ₁ =0) is therefore stored at address value 1 in the state memory. Next, set m ₂ to 1. Similarly, X ₂ is calculated from (Equation 5) as X ₂ = X ₁ +
It is given by (m ₂ -1)△X ₂ . The level 1 state data X ₁ is read from the state memory and the level 2 array data ΔX ₂ is read from the array memory to obtain X ₂ =0. Therefore, level 2 state data (m ₂ = 1, X ₂
=0) is stored in the state memory. This process is then repeated up to level L-1.

Next, since there is no further nesting at level L, (Equation 5) is calculated each time while changing the element position m _L from 1 to M _L. The M _L values calculated in this complete expansion become the final arrangement.
First, let m _L be 1. In this case, (Equation 5) is X _L =
X _L-1 + (m _L -1)△X _L. Therefore, m _L =1,
Using X _L -1 of the L level L-1 state data read from the state memory and ΔX _L of the level L array data read from the array memory, (Equation 5) is calculated to obtain X _L =0. This is the first final placement position. Status data of level L (m _L = 1, X _L
=0) is likewise stored in the state memory. Next, it is determined whether complete expansion at level L has been completed. That is, m _L (=1) of the state data of level L of the state memory is compared with M _L of the array data of level L of the array memory. If they are equal, complete expansion ends. If they are not equal, increase m _L by 1 and calculate (Equation 5). That is, m _L = 2, the state data of level L-1 read from the state memory.
X _L-1 , using △ _XL of the level L array data read from the array memory, X _L = X _L-1 + (m _L -1)
Obtain △X _L = △X _L.

Hereinafter, the state memory and array memory will be omitted since they are handled in the same way.

When complete expansion at level L is completed, the process returns to the next lower level, that is, level L-1, and similarly examines the possibility of partial expansion of element position m _L-1 . m _L-1
If not = M _L-1 , m _L- 1 is increased by one, that is, partial expansion is performed, and the complete expansion at level L described above is performed again. If m _L-1 = M _L-1 at level L-1, partial expansion is not possible, so we return to the next level below and check whether partial expansion is possible in the same way. If partial expansion is possible at level L-2, then partial expansion is performed on element position m L-1 at level _L-1 to 1,
Furthermore, complete expansion at level L is performed. In other words, if partial expansion is possible at a certain level, then
The element positions from the next higher level to level L-1 are sequentially set to 1, and (Equation 5) is calculated each time, and then completely expanded at level L to calculate the final arrangement position.
All combinations end when it is determined that partial expansion is not possible at level 1. At this time, all combinations of the X part of formula (3) have been calculated. The above explanation also applies to the Y part of (Formula 3).

From (Formula 5) and the above explanation, the latest summation at each level, that is (Formula 4), is maintained for each level, and from the expansion of level j, level j−1
The level j− that was maintained when returning to the expansion of
By referring to the total sum of 2, X _j-2 , it can be seen that only the addition of (Equation 5) is sufficient.

FIG. 2 is an example of a compressed data string sent from an electronic computer. The array code indicates that array data (M, N, ΔX, ΔY) follows next, and the corresponding array end indicates the valid range of this array data. The pattern code indicates that pattern data follows, in the example a rectangle (X ₃ , Y ₃ , W ₃ ,
_H3 ) continues. Therefore, Fig. 2 shows the rectangle (X ₃ ,
Y ₃ , W ₃ , H ₃ ) is the array data (2, 2, △X ₂ ,
△Y ₂ ) and further array data (2,
3, △X ₁ , △Y ₁ ).
This data string represents the nested array figure of FIG.

FIG. 3 is a block diagram of a graphic display device using the present invention. In the figure, reference number 1 is an electronic calculator, 2 is a nesting circuit, and 3 is a nesting circuit.
is an array memory, 4 is a state memory, 5 is an array circuit,
6 is a pattern generator, 7 is a D/A conversion circuit, and 8 is a cathode ray tube.

A data string of a compressed representation of a nested array figure as shown in FIG. 2 is sent from the electronic computer 1.
The signal is sent to the nesting circuit 2, array memory 3, and pattern generator 6 through the signal line 100.
When the nesting circuit 2 detects an array code in the data string, it increments a built-in nesting level counter by 1, and at the same time sends this nesting level as a write address to the array memory 3 through the signal line group 101, and at the same time sends the nesting level to the array memory 3 as a write address. A data write pulse is generated and sent to the array memory 3 through the signal line group 101, and each array data in the data string is stored in the corresponding nesting level address of the array memory 3. The nesting circuit 2 also decrements the nesting level counter by 1 when detecting the array end. Furthermore, when the nesting circuit 2 detects a pattern code other than the array code and the array end, if the current nesting level counter is not ▼0▼, that is, if there is an array, the nesting circuit 2 performs the expansion operation of the nesting array as detailed in FIG. Execute.

The array memory 3 is a memory that stores L pieces of array data, and the state memory 4 stores L pieces of state data (m _j , n _j , X _j , Y _j ) that are being expanded, that is, the current level at level j. This memory stores m _j and n _j indicating the progress of nesting expansion of j, and the arrangement position X _j that is added up to the level j given by (Equation 4), as well as Y _j .

Write and read addresses for both memories 3 and 4 are generated by nesting circuit 2 and sent to both memories 3 and 4 via signal line group 101. The contents of both memories 3 and 4 are transferred to signal lines 104 and 10, respectively.
5 to the array circuit. The write data of the array memory 3 is array data sent from the electronic computer 1 through the signal line 101, while the state memory 4
The write data is the aforementioned state data sent from the array circuit 5 through the signal line 106.

The array circuit 5 receives array data (M, N, △X, △
The expansion circuit of Y) sequentially calculates the placement positions of all array elements. Although the array circuit 5 only has an expansion circuit for at most one array data (M, N, △X, △Y) at the same time, due to the function of the nesting circuit 2 described in detail in Fig. 4, it can expand up to the L level. It is possible to expand nested arrays. Array circuit 5
Each arrangement position sequentially calculated in is sent to the pattern generator 6 through a signal line 107.

The pattern generator 6 adds each arrangement position sent through the signal line 107 to the pattern data sent through the signal line 100, and then converts this pattern into drawing data for drawing the pattern. The drawing data generated by this circuit is sent to the D/A conversion circuit 7 through the signal line 108. After converting the digital signal into an analog signal, the D/A conversion circuit 7 connects the signal line 10 to the signal line 10.
9 to the X and Y deflection coils of the cathode ray tube 8, and a desired figure is displayed on the cathode ray tube surface.

FIG. 4 is a diagram specifically showing the main parts of the nesting circuit 2, which is a component of the present invention. In the figure, reference number 21 is a decoder, 22 is a nesting level counter, 23 is an expansion level counter, 24 is a selector, and 25 is a comparison circuit. Array memory 3, state memory 4, and array circuit 5 are also shown for explanation. The operation will be explained below using FIGS. 1 and 2 as examples.

The operation of the nesting circuit 2 includes a nesting operation and an expansion operation depending on the data type of the compressed data string. The nesting circuit 2 performs a nesting operation when the decoder 21 decodes the compressed data string sent from the electronic computer 1 through the signal line 100 and detects an array code. That is, upon detecting the array code of the compressed data string shown in FIG. 2, the decoder 21 sends a count-up pulse to the nesting level counter 22 via the signal line 202 to increment the level value by one. At the same time, the array circuit 5 is commanded to stop via the signal line 204, the selection condition of the selector 24 is set to ▼0▼, the contents of the nesting level counter 22 sent via the signal line 205 are output to the signal line 101, and the array memory 5 is is given as the array data write address. Next, the array data sent thereafter (2, 3, △X ₁ , △Y ₁ )
Sequentially generate write pulses for each data in signal line 2.
01 to the array memory 3 and store the array data (2, 3, ΔX ₁ , ΔY ₁ ) in the memory address specified by the nesting level counter 22.
The above operations are executed every time an array code is detected. Therefore, in the example shown in FIG. 2, in the array memory 3, the address value 1 is (2, 3,
X ₁ , △Y ₁ ), and the address value is 2 (2,
2, △X ₂ , △Y ₂ ) are stored. Further, the nesting level counter 22 is set to "2".
When the decoder 21 detects the array end, it sends a countdown pulse to the nesting level counter 22 via the signal line 203 and decrements the level value by 1.

The nesting circuit 2 starts an expansion operation when the decoder 21 detects a pattern code other than an array code or an array end. The expansion operation implements the nesting expansion flow shown in FIG. 6 based on (Equation 5) described in the explanation of FIG. That is, if the current value of the nesting level counter 22 is ▼0▼, no array is defined for this pattern, so the signal line 204 instructs the array circuit 5 to draw only one figure without expanding the array. command. On the other hand, if it is not ▼0▼, a nesting array is defined, so the array circuit 5 is commanded to start the array operation via the signal line 204, and the selector condition of the selector 24 is set to "1".
The expansion level counter 23 is set to "0" by the signal line 206. The selector 24 selects the contents of the expanded level counter 23 sent through the signal line 208 and sends it as a memory address to the array memory 3 and state memory 4 through the signal line 101. The addressed contents of array memory 3 and state memory 4 are sent to array circuit 5 via signal lines 104 and 105, respectively. The expansion operation of the nesting array ends when the value of the expansion level counter 23, which started at the initial value ▼0▼, becomes ▼0▼ again due to the up-down pulse sent from the array circuit 5 through the signal line 103, and the signal line 207 This notification is sent to the decoder 21, and the retrieval of the compressed data string is started again.

The comparison circuit 25 compares the contents of the nesting level counter 22 sent via the signal line 205 and the signal line 2.
Compare the contents of 2 and the contents of the expansion level counter 23 sent through the signal line 208, and if the two values are equal, set the signal line 209 to ▼1▼ and command the array circuit 5 to complete expansion, and if they are not equal, ▼0 ▼
Commands partial expansion.

FIG. 5 is a diagram specifically showing the array circuit 5 which is a component of the present invention. In the figure, reference number 5
1 is an M selector, 52 is an N selector, 53 is an M counter, 54 is an N counter, 55 is an M comparison circuit,
56 is an N comparison circuit, 57 is a timing circuit, 5
8, 59 are selectors, 60, 61 are adder circuits, 6
2 is the X register, 63 is the Y register, 64, 65
is a selector. Also, an M selector 51, an N selector 52, an M counter 53, an N counter 54,
The M comparison circuit 55 and the N comparison circuit 56 constitute an expansion control section 66 that controls expansion at each level, and the selectors 58 and 59, the adder circuits 60 and 61, the X register 62, and the Y register 63 are explained in FIG. (Equation 5), that is, constitutes a placement position calculation unit 67 that calculates the placement position.

First, the expansion control section 66 will be explained. The expansion control section 66 controls partial expansion and complete expansion in the explanation of FIG. M selector 51 is state memory 4
Either the state data m or the initial value ▼0▼ sent from the timing circuit 57 through the signal line 105-M is selected by the expansion mode signal sent from the timing circuit 57 through the signal line 509, and is sent to the M counter 53 through the signal line 501. In the case of partial expansion, the expansion mode signal becomes ▼0▼ and status data m is sent, and in the case of complete expansion, it becomes ▼1▼ and the initial value ▼0▼ is sent to the M counter 53 as the initial value. The same applies to the N selector 52. The M counter 53 is a counter that controls the progress of expansion, and is m _j in the explanation of FIG.
An initial value is set at the start of partial expansion or complete expansion, and is incremented by 1 by a count-up pulse sent through the signal line 503 each time (Equation 5) is calculated by the arrangement position calculation unit 67 according to a command from the timing circuit 57. That is, m _j =m _j +1. The contents of the M counter 53 are sent to the state memory 4 via the signal line 106-M and at the same time to the M comparison circuit 55. The same applies to the N counter 54.

The M comparison circuit 55 compares the contents of the M counter 53 with the array data M sent from the array memory 3 via the signal line 104-M, detects the end of array expansion of the array data M in the row direction, and sends the result as a signal. line 505 to timing circuit 57; Similarly, the N comparison circuit 56 detects the column direction, that is, the end of array expansion of the array data N, and sends the result to the timing circuit 57.

Next, the arrangement position calculation section 67 will be explained. The arrangement position calculation unit 67 calculates (Equation 5) in the explanation of FIG. Signal line 104 to selecta 58
The array data ΔX of the array memory 3 sent by the line 105-X and the state data X' of the state memory 4 sent by the signal line 105-X are input. The selector 58 is connected to the timing circuit 5 by a signal line 516.
When the selection signal sent from 7 is ▼0▼, the above-mentioned △X is selected, and when it is ▼1▼, the above-mentioned ^X'1 is selected and sent to the adder circuit 60 via the signal line 510. Selector 5
9 similarly selects either the array data ΔY in the array memory 3 or the state data Y' ¹ in the state memory 4 and sends it to the adder circuit 61. Adder circuit 60 adds the output of selector 58 and the output of selector 64 sent via signal line 514, and sends the result to X register 62 via signal line 512. At this time, the selector 64
is the value of the selection signal sent from the timing circuit 57 via the signal line 517, which selects either the contents of the Enter. The adder circuit 61 and selector 65 also have the same configuration as the adder circuit 60 and selector 64 described above. The output of the adder circuit 60 mentioned above is connected to the signal line 5.
07, it is set in the X register 62 by the X set signal sent from the timing circuit 57.
Further, the output of the X register 62 is sent to the state memory 4, the selector 64, and the pattern generator 6 via the signal line 107-X. Similarly, the output of the adder circuit 61 is set in the Y register 63, and the signal line 107-Y connects the state memory 4 and the selector 65.
and sent to the pattern generator 6.

The timing circuit 57 generates various signals for controlling the expansion control section 66 and the placement position calculation section 67 as described above.

As explained above in detail using the drawings, according to the present invention, in order to draw a nested array figure as shown in FIG. 1, nested array data as shown in FIG. 2 is compressed. From the expressed data string, it can be seen that the graphic data arrangement position for drawing this array graphic can be generated based on the expansion rule explained in FIG.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a nested array figure, FIG. 2 is a diagram showing an example of a data string in compressed representation, FIG. 3 is a block diagram of a graphic display device using the present invention, and FIG. 4 5 is a diagram specifically showing the main part of the nesting circuit 2, which is a component of the present invention. FIG. 5 is a diagram specifically showing the array circuit 5, which is a component of the present invention. FIG. FIG. 3 is a processing flow diagram of expansion. In the figure, 1...electronic computer, 2...nesting circuit, 3...array memory, 4...state memory, 5...
Array circuit, 6...pattern generator, 7...D/
A converter, 8... Cathode ray tube, 21... Decoder, 22
...nesting level counter, 23...expansion level counter, 24...selector, 25...comparison circuit,
51...M selector, 52...N selector, 53...M
Counter, 54...N counter, 55...M comparison circuit, 56...N comparison circuit, 57...timing circuit,
58, 59...Selector, 60, 61...Addition circuit,
62...X register, 63...Y register, 64,6
5... Selector, 66... Deployment control section, 67... Arrangement position calculation section.

Claims (1)

[Claims] 1 an array memory that stores data (referred to as array data) that defines L array rules for array figures arranged in a nested manner up to L (L is a positive integer) level; Based on the array data and the intermediate state information of the array expansion at each level, the arrangement positions of all array elements are sequentially calculated while the nested array figure is expanded into an array, and the intermediate state information of each level of the array expansion is calculated. a state memory for temporarily storing the intermediate state information of each level in the array expansion of the array data generated by the array circuit;
A graphic data generation circuit comprising: a nesting circuit for instructing a level at which array expansion is to be executed next in the array circuit based on intermediate state information of expansion of the current level generated by the array circuit.