JPS6319899B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital circuit testing device used for inspecting a defective state of a digital circuit device.

Conventional test equipment outputs a test pattern from a pattern generator to the test object, such as a digital circuit (one printed board) or an IC memory element, stores the operation results in a memory, and compares them with predicted data to determine pass/fail. was doing.

However, the test equipment described above generally has a slow operating speed and requires a large configuration when attempting to generate a complex test pattern, so that only simple test patterns can be generated.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and to provide a test device that can generate patterns to a device under test at the operating speed of the device under test and store processed data at any location in a memory.

The present invention includes a CPU that executes programs using a microprocessor, a ROM section that has a read-only memory in which inspection patterns, verification data, execution programs, etc. are written, and a random access memory that is used for calculations etc. have
A first part that uses a high-speed random access memory to store the test pattern given by the RAM part and outputs the test pattern by periodically repeating the start address to the end address.
It consists of a high-speed RAM section and a distribution section that sends the operating clock of the device under test as a read clock to the first high-speed RAM section, and outputs the test pattern read from the first high-speed RAM section to the device under test. a pattern generator and a second high-speed memory that uses a high-speed random access memory to store processed data and allows the controller to determine the completion state of stored processed data;
A pattern generation/verification device comprising a memory including a RAM section and a selection section that outputs processing data from the device under test, a write clock, and a write start pulse to the second high-speed RAM section. be.

Next, the configuration of the present invention will be explained in detail with reference to the drawings. In Fig. 1, the control unit 1 includes a CPU 1a, a ROM
The CPU 1a is composed of a section 1b and a RAM section 1c, and uses an 8-bit microprocessor.
The ROM section 1b is composed of a read-only memory, etc., and an execution program, various patterns, collation data, etc. are written in advance.
The RAM section 1c is composed of a random access memory and the like, and is used by the CPU 1a for calculations, temporary data saving, and the like. The CPU 1a executes the program in the ROM part 1b, uses the RAM part 1c to create complex patterns, reads out various patterns in the ROM part 1b, and outputs the patterns to a pattern generator. In addition, a request is made to write the processing results of the device under test 4 to the storage device, and after the received processing data is stored in the storage device, the verification data in the ROM section 1b is compared with the contents of the storage device to determine the quality of the test results. do. Next, the pattern generator will be explained.

A specific example of the pattern generator is comprised of a high-speed RAM section 2a and a distribution section 2b, as shown in FIG. The high-speed RAM section 2a includes high-speed random access memory (high-speed RAM) 9 and registers (REG).
5, 6, a counter 7, and a comparator 8. The control unit 1 holds the read start address in REG6 and the read end address in REG5. A test pattern is instantaneously stored in the high-speed RAM 9 by the control section 1, and the test pattern is read out using an address given from the counter 7. The counter 7 starts counting from the read start address given by the REG 6 using the read clock of the read control section 11. The output is given to the high speed RAM 9 and also to the comparator 8, which compares the value given from the counter 7 with the value given from the counter 7.
The read end address given by REG5 is compared, and when they match, a pulse is output to the counter 7 to set the read start address of REG6 as an initial value. In this way, the test pattern from the read start address to the end address can be read out periodically from the high speed RAM 9.

The high-speed RAM 9 is controlled by the CPU 1a of the control unit 1.
The test pattern of the ROM section 1b is as if it were the control section 1.
Internal memory can be written to within an instant using direct memory access (DMA) transfers.
Due to this operation, the control unit 1 is forced to read out one periodic pattern from the high-speed RAM 9.
Transfer new inspection patterns to high-speed RAM9 using DMA transfer
Since the pattern being read out can be instantly switched to another periodic pattern.

The distribution section 2b includes a clock source 10 and a readout control section 1.
1. A clock source 10 composed of a distributor 12 generates clocks and pulses suitable for the device under test 4 and supplies them to the readout control section 11 and the distributor 12. The read control section 11 sends out the clock and pulses supplied from the clock source 10 as a read clock to the high speed RAM section 2a according to the type of test pattern under the control of the control 1. The distributor 12 is capable of high-speed 8-bit parallel output, and outputs the test pattern read from the high-speed RAM 9 to the device under test 4 together with a clock.

Next, a specific example of the memory device will be explained.
As shown in FIG. 1, the memory 3 is composed of a high speed RAM section 3a and a selection section 3b. The selection unit 3b is composed of a selector 19 and a write control unit 20, and the write control unit 20 uses the clock and pulses supplied from the device under test 4 to hold the specified value for storage at an arbitrary location given by the control unit 1. The counter 17 in the high-speed RAM section 3a is counted until it reaches that value using the write clock, and when it reaches the same value, a write start pulse is generated and the write clock is started at high speed.
The data is sent to the RAM section 3a. The selector 19 is capable of high-speed 8-bit parallel input and transfers the processing data supplied from the device under test 4 to the high-speed RAM section 18 in the high-speed RAM section 3a. The high-speed RAM section 3a is a high-speed random access memory (high-speed RAM) 1
8, a monitoring circuit 16, and a counter 17. A counter 17 counts with the supplied write clock, using the selector 19 of the high-speed RAM section 18, a write start pulse specifying an arbitrary location of the processing data of the write control section 20, a write clock, and the processing data of the device under test 4. By using the output as an address, processing data can be stored at any location. The monitoring circuit 16 decodes the write request given by the control unit 1 and the carry signal of the counter 17 to create a write completion state, and the control unit 1 constantly monitors this state to control processing from the device under test 4. Data can be read from the high-speed RAM 18 into the control unit 1.

Next, the operation of the present invention will be explained using the waveform diagram shown in FIG. Now, to explain the case where the device under test 4 is a TV signal encoder and decoder (hereinafter referred to as TV signal CODEC) as an example, the clock source 10 of the pattern generator generates F, H, Q, and S as shown in the figure. The signal is supplied to the distributor 12 and the readout control section 11. Here, Q is a 14MHz clock, S is a 7MHz clock,
F is a frame synchronization signal H is a horizontal synchronization signal, and H' is an enlarged part of H. Now, assuming that a ramp (staircase wave) is given to the test pattern, the control section 1 first causes the pattern generator REG6 to hold the read start address 0 and REG5 to hold the read end address 454, and then causes the high speed RAM 9 to hold the read start address 0 and the read end address 454, respectively.
Ramp (staircase wave) pattern in ROM section 1b
Write instantly using DMA transfer. Thereafter, the counter 7 is counted with the initial value of 0 using the S clock which is the read clock from the read control unit 11, and the comparator 8 compares the output of the counter 7 with the value 454 of REG5. A pulse is applied to the counter 7 to return the value of the counter 7 to the initial value of 0. In this way, the counter 7 repeats the output from 0 to 454 and gives the value to the high speed RAM 9 as an address, so that a ramp (staircase wave) pattern is periodically read out from the high speed RAM 9. The read pattern is held in a register by the distributor 12 once with a Q clock, adjusted to match the timing of the TV signal CODEC, and outputted to the TV signal CODEC. The processing data of TV signal CODEC is F
This is the relationship between H and L, and one TV screen (F pulse)
In between, H is a total of 525 lines from 0 to 524 as shown in L. In order to store all this data in the storage device 3, a large capacity memory is required.
In order to perform line-by-line verification, it is necessary to store an arbitrary location of the processed data (the relationship between H', Q, and S in FIG. 4). For this reason, from the control section 1 to the selection section 3
The line number is designated to the write control unit 20 of b.
Now, if you memorize the 100th line (H'), the control section 1
After the value 100 is held in the write control unit 20, the internal counter is initialized with F and starts counting with H. When the 100th line (H') is reached, the selector 19 supplies the processing data distributed by the S and Q clocks at the timing of the S clock as a write clock to the high speed RAM 18 and the counter 17, and the counter is counted by the S clock. 17
The output of is used as the address of the high-speed RAM 18 to store the processed data in the section H'. At that time, the monitoring circuit 1
6 can know the completion of writing by decoding the carry signal of the counter 17a.

By checking the status of the monitoring circuit 16, the control unit 1 learns that the processed data of the section H' has been stored in the high-speed RAM 18, and compares the verification data in the ROM unit 1b with the processed data in the high-speed RAM 18 to determine whether it is good or bad. make a judgment.

Although only the ramp (staircase wave) pattern has been described above, the same can be done when the test pattern is high-speed data (7 to 14 MHz) such as color bars and monochrome bars.

Also, as an application of the above, visually moving patterns can be generated. First, the control unit 1
Then, read start address 0 to REG6 of the pattern generator and read end address 454 to REG5.
is stored in the high-speed RAM 9 and is stored in the ROM section 1b of the control section 1.
Instantly write the blacking pattern within using DMA transfer. Thereafter, the counter 7 counts with the initial value set to 0 using the S clock which is the read clock from the read control unit 11, and the output of the counter 7 and the output of the counter 7 and the comparator 8 count.
The value 454 of REG5 is compared and if they match, a pulse is given from the comparator 8 to the counter 7 to return the value of the counter 7 to the initial value of 0. In this way, the counter 7 repeatedly outputs 0 to 454 and gives that value as an address to the high-speed RAM 9, so it is fast.
The blacking pattern is read from RAM9. The read pattern is held in a register by the distributor 12 once with a Q clock, adjusted to match the timing of the TV signal (CODEC), and outputted to the TV signal CODEC. At this point, the entire screen appears to be gray visually. The control unit 1 sequentially checks all 525 lines of the processed data of the TV signal CODEC starting from 0, and if it is normal, then displays the calculation result (level that appears white on the screen) using the RAM unit 1c on the left side of the screen. DMA transfer and write to high-speed RAM 9 by aligning them side by side. Since the reading start address and end address are not changed, counter 7 takes a value between 0 and 454 and is executed at high speed.
Read blanking pattern ⁺ white level from RAM9. When this is outputted to the TV signal CODEC by the distributor 12, a single white vertical line appears on the leftmost edge of the screen, and the rest of the line appears gray. In this way, by sequentially calculating using the RAM unit 1c by the control unit 1 and changing the location of the white vertical line for DMA transfer to the high-speed RAM 9, it is possible to visually change the position of the white vertical line up to the right edge of the screen line by line. A white line appears to be moving on the screen. At this time, the control unit 1 performs verification only on lines with a white level, and performs control to sequentially generate a white level on the next line only when the line is normal. In other words, each time a white level is generated for one line, the processed data is checked through the TV signal CODEC.

Next, as a second embodiment, a second distributor 2c is added to the pattern generator as shown in FIG. 3, and a second selection section 3c is added to the memory as shown in FIG. 4 to make it versatile. The present invention will be explained.

In FIG. 3, the first distributor 2b in the pattern generator is the same as distributor 2b in FIG.
The second distributor 2c includes a readout control section 13 and a distributor 1.
4. Consisting of a distributor 15, readout control section 1
3 sends out the clock given from the device under test 4 as a read clock to the high speed RAM section 2a under the control of the control section 1 depending on the type of test pattern. In this case, one of the read control units 11 and 13 is always selected by the control unit 1. The distributor 14 is capable of low-speed 8-bit parallel output and outputs the test pattern read from the high-speed RAM 9 to the device under test 4. The distributor 15 is capable of low-speed serial output, converts the test pattern read from the high-speed RAM 9 from parallel to serial, and sends it to the device under test 4. By selecting one of the distributors 12, 14, and 15, the pattern generator is capable of outputting three types of test patterns for the device under test 4, making it versatile.

In FIG. 4, the first selection section 3b in the memory is the same as the selection section 3b in FIG. The second selection section 3c includes selectors 21 and 22 and a write control section 23, and the write control section 23 operates in the same manner as the write control section 20. The selector 21 is capable of low-speed 8-bit parallel input and transfers processing data supplied from the device under test 4 to the high-speed RAM 18. The selector 22 is capable of low-speed serial input, converts the processing data of the device under test 4 from serial to parallel, and transfers it to high-speed RAM.
Transfer to 18. The control unit 1 selects the first selection unit 3b.
When the second selection section 3c is selected, either the selector 21 or the selector 22 is selected. Selector 1
By selecting one of 9, 21, and 22, the memory device has three types of input formats for the device under test 4, making it highly versatile.

For example, high-speed data (7~
14MHz), the first distribution section 2b and the first selection section 3
b is selected, high-speed 8-bit parallel processing is performed by the distributor 12 and selector 19, and the test pattern is the TV signal.
In the case of low-speed data (less than 7 MHz) in the audio part or line output part of the CODEC, the second distributor 2c and second selector 3c are selected and operated, and in the case of low-speed 8-bit parallel, the distributor 14 and selector 21 are operated. , in the case of low-speed serial, the distributor 15 and selector 22 are respectively operated. Further, the first distribution section 2b and the first selection section 3b, and the second distribution section 2c and the second selection section 3c are each switched in pairs by the control section 1.

In the above explanation, the number of types was limited to three, but the number of types can be increased by increasing the number of distribution sections and selection sections.

As described above, according to the present invention, by using a high-speed random access memory, the operating speed is high and the device under test 4 can operate with the operating clock, and it is possible to instantly switch from one periodic pattern to another. By changing the pattern, complex patterns such as moving patterns can be generated, and because they are close to actual movements, omissions at the inspection stage can be greatly reduced. Further, since the storage device can store processing data from the device under test at any location, a pattern generation and verification device with a small capacity can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a waveform diagram showing the signals of each part of the device in the embodiment shown in FIG. 1, FIG. 3 is a block diagram showing details of the pattern generator in another embodiment, and FIG. FIG. 2 is a block diagram showing a memory device in detail. 1...Control unit, 2...Pattern generator, 3...
Memory device, 4...device under test, Q...14MHz clock, S...7MHz clock, F...frame synchronization signal, H, H'...horizontal synchronization signal, L...line number.

Claims (1)

[Claims] 1 A CPU that executes a program using a microprocessor, inspection patterns and verification data,
A control unit consisting of a ROM unit with a read-only memory in which execution programs are written, and a RAM unit with a random access memory used for calculations by the CPU, and a high-speed storage of test patterns given from the control unit. The first high-speed method uses random access memory to output a test pattern that periodically repeats from the start address to the end address.
A pattern generator consisting of a RAM section and a distribution section that sends the operating clock of the device under test as a read clock to the first high-speed RAM section and outputs the test pattern read from the first high-speed RAM section to the device under test. a second high-speed RAM unit that uses a high-speed random access memory to store processed data and allows the control unit to determine the completion state of processed data storage; second high speed
A memory device consisting of a selection section that outputs to the RAM section,
A pattern generation and matching device characterized by comprising: