JPS6319822A - Method and apparatus for dry etching - Google Patents

Method and apparatus for dry etching

Info

Publication number
JPS6319822A
JPS6319822A JP16364586A JP16364586A JPS6319822A JP S6319822 A JPS6319822 A JP S6319822A JP 16364586 A JP16364586 A JP 16364586A JP 16364586 A JP16364586 A JP 16364586A JP S6319822 A JPS6319822 A JP S6319822A
Authority
JP
Japan
Prior art keywords
sample
frequency power
bias voltage
power
sample stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16364586A
Other languages
Japanese (ja)
Other versions
JPH0511413B2 (en
Inventor
Ryoji Fukuyama
良次 福山
Norio Nakazato
仲里 則男
Yutaka Kakehi
掛樋 豊
Makoto Nawata
誠 縄田
Hironori Kawahara
川原 博宣
Atsushi Ito
温司 伊藤
Yoshinao Kawasaki
義直 川崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16364586A priority Critical patent/JPS6319822A/en
Publication of JPS6319822A publication Critical patent/JPS6319822A/en
Publication of JPH0511413B2 publication Critical patent/JPH0511413B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To facilitate etching with high speed, precision and low damage by a method wherein a resistant element is provided in parallel with a DC source and the impedance of a whole DC circuit is reduced and a self-bias voltage created by the application of a radio frequency power is controlled by selecting the proper resistance value of the resistance element. CONSTITUTION:High density plasma is generated by a microwave and a negative bias voltage to a substrate 5 is induced by a radio frequency power regardless of whether the substrate 5 is made of insulating material or of non- insulating material. A DC power is applied to a sample table 6 with the radio frequency power and, by connecting a resistance element 17 in parallel with a DC source 8, the applied value of the DC power can be controlled so that the negative bias voltage can be controlled while the applied value of the radio frequency power is kept constant. When the substrate 5 is etched, the applied value of the DC source is so predetermined as to make the negative bias voltage applied to the substrate 5 high. With this constitution, increased ion energy and orientation to the substrate 5 can be given to gas ions and etching with high speed and improved precision can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はドライエツチング処理方法及び、!!!!置に
係り、特に試料に作用するバイアス電圧を制御すること
により高速精密、かつ低ダメージにエツチングを行うの
に好適なドライエツチング処理方法及び装置に関するも
のである。    ′〔従来の技術〕 従来のドライエツチング処理技術としては、例えば、特
公昭60−30098号公報に記載のように対向′IX
fliに高周波電力と共に負電圧を印加し負電圧を一1
00QV印加することによりS i 02とSiのエツ
チング速度比を5とする選択性エツチングを行う技術が
提案されている。しかし、このような従来技術では、負
電圧を印加することによる素子へ与丸るダメージの影警
については配慮されていなかった。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a dry etching treatment method and! ! ! ! In particular, the present invention relates to a dry etching processing method and apparatus suitable for etching at high speed, with precision, and with little damage by controlling the bias voltage applied to a sample. [Prior Art] As a conventional dry etching treatment technique, for example, as described in Japanese Patent Publication No. 60-30098,
A negative voltage is applied together with high frequency power to fli, and the negative voltage is reduced to -1.
A technique has been proposed in which selective etching is performed with an etching rate ratio of 5 between Si02 and Si by applying 00QV. However, such conventional techniques do not take into consideration the possibility of damage to the element due to the application of a negative voltage.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術は、負電圧によるイオンスパブタエネルギ
による素子へのダメージの点について配置ばがされてお
らず、近年のように高集積化ととも磨こ素子の電気的特
性がきびしく制限される状況下では、負の高電圧印加ば
素子の電気的特性に悪影響を与える可能性が生じるとい
う問題があった。
The above-mentioned conventional technology has not been overlooked in terms of damage to the element due to ion spattering energy caused by negative voltage, and in recent years, with the increase in integration, the electrical characteristics of polished elements are severely restricted. However, there is a problem in that applying a negative high voltage may adversely affect the electrical characteristics of the device.

本発明の目的は、試料蚤こ作用するバイアス電圧を制御
することにより、高速精密、かつ低ダメージにエツチン
グできるドライエツチング処理方法及び装置を提供する
ことにある。
An object of the present invention is to provide a dry etching processing method and apparatus that can perform high-speed, precise etching with little damage by controlling the bias voltage that acts on the sample.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、ドライエツチング処理方法を、真空室内に
導入した放電用ガスにマイクロ波と磁界とを作用させプ
ラズマを発生する工程と、該プラズマ中の活性粒子で試
料の被処理面をエツチング処理する工程と、前記試料の
被処理面のエツチング処理工程中に試料が設置された試
料台暑−高周波電力と直a電力とを印加する工程とを有
する方法とし、また、ドライエツチング処理装置を、真
空室と、該真空室内を減圧排気する手段と、前記真空室
内に放電用ガスを導入する手段、マイクロ波を発生させ
る手段と、磁界とを発生させる手段と、前記マイクロ波
と前記磁界との作用により発生するプラズマ中の活性粒
子でエツチング処理される試料が設置される試料台と、
該試料台に電気的に接続された高周波電源と、該高周波
電源と独立にtとな具備したものとすることにより、達
成される。
The above purpose is to perform a dry etching process by applying microwaves and a magnetic field to a discharge gas introduced into a vacuum chamber to generate plasma, and etching the surface of the sample to be processed using active particles in the plasma. and a step of applying high frequency power and direct a power to the sample table on which the sample is placed during the etching process of the surface to be processed of the sample, and the dry etching processing apparatus is equipped with a vacuum a chamber, means for depressurizing and evacuating the vacuum chamber, means for introducing discharge gas into the vacuum chamber, means for generating microwaves, means for generating a magnetic field, and the action of the microwaves and the magnetic field. a sample stage on which a sample to be etched with active particles in plasma generated by is placed;
This is achieved by providing a high frequency power source electrically connected to the sample stage and a power source independent of the high frequency power source.

〔作  用〕[For production]

上記従来技術では抵抗要素を含まず、負のバイアス電圧
は自己バイアス電圧からさらに負のバイアス電圧を高々
する方向の制御が行われる。このような従来の技術では
負のバイアス電圧を高くするには負の直流電圧を高周波
電力印加による自己バイアス電圧より高(することで達
成される。−方、自己バイアス電圧より負のバイアス電
圧を低くする場合には直流電源から負のな圧を発生する
ために流す電流とは逆方向に電流を流さなければならず
ウェハ載置電極の負のバイアス電圧を下げることはむづ
かしかった。
The above-mentioned conventional technology does not include a resistance element, and the negative bias voltage is controlled in such a way that the negative bias voltage is further increased from the self-bias voltage. In such conventional technology, increasing the negative bias voltage is achieved by making the negative DC voltage higher than the self-bias voltage by applying high-frequency power. In order to lower the bias voltage, it is difficult to lower the negative bias voltage of the wafer mounting electrode because it is necessary to flow a current in the opposite direction to the current flowing in order to generate negative pressure from the DC power supply.

本発明では直流電源に並列に抵抗要素を設けることによ
り直流回路全体のインピーダンスを低(している。この
ため、高周波電力印加により発生する自己バイアス電圧
は、抵抗要素の抵抗値を適当に選択することにより負の
バイアス電圧はほぼOから高周波電力印加により発生す
る自己バイアス電圧(抵抗要素の抵抗値が0の場合)ま
での範囲とすることができる。実際には処理時のプラズ
マの安定性が試料の均一処理に悪影響を与える恐れがあ
るため、負のバイアス電圧はプラズマ状態が安定な範囲
に限られる。抵抗要素の抵抗値は処理条件に応じてプラ
ズマの安定性が確保できる範囲内で負のバイアス電圧が
低くなるように選定される。この状態で直流電力を印加
することにより従来より低い負のバイアス電圧から高い
負のバイアス電圧まで、試料曖こ作用する負のバイアス
電圧を制御することが可能となり従来よりバイアス電圧
の制御範囲を広くすることができる。
In the present invention, the impedance of the entire DC circuit is reduced by providing a resistance element in parallel with the DC power source. Therefore, the self-bias voltage generated by applying high frequency power can be reduced by appropriately selecting the resistance value of the resistance element. As a result, the negative bias voltage can range from approximately 0 to the self-bias voltage generated by applying high-frequency power (when the resistance value of the resistance element is 0).In reality, the stability of the plasma during processing Negative bias voltage is limited to a range where the plasma condition is stable, as it may adversely affect uniform processing of the sample.The resistance value of the resistance element should be set to a negative value within a range where plasma stability can be ensured depending on the processing conditions. By applying DC power in this state, the negative bias voltage that affects the sample can be controlled from a lower negative bias voltage to a higher negative bias voltage than before. This makes it possible to widen the control range of the bias voltage compared to the conventional method.

以上により、試料をエツチングする場合には試料に作用
する負のバイアス電圧が高くなるように直流電力の印加
値を設定し、負のバイアス電圧を高くすることによりガ
スイオンに、基板に対するイオンエネルギの増大と方向
性を与えることができ、エツチングの高速化と精密性を
増大することができる。
As described above, when etching a sample, the applied value of DC power is set so that the negative bias voltage acting on the sample becomes high, and by increasing the negative bias voltage, the ion energy for gas ions and the substrate is increased. It is possible to provide enlargement and directionality, and increase the speed and precision of etching.

また、エツチング終点検出後の適切な時点で直流電力の
印加値を抑制して、エツチングの精密性を損わない程度
(素子の電気特性に影響を与えない程度の形状)に負の
バイアス電圧を抑制してエツチングを行う。負のバイア
ス電圧を低くすることによりイオンのエネルギを低下す
ることができ、イオンエネルギに起因する素子ダメージ
を低減できる。
In addition, the applied value of DC power is suppressed at an appropriate point after the etching end point is detected, and a negative bias voltage is applied to an extent that does not impair etching precision (a shape that does not affect the electrical characteristics of the element). Perform etching while suppressing. By lowering the negative bias voltage, the energy of ions can be lowered, and element damage caused by ion energy can be reduced.

このように直流電源回路と抵抗要素とを組合せることに
より試料ダ作用する負のバイアス電圧制御範囲な拡大し
試料の状態に応じたエツチング条件(バイアス電圧)と
することにより高速、精密。
By combining the DC power supply circuit and the resistance element in this way, the control range of the negative bias voltage that acts on the specimen is expanded, and etching conditions (bias voltage) can be set according to the state of the specimen, resulting in faster and more precise etching.

低ダメージなエツチングが可能となる。Etching with low damage is possible.

〔実 施 例〕〔Example〕

以下、本発明の一実施例を第1図により説明する。第1
図で、真空室白目こ放電用ガス導入手段(図示省略)よ
り放電用ガス12を導入し放電用ガスにマグネトロン2
で発生したマイクロ波と磁場コイル3で発生した磁界と
を作用させプラズマ4を発生し、プラズマ4中の活性粒
子で試料、例えば、半導体素子基板(以下、基板と略)
5の表面をエツチングする。なお、真空室内lの圧力は
排気口13より減圧排気手段(図示省略)で排気され所
定の値に保持される。
An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, a discharge gas 12 is introduced from a discharge gas introducing means (not shown) into the white part of the vacuum chamber, and a magnetron 2 is introduced into the discharge gas.
Plasma 4 is generated by interacting the microwaves generated by the magnetic field coil 3 with the magnetic field generated by the magnetic field coil 3, and active particles in the plasma 4 are used to attach a sample, such as a semiconductor element substrate (hereinafter abbreviated as substrate).
Etch the surface of 5. Note that the pressure in the vacuum chamber 1 is evacuated from the exhaust port 13 by a depressurizing exhaust means (not shown) and maintained at a predetermined value.

また、試料台6Iこは抵抗要素17および高周波電源7
と直流電源8とがそれぞれ電気的に接続され、コイル9
とコンデンサ10とは直流電源8へ高周波電源7の影響
を与えないためのローパスフィルター11を構成する。
In addition, the sample stage 6I also includes a resistance element 17 and a high frequency power source 7.
and a DC power supply 8 are electrically connected to each other, and the coil 9
and the capacitor 10 constitute a low-pass filter 11 for preventing the high-frequency power supply 7 from affecting the DC power supply 8 .

ここで高周波電源7は絶縁性の基板5をプラズマに対し
て負にバイアスし、抵抗要素17は直流1!源8と並列
に接続され、抵抗要素17と直流電源8とを組合せるこ
とで負のバイアス電圧を制御することができる。
Here, the high frequency power supply 7 biases the insulating substrate 5 negatively with respect to the plasma, and the resistance element 17 has a direct current of 1! The negative bias voltage can be controlled by combining the resistance element 17 and the DC power source 8, which are connected in parallel with the power source 8.

本実施例によればマイクロ波により高密度プラズマを発
生し、高周波電力着こより基板5が絶縁材。
According to this embodiment, high-density plasma is generated by microwaves, and the substrate 5 is made of an insulating material by receiving high-frequency power.

非絶縁材にかかわりなく基板5に対して負のバイアスを
発生する。これに直流電力を高周波電力と共に試料台6
に印加し、抵抗要素17を直流電源8と並列に接続する
ことにより高周波電力の印加値を一定としたまま、直流
電力の印加値を制御することにより負のバイアス電圧を
制御することが可能となる。
A negative bias is generated for the substrate 5 regardless of the non-insulating material. DC power is applied to this along with high frequency power to the sample stage 6.
By connecting the resistance element 17 in parallel with the DC power source 8, it is possible to control the negative bias voltage by controlling the applied value of DC power while keeping the applied value of high-frequency power constant. Become.

基板5(例えばM膜)なエツチングする場合には基板5
に作用する負のバイアス電圧が高(なるように直流電源
8の印加値を設定する。負のバイアス電圧を高くするこ
とによりガスイオンに基板51こ対するイオンエネルギ
の増大と方向性を与えることができ、エツチングの高速
化と精密性を増大することができる。
When etching the substrate 5 (for example, M film), the substrate 5
The applied value of the DC power supply 8 is set so that the negative bias voltage acting on the substrate 51 is high. By increasing the negative bias voltage, it is possible to give gas ions an increase in ion energy and directionality toward the substrate 51. It is possible to increase the speed and precision of etching.

その後、エツチング終点検出後の適切な時点で直流電力
の印加値を抑制して、エツチングの精密性を損わない程
度(素子の電気特性に影響を与えない程度の形状)に負
のバイアス電圧を低くすることによりM膜の下地(例え
ば5tO−z膜、Si等)に対するイオンのエネルギを
低下することができ、イオンエネルギに起因する素子ダ
メージを低減できる0 以上本実施例によればエツチングを高速精密、かつ低ダ
メージに行える効果がある。
Then, at an appropriate point after the etching end point is detected, the applied DC power is suppressed, and a negative bias voltage is applied to an extent that does not impair etching precision (a shape that does not affect the electrical characteristics of the element). By lowering the etching temperature, it is possible to lower the ion energy to the base of the M film (for example, 5tO-z film, Si, etc.) and reduce element damage caused by the ion energy. It has the effect of being precise and causing low damage.

第2図は、本発明の他の実施例を説明するもので、本発
明の一実施例を示す第1図1こ示した抵抗要素17の抵
抗値を連続して可変可能な抵抗要素17′とする構成と
したものである。なお、第2図で、その他第1図と同一
のものは同一符号で示し説明を省略する。
FIG. 2 is for explaining another embodiment of the present invention. FIG. The configuration is as follows. Note that in FIG. 2, other parts that are the same as those in FIG.

本実施例では、上記一実施例での効果の地番こ抵抗要素
17′の抵抗値を処理条件に応じて最適な値番こ調節で
きるので固定抵抗の場合と比較して種々の処理条件に適
する抵抗値(種々の処理条件尋こ応じた安定なプラズマ
が得られる抵抗値)の選定が容易となり、また、適合す
る抵抗要素への交換の必要もなくなるという利点がある
In this embodiment, the resistance value of the resistor element 17' can be adjusted to the optimum value according to the processing conditions, so that it is suitable for various processing conditions compared to the case of using a fixed resistor. This method has the advantage that it becomes easy to select the resistance value (resistance value that allows stable plasma to be obtained under various processing conditions), and there is no need to replace the resistance element with a suitable one.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、試料に作用するバイアス電圧を制御で
きるので、試料を高速精密、かつ低ダメージにエツチン
グできるという効果がある。
According to the present invention, since the bias voltage applied to the sample can be controlled, the sample can be etched at high speed and with precision and with little damage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は1本発明の一実施例のドライエブチング処浬装
置の真空室部の縦断面図、第2図は、本発明の他の実施
例のドライエツチング処理装置の真空室部の縦断面図で
ある。 l・・・・・・真空室、2・・・・・・マグネトロン、
3・・曲磁湯コイル、4・曲・プラズマ、5・・・・・
・基板、6 ・曲・試料台、7・・曲高周波電源、8・
・曲直流電源、11・・・・・・ローパスフィルタ、し
・・開放重用ガス、13・・・排気口、14・・・・・
・導波管、15・・・・・・放電管、16・・曲絶41
FIG. 1 is a longitudinal cross-sectional view of a vacuum chamber of a dry etching processing apparatus according to an embodiment of the present invention, and FIG. 2 is a longitudinal cross-sectional view of a vacuum chamber of a dry etching processing apparatus according to another embodiment of the present invention. It is a front view. 1...Vacuum chamber, 2...Magnetron,
3. Curved hot water coil, 4. Curved plasma, 5...
・Substrate, 6 ・Block/sample stage, 7...Block high frequency power supply, 8...
・DC power supply, 11...Low pass filter, Open heavy gas, 13...Exhaust port, 14...
・Waveguide, 15... Discharge tube, 16... Curved 41
figure

Claims (1)

【特許請求の範囲】 1、真空室内に導入した放電用ガスにマイクロ波と磁界
とを作用させプラズマを発生する工程と、該プラズマ中
の活性粒子で試料の被処理面をエッチング処理する工程
と、前記試料の被処理面のエッチング処理工程中に試料
が設置された試料台に高周波電力と直流電力とを印加す
る工程とを有することを特徴とするドライエッチング処
理方法。 2、前記試料台に高周波電力と直流電力とを印加する工
程が、前記試料台に高周波電力と直流電力とを同時に印
加する工程と、前記試料台に高周波電力のみを印加する
工程とを含む特許請求の範囲第1項記載のドライエッチ
ング処理方法。 3、前記試料台に印加する高周波電力の印加値を一定と
して直流電力の印加値を制御し、前記試料に作用するバ
イアス電圧を制御する特許請求の範囲第1項記載のドラ
イエッチング処理方法。 4、前記試料のエッチング終点検出後に、前記試料台に
印加される直流電力の印加値を制御し、前記試料に作用
するバイアス電圧を制御する特許請求の範囲第1項記載
のドライエッチング処理方法。 5、真空室と、該真空室内を減圧排気する手段と、前記
真空室内に放電用ガスを導入する手段と、マイクロ波を
発生させる手段と、磁界とを発生させる手段と、前記マ
イクロ波と前記磁界との作用により発生するプラズマ中
の活性粒子でエッチング処理される試料が設置される試
料台と、該試料台に電気的に接続された高周波電源と、
該高周波電源と独立に制御可能に前記試料台に電気的に
接続された直流電源と、前記試料台に電気的に接続され
た抵抗要素とを具備したことを特徴とするドライエッチ
ング処理装置。
[Claims] 1. A step of generating plasma by applying microwaves and a magnetic field to a discharge gas introduced into a vacuum chamber, and a step of etching the surface of the sample to be processed with active particles in the plasma. A dry etching processing method, comprising: applying high frequency power and DC power to a sample stage on which the sample is placed during the etching process of the surface to be processed of the sample. 2. A patent in which the step of applying high frequency power and DC power to the sample stage includes a step of simultaneously applying high frequency power and DC power to the sample stage, and a step of applying only high frequency power to the sample stage. A dry etching treatment method according to claim 1. 3. The dry etching processing method according to claim 1, wherein the applied value of the high-frequency power applied to the sample stage is kept constant, the applied value of the DC power is controlled, and the bias voltage applied to the sample is controlled. 4. The dry etching processing method according to claim 1, wherein after the etching end point of the sample is detected, the applied value of the DC power applied to the sample stage is controlled, and the bias voltage applied to the sample is controlled. 5. a vacuum chamber, a means for depressurizing and evacuating the vacuum chamber, a means for introducing discharge gas into the vacuum chamber, a means for generating microwaves, a means for generating a magnetic field, and the microwave and the a sample stage on which a sample to be etched with active particles in plasma generated by interaction with a magnetic field is placed; a high-frequency power source electrically connected to the sample stage;
A dry etching processing apparatus comprising: a DC power supply electrically connected to the sample stage so as to be controllable independently of the high frequency power supply; and a resistance element electrically connected to the sample stage.
JP16364586A 1986-07-14 1986-07-14 Method and apparatus for dry etching Granted JPS6319822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16364586A JPS6319822A (en) 1986-07-14 1986-07-14 Method and apparatus for dry etching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16364586A JPS6319822A (en) 1986-07-14 1986-07-14 Method and apparatus for dry etching

Publications (2)

Publication Number Publication Date
JPS6319822A true JPS6319822A (en) 1988-01-27
JPH0511413B2 JPH0511413B2 (en) 1993-02-15

Family

ID=15777883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16364586A Granted JPS6319822A (en) 1986-07-14 1986-07-14 Method and apparatus for dry etching

Country Status (1)

Country Link
JP (1) JPS6319822A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127770A (en) * 1976-04-19 1977-10-26 Fujitsu Ltd Spatter etching method
JPS57164986A (en) * 1982-02-26 1982-10-09 Hitachi Ltd Microwave plasma etching device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127770A (en) * 1976-04-19 1977-10-26 Fujitsu Ltd Spatter etching method
JPS57164986A (en) * 1982-02-26 1982-10-09 Hitachi Ltd Microwave plasma etching device

Also Published As

Publication number Publication date
JPH0511413B2 (en) 1993-02-15

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