JPS63197378A - Nonvolatile semiconductor storage device and its manufacture - Google Patents
Nonvolatile semiconductor storage device and its manufactureInfo
- Publication number
- JPS63197378A JPS63197378A JP62028023A JP2802387A JPS63197378A JP S63197378 A JPS63197378 A JP S63197378A JP 62028023 A JP62028023 A JP 62028023A JP 2802387 A JP2802387 A JP 2802387A JP S63197378 A JPS63197378 A JP S63197378A
- Authority
- JP
- Japan
- Prior art keywords
- memory device
- semiconductor memory
- conductivity type
- nonvolatile semiconductor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 239000010408 film Substances 0.000 claims 8
- 239000010409 thin film Substances 0.000 claims 8
- 238000002955 isolation Methods 0.000 claims 3
- 230000005641 tunneling Effects 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は浮遊ゲートを有する不揮発性半導体記憶装置に
係り、特に電気的に書換え可能なメモリ装置及びその製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device having a floating gate, and more particularly to an electrically rewritable memory device and a method for manufacturing the same.
（従来の技術）
電気的に書換え可能な不揮発性半導体記憶装置（Ｅａｐ
ｕＯＭ）は、従来，第１０図に示すようにＰ型半導体基
板ω上にゲート酸化膜■、浮遊ゲート■を設け、その上
に絶縁膜（ニ）を介して制御ゲート■を積層した２層ゲ
ート構造のメモリトランジスタと、そのドレイン■に接
続された選択トランジスタからなるセルが知られている
，第１０図において、（ａ）は１セルの平面図． （ｂ
）（ｃ）は夫々Ａ−Ａ’。(Prior art) Electrically rewritable non-volatile semiconductor memory device (EAP)
Conventionally, uOM) is a two-layer structure in which a gate oxide film (■) and a floating gate (■) are provided on a P-type semiconductor substrate (ω), and a control gate (■) is laminated thereon via an insulating film (d), as shown in Figure 10. A cell consisting of a memory transistor with a gate structure and a selection transistor connected to its drain is known. In FIG. 10, (a) is a plan view of one cell. (b
) and (c) are respectively AA'.
Ｂ−Ｂ’断面図を示す。A sectional view taken along line B-B' is shown.
このセルに書込みを行なう場合は，例えば制御ゲート■
、選択ゲート■にパルス電圧２ＱＶを、また選択トラン
ジスタのドレイン（４）及びメモリトランジスタのソー
ス０を接地し、浮遊ゲート■とｎ◆層（１０）間の一部
に設けられた例えば膜厚９０人の薄い酸化ＩＩＩ（１１
）を介して電子をｎ中層（１０）から浮遊ゲート■に注
入して行なう。When writing to this cell, for example, the control gate ■
, a pulse voltage of 2QV is applied to the selection gate ■, and the drain (4) of the selection transistor and the source 0 of the memory transistor are grounded, and a film with a thickness of, for example, 90 mm is provided between the floating gate ■ and the n◆ layer (10). Human thin oxide III (11
), electrons are injected from the n-middle layer (10) into the floating gate (2).
消去を行なう場合は選択ゲート■、選択トランジスタの
ドレイン■を夫々２０ｖ，制御ゲート■を接地、メモリ
トランジスタのソース■を５ｖにして浮遊ゲート■から
ｎ”Ｍ （１０）へ電子を放出する。When erasing, the selection gate (2) and the drain (2) of the selection transistor are each set at 20V, the control gate (2) is grounded, and the source (2) of the memory transistor is set at 5V, and electrons are emitted from the floating gate (2) to n''M (10).
読出し時は例えば選択トランジスタのドレイン■を２ｖ
、選択ゲート■を５ｖ、制御ゲート■、メモリトランジ
スタのソース■を接地することにより行なう．以上の書
込み，消去読出し動作において基板は接地電位とされて
いる．尚，選択トランジスタの２層構造のゲートは同一
パターンとされ，スルーホールを介して所定箇所で相互
にコンタクトしている。When reading, for example, the drain of the selection transistor is set to 2V.
, the selection gate (2) is grounded to 5V, the control gate (2), and the source (2) of the memory transistor are grounded. In the write, erase and read operations described above, the substrate is at ground potential. Note that the gates of the two-layer structure of the selection transistors have the same pattern and are in contact with each other at predetermined locations via through holes.
書込まれたセルは浮遊ゲート■に電子が注入されている
ため、上記の読出し条件ではｎチャネル電界効果トラン
ジスタはカットオフの状態で，ドレイン電流は流れない
．逆に消去されたセルではメモリトランジタのチャネル
領域に反転層が形成されドレイン電流が流れる．ドレイ
ン電流が流れたセルを“０”、流れないセルを“′１′
″と判定し，データの読み出しが可能となる。Since electrons are injected into the floating gate of the written cell, under the above read conditions, the n-channel field effect transistor is in a cutoff state and no drain current flows. Conversely, in erased cells, an inversion layer is formed in the channel region of the memory transistor, and a drain current flows. Cells in which drain current flows are marked as “0”, and cells in which drain current does not flow are marked as “’1”.
”, and the data can be read.
このようなＥＢＦＲＯＭセルで書込み量を大きくするた
めには，薄い酸化膜（１１）に印加される電界を大きく
しなければならない．薄い酸化膜（１１）に加わる電界
は制御ゲート■と浮遊ゲート■との間の結合容量と、浮
遊ゲート■とｎ中層（１０）との間の結合容量との比で
決定される．この比が大きい程，薄い酸化膜（１ｌ）に
加わる電界は大きくなりトンネル電流は増加する。In order to increase the write amount in such an EBFROM cell, it is necessary to increase the electric field applied to the thin oxide film (11). The electric field applied to the thin oxide film (11) is determined by the ratio of the coupling capacitance between the control gate (2) and the floating gate (2) and the coupling capacitance between the floating gate (2) and the n-layer (10). As this ratio becomes larger, the electric field applied to the thin oxide film (1l) becomes larger and the tunnel current increases.
（発明が解決しようとする問題点）
上記セルでは薄い酸化膜（１１）の左右にゲート酸化膜
■領域を見込む構造であり、メモリトランジスタのドレ
イン領域に接続するｎ中層型（１０）の幅が大きい。こ
れによりｎ中層（１０）と浮遊ゲート０間の結合容量が
大き（、Ｊｊ＃、ＩＪＱ”のしきい値差が余り取れない
ため誤読出しが生じ易いという問題があった。一方、薄
い酸化膜（１１）の面積を小さくする事も考えられるが
、マスク材のパターニング精度が悪化してしまう、また
、制御ゲート０と浮遊ゲート０間の結合容量を大きくす
るにも集積度上限界がある。(Problems to be Solved by the Invention) The above cell has a structure in which gate oxide film regions are expected on the left and right sides of the thin oxide film (11), and the width of the n middle layer type (10) connected to the drain region of the memory transistor is big. As a result, the coupling capacitance between the n-middle layer (10) and the floating gate 0 is large (Jj Although it is possible to reduce the area of (11), the patterning accuracy of the mask material deteriorates, and there is also a limit to the degree of integration in increasing the coupling capacitance between the control gate 0 and the floating gate 0.
本発明は上記事情に鑑みてなされたものであり、セル面
積を大きくすることなく、書込み、消去時のセルのしき
い値差を増大できる不揮発性半導体記憶装置及びその製
造方法を提供する事を目的とする。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a nonvolatile semiconductor memory device and a method for manufacturing the same that can increase the threshold difference between cells during writing and erasing without increasing the cell area. purpose.
（問題点を解決するための手段）
本発明は、薄い酸化膜領域の少なくとも一辺をフィール
ド酸化膜で画定するようにしたものである。(Means for Solving the Problems) According to the present invention, at least one side of a thin oxide film region is defined by a field oxide film.
（作 用）
薄い酸化膜とフィールド酸化膜を接して設けることによ
り薄い酸化膜化膜下のｎ十領域が形成されている素子領
域の幅を従来より狭めることが出来、制御ゲートと浮遊
ゲート間の容量よりも浮遊ゲートとｎ中層間の容量を十
分小さくすることができるので結合容量比が大きく取れ
、書込み時と消去時のしきい値差を大幅に拡げる事が出
来る（実施例）
次に１１本発明の一実施例を第１図、第２図及び第３図
を参照して説明する。第１８（ａ）は１つのセルの平面
図、 （ｂ）（ｃ）はＡ−Ａ’ 、Ｂ−Ｂ’断面図であ
る。第２図、第３図はその製造工程を示し、第２図（ａ
）〜（ｅ）はＡ−Ａ’断面、第３図（ａ）〜（ｅ）はそ
れに対応するＢ−Ｂ’断面を示している。(Function) By providing the thin oxide film and the field oxide film in contact with each other, the width of the device region where the n0 region under the thin oxide film is formed can be narrower than before, and the width between the control gate and the floating gate can be reduced. Since the capacitance between the floating gate and the n-layer can be made sufficiently smaller than the capacitance of , a large coupling capacitance ratio can be obtained, and the threshold difference between writing and erasing can be greatly expanded (Example) Next 11 An embodiment of the present invention will be described with reference to FIGS. 1, 2, and 3. The 18th (a) is a plan view of one cell, and (b) and (c) are AA' and BB' cross-sectional views. Figures 2 and 3 show the manufacturing process, and Figure 2 (a
) to (e) show the AA' cross sections, and FIGS. 3(a) to (e) show the corresponding BB' cross sections.
製造工程を説明すると、先ず最初に第２図（ａ）（第３
図ａ ）に示す如く６Ω・１のＰ−型シリコン基板（
２１）表面の素子領域にシリコン酸化膜（２２）を形成
し、この上にシリコン窒化膜（２３）パターンを形成し
、これをマスクに素子間領域にボロン（Ｂ）イオン注入
し、熱酸化により０，８ｐ厚のフィールド酸化膜（２４
）を形成する。フィールド酸化膜下には反転防止のＰ型
層（２５）が形成される。To explain the manufacturing process, first of all, the manufacturing process shown in FIG.
As shown in Figure a), a 6Ω・1 P-type silicon substrate (
21) Form a silicon oxide film (22) in the element region on the surface, form a silicon nitride film (23) pattern on this, use this as a mask to implant boron (B) ions into the inter-element region, and perform thermal oxidation. 0.8p thick field oxide film (24
) to form. A P-type layer (25) for preventing inversion is formed under the field oxide film.
次いで、シリコン窒化膜（２３）、シリコン酸化膜（２
２）を除去し、基板表面を熱酸化して１００人厚０酸化
膜を形成し、フォトレジスト（破線）をマスクにして基
板にヒ素（Ａｓ）を４０ＫｅＶで例えば２ Ｘ １０”
ロー２イオン注入して前記１００人厚０酸化膜下にｎ＋
層（２７）とメモリトランジスタのチャネル長を決める
ためのｎ＋層（２８）を形成する。このｎ中層（２７）
（２８）はイオン注入マスクでＹ方向（第１図ａ参照
）の辺が、またフィールド酸化膜（２４）によりＸ方向
の辺が決まる。この後、前記１００人厚０酸化膜をフッ
化アンモニウム又はＲＩＥ （反応性イオンエツチング
）で除去し、再度９００℃で熱酸化して４００人厚０ゲ
ート酸化膜（２６）を形成する（第２図す、第３図ｂ）
。Next, a silicon nitride film (23) and a silicon oxide film (23) are formed.
2) is removed, the surface of the substrate is thermally oxidized to form an oxide film with a thickness of 100 mm, and using the photoresist (broken line) as a mask, arsenic (As) is applied to the substrate at 40 KeV, for example, 2 x 10".
Low 2 ions are implanted under the 100-layer 0 oxide film.
A layer (27) and an n+ layer (28) for determining the channel length of the memory transistor are formed. This n middle layer (27)
The side in the Y direction (see FIG. 1a) is determined by the ion implantation mask (28), and the side in the X direction is determined by the field oxide film (24). Thereafter, the 100-layer-thickness 0-oxide film is removed by ammonium fluoride or RIE (reactive ion etching), and thermally oxidized again at 900°C to form a 400-layer-thickness 0-gate oxide film (26). Figure 3b)
.
この後、トンネル酸化膜を形成する領域にフォトレジス
トマスク（２９）を形成し、基板表面のシリコン酸化膜
（２６）をフッ化アンモニウム又はＲＩＥで除去する。Thereafter, a photoresist mask (29) is formed in the region where the tunnel oxide film is to be formed, and the silicon oxide film (26) on the surface of the substrate is removed by ammonium fluoride or RIE.
この時、開口部のフィールド酸化膜（２４）も若干エツ
チングされる。フォトレジストマスク（２９）は矩形の
開口を有し、Ｘ方向はフィールド酸化膜（２４）上に延
在する（第２図Ｃ２第３図Ｃ）。At this time, the field oxide film (24) in the opening is also slightly etched. The photoresist mask (29) has a rectangular opening and extends over the field oxide film (24) in the X direction (FIG. 2C2, FIG. 3C).
次いで、フォトレジストマスク（２９）を除去し。The photoresist mask (29) is then removed.
８００℃で熱酸化して厚さ１００人のトンネル酸化膜（
３０）を形成し、更にリンをドープしたポリシコン層を
形成し、これをバターニングしてフローティングゲート
となる部分についてＸ方向のセル間の部分を除去する（
第２図Ｃ２第３図ｄ）。A tunnel oxide film with a thickness of 100 mm was formed by thermal oxidation at 800°C (
30), further form a phosphorus-doped polysilicon layer, and pattern this to remove the portion between the cells in the X direction for the portion that will become the floating gate (
Figure 2 C2 Figure 3 d).
そしてポリシリコン層表面を１０００℃で熱酸化して５
００人厚０シリコン酸化膜（３１）を形成し、更に第２
層目のリンをドープしたポリシリコン層を形成する。そ
してフォトレジストマスクを用い、この２層ポリシリコ
ン膜を順次パターンニングして各ゲート電極を形成する
１図中、（３２） （３３）は選択トランジスタの選択
ゲート、（３４）はメモリトランジスタの浮遊ゲート、
（３５）はメモリトランジスタの制御ゲートである。Then, the surface of the polysilicon layer was thermally oxidized at 1000°C.
A silicon oxide film (31) with a thickness of 0 is formed, and then a second
A second phosphorus-doped polysilicon layer is formed. Then, using a photoresist mask, this two-layer polysilicon film is sequentially patterned to form each gate electrode. Gate,
(35) is a control gate of the memory transistor.
この後、基板に、セルを高耐圧構造にするため低濃度の
ｎ一層（３６） （３７）をリンＣＰ）イオン注入によ
り全面に形成し、更に選択トランジスタのドレイン部に
形成された上記ｎ一層の一部表面から制御ゲート（３５
）上にかけてフォトレジストマスク（破線）を形成し、
高濃度にヒ素（Ａｓ）をイオン注入して選択トランジス
タのドレインであるｎ中層（３８）とメモリトランジス
タのソースであるｎ＋層（３９）を形成する。尚、説明
は省略したが、選択ゲート（３２）（３３）は所定箇所
でスルーホールを介して相互にコンタクトしている（第
２図ｅ。Thereafter, a low concentration n layer (36) (37) was formed on the entire surface of the substrate by phosphorus CP) ion implantation in order to make the cell a high breakdown voltage structure. Control gate (35
) to form a photoresist mask (dashed line),
Arsenic (As) is ion-implanted at a high concentration to form an n middle layer (38) which is the drain of the selection transistor and an n+ layer (39) which is the source of the memory transistor. Although the explanation is omitted, the selection gates (32) and (33) are in contact with each other through through holes at predetermined locations (FIG. 2e).
第３図ｅ）。Figure 3 e).
かかる本実施例によれば、薄い酸化膜（３０）の２辺が
フィールド酸化膜（２４）によって画定される事となり
、結合容量比が改善され“１” ａｔＱ”のマージンが
大幅に増大する。尚、書込み、消去、読出し時の各部の
電位条件は第１０図の説明で述べたのと同じである。第
４図は、かかるセルの制御ゲート電圧に対するドレイン
電流の特性をＨＯｎ 、 ６１１ ＃の夫々の場合につ
いて示したものである。According to this embodiment, two sides of the thin oxide film (30) are defined by the field oxide film (24), improving the coupling capacitance ratio and greatly increasing the margin of "1" atQ. Note that the potential conditions of each part during writing, erasing, and reading are the same as those described in the explanation of Fig. 10. Fig. 4 shows the characteristics of the drain current with respect to the control gate voltage of such a cell as shown in HOn, 611#. This is shown for each case.
第５図は、書込み消去の繰り返し回数と書込み時、消去
時のメモリトランジスタのしきい値の関係を示したもの
である０図より判るように１回数の増加に伴ない、書込
みセルと消去セルのメモリトランジスタのしきい値差は
樽状の変化を示す。Figure 5 shows the relationship between the number of write/erase repetitions and the threshold values of memory transistors during writing and erasing. The threshold difference of the memory transistors shows a barrel-like change.
第６図は２万回におけるしきい値差と最大部のしきい値
差の差分Δｖｔｈ ｔ＆ｎ＋層（２７）のドーズ量に対
して示したものである。この図から、ドーズ量が５ Ｘ
１０” ａｍ−” より小さくなると急激にΔｖｔｈ
も大きくなる事が判る。勿論５ Ｘ １０” ｃｘａ−
” より低いドーズ量を用いても構わないが、Δｖｔｈ
が大きいと多数回書込み消去を繰り返した時のマージン
の低下も大きくなるのでｎ中層（２７）の不純物のドー
ズ量は５ Ｘ １０” ｒｘ−２以上、好ましくは２Ｘ
ＩＯ１４ａｍ−２以上が良い、これはｎ中層（２７）の
トンネル酸化膜下の逆導電型不純物の表面濃度に換算し
て夫々４．５Ｘ １０” ａｍ−’ 、 １．８Ｘ １
０” ａｍ−”である、上限はメモリトランジスタのパ
ンチスルーによるドレイン耐圧の劣化を防止するため５
Ｘ１０”Ｃ３Ｉ−”（４，５Ｘ１０”ｃｓ＋−”）とす
るのが好ましい。FIG. 6 shows the difference Δvth between the threshold difference at 20,000 times and the maximum threshold difference with respect to the dose of the t&n+ layer (27). From this figure, it can be seen that the dose is 5
When it becomes smaller than 10” am-”, Δvth suddenly decreases.
It turns out that it also gets bigger. Of course 5 x 10” cxa-
” A lower dose may be used, but Δvth
If the value is large, the margin will decrease greatly when writing and erasing is repeated many times, so the dose of impurities in the n-middle layer (27) should be 5 x 10" rx-2 or more, preferably 2x.
IO of 14 am-2 or more is better, which is converted to the surface concentration of the opposite conductivity type impurity under the tunnel oxide film of the n-middle layer (27), which is 4.5X 10"am-' and 1.8X 1, respectively.
0"am-", and the upper limit is 5 to prevent deterioration of the drain breakdown voltage due to punch-through of the memory transistor.
Preferably, it is X10"C3I-"(4,5X10"cs+-").
ｎ中層（２７）の濃度が高いとしきい値の変動が少なく
なる理由は消去時のトンネル酸化膜中への正孔トラップ
が押えられることが一因であると考えられる。第７図は
トンネル部の拡大図で、破線で示した領域は空乏層を示
している。空乏層内では電子正孔対が生成するが、ｎ中
層（２７）の表面の空乏層厚はｎ＋層（２７）が高濃度
である程薄い、従って空乏層中の電界が低く空乏層中の
正孔がこの電界により加速されてトンネル酸化膜（２７
）中にトラップされるのを押える事が可能となる。また
、高濃度にするとｎ中層（２７）の横方向への回わり込
みも大きくなり、フィールド酸化膜下への侵入が大きい
、こる、この部分での空乏層厚は薄く、従って空乏層内
の正孔が基板に逃げるのを抑制する。正孔が基板に逃げ
ると全体の空乏層厚が増大するので好ましくない。従っ
て高濃度にすることによりｎ＋層（２７）がフィールド
酸化膜下に延びるようにする事が望ましい。One reason why the fluctuation of the threshold value is reduced when the concentration of the n-middle layer (27) is high is thought to be that trapping of holes into the tunnel oxide film during erasing is suppressed. FIG. 7 is an enlarged view of the tunnel section, and the region indicated by the broken line indicates the depletion layer. Electron-hole pairs are generated in the depletion layer, but the thickness of the depletion layer on the surface of the n-middle layer (27) is thinner as the concentration of the n+ layer (27) is higher, so the electric field in the depletion layer is lower. Holes are accelerated by this electric field and form a tunnel oxide film (27
) It becomes possible to prevent being trapped inside. In addition, when the concentration is high, the lateral wrapping of the n-middle layer (27) becomes large, and the penetration into the field oxide film becomes large.The depletion layer thickness in this part is thin, and therefore Prevents holes from escaping to the substrate. If holes escape to the substrate, the overall thickness of the depletion layer increases, which is undesirable. Therefore, it is desirable to have a high concentration so that the n+ layer (27) extends below the field oxide film.
第８図、第９図は本発明の他の実施例の製造工程を示し
、夫々第２図、第３図に対応している。FIGS. 8 and 9 show manufacturing steps of other embodiments of the present invention, and correspond to FIGS. 2 and 3, respectively.
本実施例では第８図（ｂ）（第９図ｂ）の工程でのｎ÷
層（２７）形成のためのヒ素（Ａｓ）イオン注入のドー
ズ量を３Ｘ１０”Ｃ３Ｉ−” とした。また、フォトレ
ジストマスク（２９）を用いて基板表面のシリコン酸化
膜（２６）を除去した後、リン（Ｐ）を４０ＫａＶ、２
Ｘ１０１４ａｍ’″８にてイオン注入するようにした（
第８図Ｃ９第９図Ｃ）、、他は先の実施例と同じである
。In this example, n÷ in the process of FIG. 8(b) (FIG. 9b)
The dose of arsenic (As) ion implantation for forming the layer (27) was set to 3×10"C3I-". In addition, after removing the silicon oxide film (26) on the substrate surface using a photoresist mask (29), phosphorus (P) was applied at 40KaV and 2
Ion implantation was performed at X1014am'''8 (
FIG. 8C9 FIG. 9C), the rest is the same as the previous embodiment.
この実施例においてもトンネル部のｎ中層（２７）のこ
の例では第８図（ｃ）で、フィールド酸化膜退行部へリ
ンを重ねてイオン注入しているため、製造後のｎ中層（
２７）端での絶縁膜厚ｄは５００Å以上となる。また、
トンネル部以外のｎ中層（２７） （２８）の濃度を押
えることが出来るのでその部分の横方向拡散が少なくチ
ャネル長しの制御性、ドレイン耐圧が良い。尚、２回目
のイオン注入工程（第８図Ｃ）でリンをイオン注入した
が、これはヒ素（Ａｓ）でも良い。In this example, as shown in FIG. 8(c) in the N-middle layer (27) of the tunnel section, ion implantation is carried out in a layered manner into the field oxide film regression part, so that the N-middle layer (27) after manufacture is
27) The insulating film thickness d at the end is 500 Å or more. Also,
Since the concentration of the n-middle layer (27) (28) other than the tunnel part can be suppressed, lateral diffusion in that part is small, and the controllability of the channel length and drain breakdown voltage are good. Although phosphorus ions were implanted in the second ion implantation step (FIG. 8C), arsenic (As) may also be used.
以上の実施例においては薄い酸化膜領域はその２辺がフ
ィールド絶縁膜により画定される構造としたが、薄い酸
化膜領域をＸ方向にずらし、−辺のみがフィールド絶縁
膜により画定されるようにしても良い。In the above embodiment, the thin oxide film region has a structure in which two sides are defined by the field insulating film, but the thin oxide film region is shifted in the X direction so that only the − side is defined by the field insulating film. It's okay.
本発明によれば薄い酸化膜領域の少なくとも一辺がフィ
ールド酸化膜端部に接する構造としたので浮遊ゲートと
薄い酸化膜下のｎ中層の結合容量を小さくすることがで
き、書込み量が大きく誤読出しの少ないセルが得られる
。According to the present invention, since at least one side of the thin oxide film region is in contact with the edge of the field oxide film, the coupling capacitance between the floating gate and the n-middle layer under the thin oxide film can be reduced, resulting in a large amount of writing and erroneous reading. This results in cells with fewer cells.
第１図は本発明の詳細な説明するための図、第２図及び
第３図はその製造工程断面図、第４図はセルの特性図、
第５図は書込み消去の繰返し回数に対するしきい値の特
性図、第６図はそのｎ中層ドーズ量依存性を示す図、第
７図はトンネル部の拡大図、第８図及び第９図は他の実
施例を説明する図、第１０図は従来例の図である。
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
第 １ 図
第２図 第３図
第４図
第７図
書込み消去品数（ω）
ｎ十 ド−ス゛量（ｃｍ−２）
第 ６ 図
（ｅ） （ｅ）第８
図 第９図FIG. 1 is a diagram for explaining the present invention in detail, FIGS. 2 and 3 are cross-sectional views of the manufacturing process, and FIG. 4 is a characteristic diagram of the cell.
Fig. 5 is a characteristic diagram of the threshold value with respect to the number of repetitions of write/erase, Fig. 6 is a diagram showing its dependence on the n-middle layer dose, Fig. 7 is an enlarged view of the tunnel section, and Figs. 8 and 9 are FIG. 10, which is a diagram for explaining another embodiment, is a diagram of a conventional example. Agent Patent Attorney Yudo Nori Chika Kikuo Takehana No. 1 Figure 2 Figure 3 Figure 4 Figure 7 Number of written and erased items (ω) n0 Dose amount (cm-2) Figure 6 (e) (e) Eighth
Figure 9
Claims (13)
おいて、浮遊ゲートとの間でトンネル電流を流す絶縁薄
膜が、チャネル部に設けられた基板とは逆導電型の領域
上に形成され、この逆導電型領域は、メモリトランジス
タのドレイン領域に接続されると共に、前記絶縁薄膜の
少なくとも一辺が素子分離用の絶縁膜によって画定され
ている事を特徴とする不揮発性半導体記憶装置。(1) In an electrically rewritable nonvolatile semiconductor memory device, an insulating thin film that allows a tunnel current to flow between it and the floating gate is formed on a region of the opposite conductivity type to that of the substrate provided in the channel part. A nonvolatile semiconductor memory device, wherein the opposite conductivity type region is connected to a drain region of a memory transistor, and at least one side of the insulating thin film is defined by an insulating film for element isolation.
記メモリトランジスタのドレイン領域に接続されている
事を特徴とする前記特許請求の範囲第１項記載の不揮発
性半導体記憶装置。(2) The nonvolatile semiconductor memory device according to claim 1, wherein a source region of a selection transistor for cell selection is connected to a drain region of the memory transistor.
ｃｍ＾−＾２以上である事を特徴とする前記特許請求の
範囲第１項記載の不揮発性半導体記憶装置。(3) The dose amount of the opposite conductivity type region is 5×10^1^3
2. The nonvolatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device has a width of cm^-^2 or more.
ｃｍ＾−＾２以上である事を特徴とする前記特許請求の
範囲第１項記載の不揮発性半導体記憶装置。(4) The dose amount of the opposite conductivity type region is 2×10^1^4
2. The nonvolatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device has a width of cm^-^2 or more.
５×１０＾１＾■ｃｍ＾−＾３以上である事を特徴とす
る前記特許請求の範囲第１項記載の不揮発性半導体記憶
装置。(5) The surface concentration of the opposite conductivity type region under the insulating thin film is 4.
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is 5×10^1^■cm^-^3 or more.
８×１０＾１＾■ｃｍ＾−＾３以上である事を特徴とす
る前記特許請求の範囲第１項記載の不揮発性半導体記憶
装置。(6) The surface concentration of the opposite conductivity type region under the insulating thin film is 1.
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is 8×10^1^■ cm^-^3 or more.
＾９ｃｍ＾−＾３以下である事を特徴とする前記特許請
求の範囲第５項記載の不揮発性半導記憶装置。(7) The surface concentration of the opposite conductivity type region is 4.5×10^1
The non-volatile semiconductor memory device according to claim 5, characterized in that it is ^9 cm^-^3 or less.
おいて、前記逆導電型領域の端部は前記浮遊ゲートが伸
びている前記素子分離用の絶縁膜下に延在している事を
特徴とする前記特許請求の範囲第１項記載の不揮発性半
導体記憶装置。(8) In a portion adjacent to the insulating thin film and the element isolation insulating film, an end of the opposite conductivity type region extends below the element isolating insulating film to which the floating gate extends. A nonvolatile semiconductor memory device according to claim 1, characterized in that:
厚が３００Å以上である事を特徴とする前記特許請求の
範囲第８項記載の不揮発性半導体記憶装置。(9) The nonvolatile semiconductor memory device according to claim 8, wherein in the adjacent portion, the insulating film thickness at the end of the opposite conductivity type region is 300 Å or more.
純物が添加され、前記絶縁薄膜部下には更に基板と逆導
電型の不純物が重畳する如く添加されてなる事を特徴と
する前記特許請求の範囲第１項記載の不揮発性半導体記
憶装置。(10) The entire region of the opposite conductivity type is doped with an impurity of a conductivity type opposite to that of the substrate, and an impurity of a conductivity type opposite to that of the substrate is further doped under the insulating thin film so as to overlap. A nonvolatile semiconductor memory device according to claim 1.
る如く添加された不純物がリンである事を特徴とする前
記特許請求の範囲第１０項記載の不揮発性半導体記憶装
置。(11) The nonvolatile semiconductor memory device according to claim 10, wherein the impurity added throughout is arsenic, and the impurity added so as to overlap is phosphorus.
膜が、チャネル部に設けられた基板とは逆導電型の領域
上に形成され、この逆導電型領域がメモリトランジスタ
のドレイン領域に接続された電気的に書換え可能な不揮
発性半導体記憶装置の製造方法において、ゲート絶縁膜
を形成後、少なくとも一辺が素子分離用の絶縁膜上に及
ぶ開口を有するマスク材を形成してゲート絶縁膜を除去
し、この除去部に前記トンネル電流を流す絶縁薄膜を形
成する事を特徴とする不揮発性半導体記憶装置の製造方
法。(12) An insulating thin film that allows a tunnel current to flow between the floating gate and the floating gate is formed on a region of a conductivity type opposite to that of the substrate provided in the channel portion, and this region of the opposite conductivity type is connected to the drain region of the memory transistor. In a method for manufacturing an electrically rewritable nonvolatile semiconductor memory device, after forming a gate insulating film, a mask material having an opening extending over at least one side of the insulating film for element isolation is formed, and the gate insulating film is removed. and forming an insulating thin film through which the tunneling current flows in the removed portion.
前記マスク材を用いて前記逆導電型領域が形成された基
板に対して更に基板と逆導電型不純物を導入する事を特
徴とする前記特許請求の範囲第１項記載の不揮発性半導
体記憶装置の製造方法。(13) After removing the gate insulating film using a mask material,
2. The nonvolatile semiconductor memory device according to claim 1, wherein an impurity of a conductivity type opposite to that of the substrate is further introduced into the substrate on which the region of opposite conductivity type is formed using the mask material. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62028023A JP2760983B2 (en) | 1987-02-12 | 1987-02-12 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62028023A JP2760983B2 (en) | 1987-02-12 | 1987-02-12 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63197378A true JPS63197378A (en) | 1988-08-16 |
| JP2760983B2 JP2760983B2 (en) | 1998-06-04 |
Family
ID=12237150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62028023A Expired - Lifetime JP2760983B2 (en) | 1987-02-12 | 1987-02-12 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2760983B2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53120285A (en) * | 1977-03-29 | 1978-10-20 | Fujitsu Ltd | Manufacture of semiconductor |
| JPS60124965A (en) * | 1983-12-10 | 1985-07-04 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS60244073A (en) * | 1984-05-17 | 1985-12-03 | Toshiba Corp | Manufacture of nonvolatile semiconductor memory device |
| JPS60502128A (en) * | 1983-08-29 | 1985-12-05 | シ−ク・テクノロジイ・インコ−ポレイテツド | Method for manufacturing non-volatile MOS memory device |
-
1987
- 1987-02-12 JP JP62028023A patent/JP2760983B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53120285A (en) * | 1977-03-29 | 1978-10-20 | Fujitsu Ltd | Manufacture of semiconductor |
| JPS60502128A (en) * | 1983-08-29 | 1985-12-05 | シ−ク・テクノロジイ・インコ−ポレイテツド | Method for manufacturing non-volatile MOS memory device |
| JPS60124965A (en) * | 1983-12-10 | 1985-07-04 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS60244073A (en) * | 1984-05-17 | 1985-12-03 | Toshiba Corp | Manufacture of nonvolatile semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2760983B2 (en) | 1998-06-04 |
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