JPS63197350A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS63197350A
JPS63197350A JP3092987A JP3092987A JPS63197350A JP S63197350 A JPS63197350 A JP S63197350A JP 3092987 A JP3092987 A JP 3092987A JP 3092987 A JP3092987 A JP 3092987A JP S63197350 A JPS63197350 A JP S63197350A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
conductive film
recess
bonding pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3092987A
Other languages
Japanese (ja)
Inventor
Yuuji Gondai
權代　裕治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP3092987A priority Critical patent/JPS63197350A/en
Publication of JPS63197350A publication Critical patent/JPS63197350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To shorten the run of power lines on a chip by a method wherein a power conducting film is formed to uninterruptedly surround a recess, which is to be mounted with a semiconductor circuit chip, for the placement at desired positions of power source bonding pads. CONSTITUTION:An integrated circuit chip 1 is fixed tight into a recess 6 at the middle of an insulating substrate 4, and a GND conductive film 7 is formed to surround uninterruptedly the integrated circuit chip 1 and, further, a VDD conductive film 8 is formed to surround the GND conductive film 7. The VDD conductive film 8 is surrounded with a plurality of stripes of signal conductive films 3. The signal conductive films 3 are electrically connected respectively to their corresponding bonding pads 2 on the integrated circuit chip 1 with the intermediary of bonding lines 5. The conductive films 7 and 8 are connected at several spots to their respective power bonding pads 9 through the intermediary of the bonding lines 5. This design improves the device in its electrical characteristics and enhances the integrated circuit chip integration, which results in a virtual decrease in the required number of pins.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マスク設計上電源用ポンディングパッドの配
置が自白で、電気的特性が良く、小型の半導体集積回路
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a small-sized semiconductor integrated circuit device that has good electrical characteristics and has good electrical characteristics in which the arrangement of power supply bonding pads is obvious due to the mask design.

〔従来の技術〕[Conventional technology]

従来この種の半導体集積回路装置は、第２図（ａ）（ｂ
）に示すように集積回路チップ１上に設けられた複数個
の電源用ポンディングパッド９に外部から電源を供給す
る為に、この電源用ポンディングパッド９と同じ数の導
電膜３′を絶縁基体４上に形成していた。Conventionally, this type of semiconductor integrated circuit device is shown in FIGS.
), in order to supply power from the outside to the plurality of power supply bonding pads 9 provided on the integrated circuit chip 1, the same number of conductive films 3' as the power supply bonding pads 9 are insulated. It was formed on the base 4.

〔発明が鳥決しようとする問題点〕[Problems that invention attempts to resolve]

上述した従来の半導体集積回路装置は、集積回路チック
上に設けられた複数個の′＃Ｊｔ源用ポンディングパッ
ドに外部から電源を供給する為に、この電源用ポンディ
ングパッドと同じ数の４電膜を絶縁基体上に形成しなけ
ればならず、半導体集積回路装置の電源ビンの数が増え
るという欠点があると同時に、集積回路チップ上の所望
の位置に電源用ポンディングパッドを配置することが出
来ない為に、集積回路チップ上で電源線を引き廻してい
た、この為電圧降下による電気的特性の忌化が起きると
いう欠点があるとともに、集積回路チップの集積度を上
げることが出来ないという欠点がある。In the conventional semiconductor integrated circuit device described above, in order to externally supply power to the plurality of '#Jt source bonding pads provided on the integrated circuit chip, four This method has the drawback that the electrical film must be formed on an insulating substrate, increasing the number of power supply pins in the semiconductor integrated circuit device, and at the same time, it is difficult to arrange the power supply bonding pad at a desired position on the integrated circuit chip. Because of this, power lines were routed around the integrated circuit chip, which had the disadvantage of degrading the electrical characteristics due to voltage drop, and making it impossible to increase the degree of integration of the integrated circuit chip. There is a drawback.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体集積回路装置は、絶縁基体の中央部に集
積回路チップを固着する為の凹みを有し、この凹みを連
続して囲むように電源用の導電膜を有し、さらにこの導
電膜の周囲を囲む複数個の信号耐用の導電膜を有してい
る。The semiconductor integrated circuit device of the present invention has a recess for fixing an integrated circuit chip in the center of an insulating substrate, a conductive film for a power supply continuously surrounding the recess, and a conductive film for power supply continuously surrounding the recess. It has a plurality of signal-resistant conductive films surrounding the periphery.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）は本発明の一実施例の平面図、同図（ｂ）
は図（ａ）のＡ−Ａ断面図である。FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
is a sectional view taken along line A-A in Figure (a).

第１図（ａ）（ｂ）において、集積回路チップ１は、絶
縁基体４の中央の凹み６に固着されておシ、この集積回
路チップ１の周囲を連続的に囲むようにＧＮＤ用導を膜
７が形成されておシ、さらに外側をＶＤＤ用導電導電膜
８み、その周囲を複数の信号用導！＠３が囲むように形
成されている。更に、各々の信号用導電膜３は半導体チ
ップ１上のポンディングパッド２とボンディング線５を
介して１対１に電気的に接続されておシ、ＧＮＤ用導電
膜７とＶＤＤ用導電導電膜８数の箇所から各々の電源用
ポンディングパッド９にボンディング線５を介して、電
気的に接続されている。In FIGS. 1(a) and 1(b), an integrated circuit chip 1 is fixed in a recess 6 at the center of an insulating substrate 4, and a GND conductor is connected so as to continuously surround the integrated circuit chip 1. A film 7 is formed on the outside, and a conductive film 8 for VDD is formed on the outside, and a plurality of signal conductors are formed around it! @3 is formed so as to surround it. Further, each signal conductive film 3 is electrically connected one-to-one to the bonding pad 2 on the semiconductor chip 1 via a bonding line 5, and the GND conductive film 7 and the VDD conductive film It is electrically connected to each of the power supply bonding pads 9 via bonding wires 5 from eight locations.

尚、上側では、ＶＤＤとＧＮＤの単一電源となっている
が二１Ｅ源、三寛源とすることも可能である。Although the upper side has a single power supply of VDD and GND, it is also possible to use a 21E power supply or a 3Kan power supply.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、絶縁基体の中央部に、集
積回路チップを固着する為の凹みを有し、この凹みを連
続して囲むように電源用の導電膜を構成することによシ
、チップ上に設けられた複数個の電源用ポンディングパ
ッドに、絶縁基体上の１組の電源用導１を膜から、電源
を供給できる為に、マスク設計上、電源用ポンディング
パッドを所望の位置に濾くことが出来、集積回路チップ
上での電源線の引き蜘しか短くなるので、電気的特性が
良くなる効果と集積回路チップの集積度を上げる効果と
、実質的に半導体集積回路装置のピンの数を減らすこと
が出来るので、実装面積を小さく出来る効果がある。As explained above, the present invention has a recess in the center of an insulating substrate for fixing an integrated circuit chip, and a conductive film for power supply is configured to continuously surround this recess. Since power can be supplied from the membrane to a set of power conductors 1 on the insulating substrate to multiple power supply bonding pads provided on the chip, the power supply bonding pads are desirable in terms of mask design. Since the power supply line on the integrated circuit chip is shortened, the electrical characteristics are improved and the degree of integration of the integrated circuit chip is increased. Since the number of pins of the device can be reduced, the mounting area can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は本発明の一実施例の平面図、同図（ｂ）
は同図（ａ）のＡ−Ａ断面図、 第２図（ａ）は従来の平面図、同図（ｂ）は同図（ａ）
のＡ−入断面図である。 １・・・・・・集積回路チップ、２・・・・・・信号用
ポンディングパッド、３・・・・・・信号用導［Ｍ、　
　３’・・・・・・電源用導Ｘ膜、４・・・・・・絶縁
基体、５・・・・・・ボンディング！！。 ６・・・・・・チップを固着する凹み、７・・・・・・
（）ＮＤ用導電膜、８・・・・・・ＶＤＤ用４蹴膜、９
・・・・・・１１７を源用ポンディングパッド。 代理人　弁理士　　内　原　　　晋、、′：、、“１、
ｙ：、−、、、、、゛−ニア：゛ 石１　目FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
Figure 2(a) is a conventional plan view, and Figure 2(b) is a cross-sectional view of Figure 2(a).
FIG. 1... Integrated circuit chip, 2... Signal bonding pad, 3... Signal conductor [M,
3'... X-conducting film for power supply, 4... Insulating base, 5... Bonding! ! . 6... Concavity for fixing the chip, 7...
() Conductive film for ND, 8...4 film for VDD, 9
...117 is the source pounding pad. Agent: Susumu Uchihara, patent attorney, ``1.''
y:,-,,,,, ゛-Nia: ゛Stone 1st

Claims (1)

【特許請求の範囲】[Claims] 絶縁基体の中央部に集積回路チップを固着する為の凹み
を有し、この凹みを連続して囲むように電源用の導電膜
を複数個有し、さらにこの導電膜の周囲を信号用の複数
個の導電膜が囲むように配列されている事を特徴とする
半導体集積回路装置。The insulating base has a recess in the center for fixing the integrated circuit chip, a plurality of conductive films for power supply continuously surrounding this recess, and a plurality of conductive films for signal use surrounding this conductive film. A semiconductor integrated circuit device characterized in that conductive films are arranged in a surrounding manner.
JP3092987A 1987-02-12 1987-02-12 Semiconductor integrated circuit device Pending JPS63197350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3092987A JPS63197350A (en) 1987-02-12 1987-02-12 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3092987A JPS63197350A (en) 1987-02-12 1987-02-12 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS63197350A true JPS63197350A (en) 1988-08-16

Family

ID=12317372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3092987A Pending JPS63197350A (en) 1987-02-12 1987-02-12 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS63197350A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020524A (en) * 1983-07-14 1985-02-01 Toshiba Corp Semiconductor integrated circuit device
JPS6231132A (en) * 1985-08-02 1987-02-10 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020524A (en) * 1983-07-14 1985-02-01 Toshiba Corp Semiconductor integrated circuit device
JPS6231132A (en) * 1985-08-02 1987-02-10 Nec Corp Semiconductor device

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