JPS63197334U - - Google Patents
Info
- Publication number
- JPS63197334U JPS63197334U JP8927087U JP8927087U JPS63197334U JP S63197334 U JPS63197334 U JP S63197334U JP 8927087 U JP8927087 U JP 8927087U JP 8927087 U JP8927087 U JP 8927087U JP S63197334 U JPS63197334 U JP S63197334U
- Authority
- JP
- Japan
- Prior art keywords
- electronic device
- conductor layer
- layer pattern
- copper foil
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims 2
- 239000000615 nonconductor Substances 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 239000011889 copper foil Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8927087U JPS63197334U (en18) | 1987-06-10 | 1987-06-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8927087U JPS63197334U (en18) | 1987-06-10 | 1987-06-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63197334U true JPS63197334U (en18) | 1988-12-19 |
Family
ID=30948110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8927087U Pending JPS63197334U (en18) | 1987-06-10 | 1987-06-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63197334U (en18) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024069963A1 (ja) * | 2022-09-30 | 2024-04-04 | ファナック株式会社 | プリント基板および実装品の製造方法 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5034170A (en18) * | 1973-07-27 | 1975-04-02 | ||
| JPS61222138A (ja) * | 1985-03-27 | 1986-10-02 | Toshiba Corp | 混成集積回路 |
| JPS6226831A (ja) * | 1985-07-29 | 1987-02-04 | Oki Electric Ind Co Ltd | 厚膜回路パタ−ン |
-
1987
- 1987-06-10 JP JP8927087U patent/JPS63197334U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5034170A (en18) * | 1973-07-27 | 1975-04-02 | ||
| JPS61222138A (ja) * | 1985-03-27 | 1986-10-02 | Toshiba Corp | 混成集積回路 |
| JPS6226831A (ja) * | 1985-07-29 | 1987-02-04 | Oki Electric Ind Co Ltd | 厚膜回路パタ−ン |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024069963A1 (ja) * | 2022-09-30 | 2024-04-04 | ファナック株式会社 | プリント基板および実装品の製造方法 |