JPS63197257A - Memory package - Google Patents

Abstract

PURPOSE:To reduce test time down to the time needed for a single memory part by giving simultaneously writing/reading actions to all plural memory parts at the time of a test. CONSTITUTION:An address is inputted onto a signal line 1 together with the write data and a timing signal supplied onto a signal line 2 and a signal line 3-1 respectively. Thus the timing signals are outputted to all memory parts 11-1-11-N via a signal line 10. If a write mode is set at this time point, the timing needed for writing is outputted and the memory data on a signal line 9 are written simultaneously into the addresses designated by the memory part addresses on a signal line 8 at all parts 11-1-11-N. When the timing signal on the line 3-1 shows a read mode, the read data on the signal lines 12-1-12-N are read out simultaneously in the same way as the writing mode.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to multiple independent controls for storage devices,
In particular, it relates to a storage package constituted by a storage section controlled in such a manner.

(Prior Art) With the remarkable progress of semiconductor integrated circuits in recent years, the capacity of memory integrated circuits in particular has increased, and large-capacity storage package that is small and has a low unit cost per bit has become available. .

Conventionally, this type of storage package is composed of a plurality of storage sections, and a method has been known in which % writing/extraction is performed by selecting the storage section using a selector.

(Problems to be solved by the invention) In the conventional large-capacity storage bankage configured with a plurality of storage sections described above, the percentage write/read control method does not allow the storage capacity to increase as the storage capacity increases. There is a drawback that the inspection time for the package is increased.

An object of the present invention is to simultaneously perform write/read operations on all of a plurality of storage units during testing.
It is an object of the present invention to provide a storage package that eliminates the drawbacks and is configured so that the inspection time for the storage package is not increased.

(Means for Solving the Problems) A storage package according to the present invention includes a plurality of storage units, an address distribution circuit, and a data distribution circuit.

It is configured to include a timing switching circuit, a data comparison circuit, and a storage section selection circuit.

The plurality of storage units are for storing input data at input addresses.

The address distribution circuit is for distributing input addresses to a plurality of storage units.

The data distribution circuit is for distributing input data to a plurality of storage units.

The timing switching circuit selects one of the plurality of timing signals when the test signal is input, transmits the timing of the selected timing signal to the plurality of storage units, and selects one of the plurality of timing signals when the test signal is input. If not, it is for transmitting each input timing signal to a plurality of storage units.

When a test signal is input, the data comparison circuit compares the read data from multiple storage units, checks whether all the data match, and signals an error signal if there is any difference. It is for outputting .

The storage section selection circuit is for inputting read data from a plurality of recorders and winding sections, and selectively outputs the data based on the inkstone output storage section information.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram illustrating one embodiment of a storage package according to the present invention. In FIG. 1, 5 is an address distribution circuit, 6 is a data distribution circuit, 7 is a timing switching circuit, 11-1 to 11-N are first to Nth storage sections, 14 is a storage section selection circuit, and 15 is a timing switching circuit. This is a data comparison circuit.

In FIG. 1, an address distribution circuit 5 receives an address on a signal line 1 and outputs a storage address on a signal line 8. Data distribution times F&6.

Write data on the signal line 2 is input, and the stored data is distributed to the first to Nth storage units ll-1 to 11-N via the signal line 9. The timing switching circuit 7 connects the signal lines 3-1 to 3-1.
Input the timing signal on signal line 3-N, and input all the timing signals on signal line 3-1 to 3-N, or all the timing signals on signal line 3-1 to 3-N according to the instructions of the test signal on signal line One of the timing signals is RAS, CAS% or W.
Signal line 1O-1-10-N as ET timing signal
6 first to output to each storage unit 11-1 to 11-N via
- The Nth storage units 11-1 to 11-N receive the storage unit address on the signal line 8, the storage data on the signal line 9, and the timing signal on the signal line 10=1-10-N. , performs write/read operations.

The storage section selection circuit 14 selects the first to Nth storage sections 1l-IA.
Input the output data from -11-N to signal lines 12-1 to 12-N, select the read data based on the storage information on the signal line 13, and send the pan cage reading ratio data onto the signal line 16. Output. The data comparison circuit 15 connects the signal line 12-
1 to 12-N read data are input, and if the testing signal on the signal line 4 is enabled, each data is compared, and if they do not match, all error signals are output on the signal line 17.

Next, the operation of this embodiment will be explained with reference to FIG.

In the case of normal operation, the test signal on the signal line 4 is not input. At this time, an address is input onto signal line 1, and embedded data is input onto signal line 2. Signal line 3
-M (1<M<N) When a timing signal is input on the signal line lo -M (1<MAN), the timing signal (when writing RAS, CAS%, and WET) are output, and the storage data on signal line 9 is written to the address specified by the storage unit address signal on signal line 8.

When the timing signal on the signal line 3-M (1 x M<N) indicates a read operation, the Mth storage section 11-M ( Timing signal to x M<N> (WET is not output during reading.)
is output, and the signal line 12-M (1<M<N) is output from the address indicated by the storage address signal on the signal line 8.
Read the read data upward.

At this time, since the memory section information on the signal line 13 indicates the M-th memory section, the memory section selection circuit 14 is connected to the signal line 12-M (1
<MriN) and outputs the pancage read data to the signal line 16.

Next, the operation when a testing signal is input from the signal line 4 in order to test the storage pancage will be described. At this time, the timing switching circuit 7 outputs the signals gi3-1 to gi3-N.
Select only the predetermined signals from among the above timing signals.

Assume that the timing signal on signal line 3-1 is selected.

Here, an address is input onto the signal line l.

When fill-in data is input to the signal line 2 and a timing signal is input to the signal line 3-1, the timing signal is output to all the storage units 11-1 to 11-N via the signal line 10. .

If it is a write operation at this time, the timing required for 1 writing is output, and the data is sent to the address specified by the memory address on the signal line 8 in all memory units 11-1 to 11-N on the signal line 9. The stored data of 1 is loaded at the same time.

When the timing signal on the signal line 3-1 indicates a read operation, the timing signal on the signal line 10 is output to all the storage units 11-1 to 11-N, and the signal line 8 The read data on the 1 signal lines 12-1 to 12-N are simultaneously read from the address indicated by the upper storage address.

Since the test signal is input on the signal line 4, the data comparison circuit 15 inputs the read data on the signal lines 12-1 to 12-N, compares the read data, and compares all the data. If they match, nothing is output.

If they do not match, an error signal is output on the signal line 17.

With this method, N
storage modules can be tested.

(Effects of the Invention) As explained above, the present invention allows the circuit to perform write/read operations on all of the plurality of memory sections during testing, thereby reducing the time required for the test to the time of one memory section. It has the effect of being able to shorten the time.

In particular, the nine-capacity storage package that has been realized in recent years has multiple storage modules and has a large storage capacity.
The present invention has the effect that the p test time can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating one embodiment of a storage package according to the present invention. 5...Address distribution circuit 6...Data distribution circuit 7...Timing switching circuit 11-1 to 11-N...Storage section 14...Storage section selection circuit 15...Data comparison circuit 1. 2.3-1~3-N, 4,8,9.10-1~10
-N, 12-1 to 12-N, 13.16.17...Signal line

Claims (1)

[Claims] a plurality of storage units for storing input data at input addresses; an address distribution circuit for distributing the input address to the plurality of storage units; and an address distribution circuit for distributing the input address to the plurality of storage units; a data distribution circuit that distributes data to the storage units; and, if a testing signal is input, selects one of a plurality of timing signals, and transmits the timing of the selected timing signal to the plurality of storage units; , a timing switching circuit for transmitting each input timing signal to the plurality of storage units when the test signal is not input; and a timing switching circuit for transmitting each input timing signal to the plurality of storage units when the test signal is input; a data comparison circuit for comparing read data from the plurality of storage units, checking whether or not all data match, and outputting an error signal if even one of the data is different; 1. A storage package comprising a storage section selection circuit for inputting data and selectively outputting data based on read storage section information.