JPS63197221A - Barrel shifter - Google Patents

Abstract

PURPOSE:To increase the arithmetic processing speed for addition/subtraction of floating points in consideration of a rounding mode, by using a detecting circuit for cancelling bit train. CONSTITUTION:The right arithmetic shift data of the positive significance is set at O (where O0 is defined as a most significant bit MSB) with On-1 defined as a least significant bit LSB respectively. Then a signal level opposite to the signal level set on a route 13 is outputted to an output terminal 15 in response to the change of the signal level of the route 13. At the same time, a bit train taken down from (n) digits at the time of the right arithmetic shift, i.e., a cancelling bit train is outputted to a route 25 as a signal level of the negative significance with -Zo and -Zn-1 set opposite to the MSB and the LSB respectively. A zero detecting circuit 16 decides whether (n) pieces of signals levels on the route 25 are all set at H levels or not. The result of this decision is outputted to an output terminal 17 in the form of the 1-bit information show ing the presence of absence of a bit taken down at the time of the right arithme tic shift.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention is needed in floating point addition and subtraction with rounding mode. This invention relates to a barrel shifter arithmetic unit that speeds up bit drop detection during right arithmetic shifts.

[Conventional technology]

FIG. 3 is a block diagram of a conventional barrel shifter, for example.

Assuming that the shifted data X is expressed as an n-bit signed binary number, (1) if there are n input terminals Xo to Xn-1 for applying the shifted data X as a positive and significant applied voltage・Xo is MS B (Mo5t
51gn1ficant Bit), Xrs-
1 is LSB (Least Significant
Btt).

Also, when shift number data τ is positive, perform left arithmetic shift.

Assuming that it is expressed as a signed binary number of m bits (however, m≧mg2n+1) indicating a right arithmetic shift when negative, (2!

Shift number data Y-i is given as a positive and significant voltage applied to Om input terminals y,) Nyrn-1, where CYo is MSB, Y! ++1-1 corresponds to LSB. (3)
, (4) are the clock input terminals CLK1 and CLK for dynamically operating the barrel shifter.
It is 2. (51if: Positive and significant selected data x (
x=xo.

X, . . . n signals m 80~an, -j and n of path B(7)
The preselector outputs to the main signal line b(, -brt-1).

(8) C consists of a combinational circuit based on the truth value shown in FIG. 8 which inputs the positive significant signal input to the input terminal CL K 2 (41) and the shift number data τ, and is connected to the path 5 (9).
) is a shift number depuder that outputs a positive and significant signal level to n signal lines So~.5n-1. aυ is an inverter element for inverting the signal level input from the input terminal CL K 1 (31).

The output signal line (l) of the inverter element aυ and the path A (6
).

n signal lines aQ to Ign-1. n signal lines bO'=bn-1 on route B (7) and n signal lines S on route 8 (9).

~S n-1 as input, route? 00tM at a negative significant signal level on n O signal lines 60 to 0n-1 of 1jai.
S.B.

Crossbar false switch array that outputs shift result data with 0n-1 as LSB, an1 is path 0 (to)
In order to invert the upper signal level, (Da inverter elements, (ll[n output terminals Oo~0H-1°(l
is an O zero detection circuit for detecting whether or not the entire shift result data is the logical value "O#" based on the negative significant shift result data on path 0 (I3), and aη is the 1-bit information This is an output terminal STK that outputs.

The inside of the crossbar switch array 0 is shown in FIG. The inside of Figure 4 is the power supply terminal to which the power supply voltage is applied,
(1'1tljP channel MO8 transistor, (to) is a transistor chain, j), there are nXn pieces. In addition, the internal configuration of the wire f: shown in FIG. @ is the ground terminal.

Next, the operation will be explained.

In a conventional barrel shifter, in order to obtain the right arithmetic shift result and information on whether or not there is a bit missing, that is, whether there is '11' in the bit string spilled from the number of digits at the time of right arithmetic shift, 2. 1 cycle operation is required.

In other words, n bits of shifted data are converted into P bits (P
2O) When performing a right arithmetic shift, in the first cycle operation, the number -P is the shift number data! is applied to the input terminal yoxym-1(2), and right arithmetic shift is performed to obtain right arithmetic shift result data 0. Next, in the second cycle operation, a numerical value n-p is given as shift number data Y and a one-digit missing bit string is obtained by performing an arithmetic shift to the left by III-p bits.

This is detected as a zero by a zero detection circuit, and the presence or absence of dropped bits during the right arithmetic shift is detected.

As shown in FIG. 6, one cycle operation consists of a non-overlapping two-phase clock φ1. It is composed of a combination of φ2 periods.

First, the first cycle operation will be explained.

At the same time as the beginning of the φ1 period of the first cycle operation,
Shifted data Xi input terminal X6-Xn-t (1)
A positive and significant applied voltage is applied so that Xo corresponds to the MSB and Xn-1 corresponds to the LSB, and the value -P is set as the shift number data Y to the input terminals Ya, YIT! −, y in (2)
.

A positive and significant applied voltage is given so that Ym-4 corresponds to the MSB and Ym-4 corresponds to the LSB. Above input terminals XO~Xn-
The applied voltages applied to v (1) and the input terminals TO- and YIn-1 (2) continue in this state until the start of the φ1 period of the second cycle operation. Also, during the φ1 period, an applied voltage of signal level ``H='' is applied to the input terminal CL K t +31, and the P-channel MOB run shifter 19 in the crossbar switch array q3 is turned on.・Precharge the n signal lines of 0E1, that is, the path δ (13) to the signal level "■".

・On the other hand, input terminals XO to xn-1 (1) and input terminal YO
~Ym-1 (preselector (5)
and shift number decoder (9) send output signals based on the truth values of FIGS. 1 and 8 to path A (61 and path B (7), respectively).
), output on route 5 (9). In addition, the input terminal CLK
2 (41 has a signal level of 1L except for the φ2 period).

If an applied voltage of d@H'' is applied during the φ2 period, the signal level number on the 9th path 5 (9) is shown in the truth value of FIG. @″L′.

Therefore, until the start of the φ2 period, the crossbar switch
N-channel MO8 transistor cnts which is a component of the transistor φ chain (a) in the crossbar switch array az whose gate input is the path 5(9) in the array a2, that is, So~5n-1.

It is in the OFF state. The charge precharged during the φ1 period is held on the path 0f13, and the path 0 (one signal line o of 13) = -on-1 until the start of the φ2 period.
The signal level of is in the ``H# state.

At the same time as the start of the φ2 period. Path 5 (9), which is the output of the shift number decoder (8), that is, the signal line go -5n-1t
iAs shown in Fig. 8. The signal level of any one of them is in the "H" state, and the others are in the "L'" state.

This toki, crossbar switch array (n × in 13
In the chain of n transistors (A), both N-channel MOS transistors Q9 and (2) are O
Charges on the signal line in the path 0fi31 connected to the drain side of the transistor chain (a) that changes to the N state are discharged.

In addition, as the signal level of path OI changes, output terminal Ql
~0n-IQFj Kij:, positive significant right arithmetic shift result data 0 (oo is MSB, on-i is LSB).

A signal level opposite to the signal level on path oa31 is output.

At the same time, 1-bit information indicating whether the values of the right arithmetic shift result data 0 are all logical values is outputted to the output terminal 5TKOη.

that's all. The operation for obtaining the right arithmetic shift data result 0 when the 1-digit shifted data X is arithmetic shifted to the right by P bits in the first cycle operation has been explained.

Next, the second cycle operation will be explained.

In the second cycle operation, at the same time as the start of the φ1 period, n-P is used as the shift number data Y and the input terminal Yo-ym is
-1(2) is given as a positive and significant applied voltage.

The other operations are exactly the same as the first cycle operation.

That is, in the second cycle operation, the input terminal yo-
Yff1-. Since the shift number data T given to (2) is positive or 7o, this barrel shifter operates to shift the shifted data X given to the input terminal xo xxn-1 (1) to the left by n - P bits. Do the following.

Here, the n-P bit left arithmetic shift result data output to the output terminals Oo~On, 1 (1:I) is the n-P bit left arithmetic shift result data that is output by P bits right arithmetic shift of the 1-digit shifted data x, as shown in FIG. This shows the zero-digit bit string that has dropped from the 1st digit when
A signal level indicating whether or not there is a logical value ""1" in the 2-digit missing bit string is output to the output terminal 8 T K (171), which is the output of the G, so that it is possible to detect the presence or absence of bit missing.

[Problem that the invention seeks to solve]

A conventional barrel shifter is constructed as shown above. In order to detect the right arithmetic shift result and the presence or absence of a bit drop at that time, two cycle operations are required, and the calculation time is considerable. When performing a right arithmetic shift, -P and re-
In order to prepare two numerical values of P, there was a problem in that an additional full adder had to be provided.

This invention was made to solve the above-mentioned problems, and in one cycle operation, it is possible to obtain right arithmetic shift result data and information on the presence or absence of bit loss during right arithmetic shift. During bit right arithmetic shift, F-
The purpose is to obtain a barrel shifter that can be operated by preparing only one numerical value of p.

[Means for solving problems]

The barrel shifter according to the present invention includes a 9-digit dropped bit string detection circuit for detecting the presence or absence of dropped bits when right arithmetic shift is performed.

[Effect]

Barrel shifter according to the present invention 1. Outputs right arithmetic shift result data of an arbitrary number of bits in 11 operations, and uses a one-digit drop bit string detection circuit.

The digit loss bit string at this time is detected, the digit loss bit string is zero-tested, and information on the presence or absence of bit loss during the right arithmetic shift is output.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention, and (1
) to @ are exactly the same as the above-mentioned conventional device. , (Incorporated) is a crossbar switch array with a digit loss bit string detection circuit, and the conventional crossbar switch array shown in Figure 4.
This is the array 63 plus a missing bit string detection circuit. A configuration diagram of the crossbar switch array Qe with a lost bit string detection circuit is shown in Figure 2.In Figure 2,
aQ""'aH-1,bO~b n-1°so~
8n-j, oo~O, -IUp Similarly to the conventional device, each has one route A (61, route B (7), and route 5 (9)).

Corresponds to route Oa3.

Compared to the conventional crossbar switch array α2.

The transistor chain and n P-channel MOS transistors (II and n power supply terminals or a dropped bit string detection circuit are configured, and the signal line Zo -=-Z, -, that is, the negative Outputs a significant truncated bit string.

Next, the operation will be explained.

This barrel shifter operates in a dynamic manner, so as with the conventional barrel shifter, as shown in Figure 6,
The cycle operation is performed using a non-overlapping two-phase clock φ1. It is composed of a combination of φ2. Now, in order to arithmetic shift the n-bit shifted data XiP bits to the right and detect the right arithmetic shift result data and the presence or absence of bit loss, φ1
Simultaneously with the start of the period, the shifted data Xf input terminal X.

~Xn-1cil, Xo is MSB, xn-1 is LS
Apply as a positive and significant applied voltage corresponding to B,
The number -p (that is, the two's complement of P).

A positive and significant applied voltage is applied as shift number data Y to the input terminal yo -'ym, +21, and this state is continued until the end of the φ2 period. Also, during the φ1 period, an applied voltage of signal level 1H" is applied to the input terminal CLKI (31), and the P-channel MO8 transistor α in 04 is turned on.
By entering the N state, the path ZCa and the path 5 are precharged to the signal level 1H'. On the other hand, input terminal Xo
-XH-1 (1) *Input terminal To -ym-1 (2)
The preselector (5) and shift number decoder (8) output signals based on the truth values of FIGS. 1 and 8, respectively, according to the shifted data X and shift number data Y input from the route controller (6), Output on route B (route 5 (9)).

In addition, if the input terminal CLK2 (41 is applied with a voltage of signal level "L" except for the φ2 period and "H" during the φ2 period, the signal level on the path 5 (9) will be the truth value shown in FIG. 8. As shown, all periods except the φ2 period are at "L" level. Therefore.

N-channel MO8) transistor an1: jOFF whose gate input is the path 5 (9) in the crossbar switch array with one-digit drop bit string detection circuit until the start of the φ2 period
The charges precharged during the φ1 period are held on the path 0 (13) and the path 2 (c), and the n signals on each path Oα3 and path 2 (c) are held until the start of the φ2 period. The level is [@H' state.

At the same time as the start of the φ2 period, the signal line 5o-=-8n-1 of the path 5 (9), which is the output of the shift number decoder (8), becomes 0.
The signal level of any one of the signals becomes "H" state, and the other becomes V'i@L" state. At this time, the transistor chain in the crossbar switch array with digit loss bit string detection circuit In the N-channel MO8) transistor, both transistors and υ change to ON state.
Path 0 (1:
The charges held on path ZC2!9 are discharged and changed to @L'' level.
(Output terminals 00~0n-1
(At t5, set the right arithmetic shift result data of positive significance to 0 (00 is MSB, 0n-1'1LSB), and select the path?
A signal level opposite to that on 5a3 is output. At the same time, the path 'i(2!9) has O at the right arithmetic shift.
The bit string spilling from the n digit, that is, the missing bit string, has a negative significance signal level, and the lice is the MSB, and Z and 1 are the LSB.
is output as the corresponding one, and the signal level on this path 2 (c) is detected by the zero detection circuit, and all n lines are detected.
Determine whether it is at H# level (i.e. @0”),
The determination result is outputted to the output terminal 5TKaη as 1-bit information indicating the presence or absence of a bit drop during the right arithmetic shift.

〔Effect of the invention〕

As mentioned above, in this barrel shifter.

By being equipped with a dropped bit string production circuit, it is possible to obtain the right arithmetic shift result and the information on the presence or absence of bit dropping at this time in a single operation, so it is possible to take rounding mode into consideration1-
7 Also, speed-up of calculations in floating-point addition and subtraction can be achieved. Since the bit string detection circuits in the barrel shifter are arranged regularly, there is an effect that an integrated circuit with a high degree of integration can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a barrel shifter for explaining the present invention in detail, FIG. Figure 3 is a configuration diagram of a barrel shifter to explain a conventional barrel shifter, Figure 4 is a configuration diagram to explain the crossbar switch array in Figure 3, and Figure 5.
'j Figure 4 is a configuration diagram to explain the transistor chain, Figure 6 is a time diagram to explain the timing.
It is a chart. Figure 7 is a diagram for explaining the truth value of the preselector (5), and Figure 8 is the shift number decoder (8).
Figure 9 is a diagram for explaining the truth value of. FIG. 3 is a diagram showing the relationship between shifted data and arithmetic shift results. In the drawings, the same or equivalent parts are designated by the same reference numerals.

Claims (1)

[Claims] In a barrel shifter, which is a type of arithmetic unit in an integrated circuit that can shift an arbitrary number of bits in one operation, the shift number is given in two's complement notation, and if it is positive, it is shifted left,
When negative, it has a right arithmetic shift function, and includes a clock input terminal into which two clock signals are input for dynamically operating this barrel shifter, and an inverter for inverting the phase of one of the two clock signals. an input terminal for inputting the shifted data, an input terminal for inputting the shift number data, a preselector that performs preprocessing on the shifted data according to the value of the shift number data, and the shift element. A crossbar switch equipped with a shift number decoder that decodes numerical data, and a zero-digit bit string detection circuit that receives signals generated by the preselector and the shift number decoder as input and outputs a zero-digit bit string and shift result data. - an array, a zero detection circuit that zero-tests the zero-digit bit string that is the output of the crossbar switch array, and an output terminal that is the output of the zero-detection circuit and outputs information on the presence or absence of bit loss;
A barrel comprising: an inverter element for positively and significantly inverting the phase of the shift result data that is the output of the crossbar switch array; and an output terminal from which the positive and significant shift result data is output. shifter.