JPS63197113A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To prevent the production of soft errors through an alpha-ray by using a signal obtained via a set/reset latch from an affirmative and negative output as a feedback signal. CONSTITUTION:A signal being the result or ORing an output of a set/reset latch (RS latch) 11 using the affirmative output signal Q and the negative output signal, the inverse of Q as the set and reset inputs respectively and the affirmative output signal Q or the negative output signal, the inverse of Q, is used as a feedback signal. That is, in using the RS latch 11 comprising the NOR gate in place of a conventional NOR gate, the latch 11 is set or reset by the H level input and the signal is transmitted and not inverted by the L level input (in holding state). Thus, an error signal where the output goes from L to H level is not caused. Thus, the flip-flop circuit not causing any soft error due to the incident of an alpha ray is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip-flop circuit that temporarily stores information in a logic device, and in particular, to a flip-flop circuit that temporarily stores information in a logic device.
The present invention relates to a flip-flop circuit suitable for use in SI.

[Conventional technology]

Conventionally, there is a flip-flop circuit for preventing soft errors caused by alpha rays, etc., as disclosed in Japanese Patent Application Laid-Open No. 169015/1985 filed by the present inventors. As shown in FIG. 8, for example, the technique described therein is such that the original feedback loop of the flip-flop is duplicated by an auxiliary feedback loop 81. OR of
The output is fed back to gate 84 via AND gate 85, while an auxiliary feedback loop 81 configured based on the concept of redundancy feeds from the NOR output of gate 84 to OR gate 82. Gate 8 via inverter 83
4 Feedback will be given.

With this configuration, the α-ray noise that may occur in the output of the gate 85 and the α-ray noise that may occur in the inverter 83 can be changed from a logical high level (hereinafter referred to as H level) to a logical low level (hereinafter referred to as L). In this case, unless α-ray noise occurs simultaneously in the outputs of both the gate 85 and the inverter 83, the flip-flop will not be inverted.

FIG. 9 is a conceptual representation of the above example. The logic part of the flip-flop is defined as the entire flip-flop excluding a part of the feedback, and the auxiliary feedback loop is denoted by 91.
91 from ζ- through NOR gate 93 and OR gate 92
Hefeed back. Here, the OR gate 92 and its output 94 are described in this manner for logical expression, although this portion is not duplicated in this figure.

In reality, if the gate 84 is implemented as shown in FIG. 8, there will be no unduplicated portion. Furthermore, depending on the way the gate is implemented, if alpha noise cannot occur in the output of the OR gate 92, the connection 94 does not need to be duplicated.

Also, as the positive side output Q as shown in FIG.

If two independent signals (α-ray noise cannot occur at the same time and are logically the same) can be used, the output signal lines 95 and 101 are logically ORed by the gate 92 and fed back to the ninth signal line. The same effect as shown in the figure can be obtained.

[Problem that the invention seeks to solve]

The above-mentioned prior art is an invention that attempts to prevent α-ray soft errors in flip-flops by duplicating the feedback loop, but for example, in the configuration shown in FIG. 9,
Although there is no danger that the flip-flop will be inverted even if noise that lowers the H level to the L level occurs at the inputs 95 and 96 of the OR gate 92, an error will occur if there is noise that raises the H level from the L level to the H level. There is still a risk of This is because the gate 92 is an OR, so if either of the inputs 95, 96 goes to H level, the output 94 goes to H level.

It can be said that the above risks are relatively small. because,
In the above case, noise that lowers the H level to the L level occurs in the Q output of the NOR gate 91, and that noise
Large enough to pass 3.

This is because the noise that raises the L level to the H level occurs in 96 only. However, this possibility is not completely eliminated, and there is still a problem that there is a possibility of soft errors caused by alpha rays.

The present invention solves the problems of the prior art mentioned above.

It is an object of the present invention to provide a flip-flop circuit that does not cause soft errors due to alpha rays.

[Means for solving problems]

The above object is achieved by using signals obtained through a set-reset latch (hereinafter referred to as FRS latch) for the positive side and negative side outputs Q and Q as feedback signals in the flip-flop circuit.

[Effect]

In FIG. 9, which shows the conventional circuit configuration, the NOR gate 9
If a set-reset latch (RS latch) consisting of a NOR gate is used instead of 3, this latch becomes
While it is set or reset by an H level input and the signal passes, it is not inverted by an L level input (hold state).

Therefore, the output 96 will not generate an error signal from the L level to the H level.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The α-ray noise considered here works to lower the output of a certain circuit from a logical high level (H level) to a logical low level (L level). Now, we only need to consider this error mode.The opposite mode, that is, the error from L level to H level, does not occur.However, noise from H level to L level will change from L level when it passes through the NOR gate or inverter. This will cause noise to the H level, so this needs to be taken into consideration.

In FIG. 1, the logical part of the flip-flop is defined as the entire flip-flop excluding a part of the feedback, and is represented by 10. 19, it is input to the RS latch 11. First, consider when Q is at H level. 18, 16
, 17.15 are at H level, and 19 is at L level. Further, 110 is an L level, and 111 is an H level. When α-ray noise (hereinafter simply referred to as α-ray noise) that lowers the H level to the L level occurs at Q, 18°16 tries to become the L level, but since 11,1 is the H level, The noise generated at 18 does not pass through the NOR gate 12,
Therefore, no noise occurs on the feedback line 17, and hence no noise occurs on the feedback line 15, so this flip-flop does not cause an inversion error.

Next, the output of the NOR gate 13, exactly 1i1 or 17
When α-ray noise occurs, since the signal 16 is at H level, the α-ray noise does not pass through the OR gate 14, and no noise is generated in the feedback l115, so this flip-flop does not cause an inversion error.

Regarding the output of the OR gate 14, it is assumed that α-ray noise cannot occur, as will be described later.

Therefore, when Q is at H level, this flip-flop is exactly the same as the conventional example shown in FIG. 9 with respect to the operation of 0 or more without causing an inversion error.

Next, consider when Q is at L level, that is, when Q is at H level. 19 is H level, 18°16.17,15
becomes L level. Further, 110 is an H level, and 111 is an L level. When α-ray noise occurs in ζ-, 19
tries to go to L level, but since 110 is at H level, the noise generated on 19 does not pass through NOR gate 13, and therefore no noise is generated on 17.Therefore, noise is also generated on feedback line 15. This flip-flop will cause an inversion error.

When α-ray noise occurs at the output 110 of the NOR gate 12, since the signal 19 is at H level, the α-ray noise does not pass through the NOR gate 13, and as in the case above, this blip-prop does not cause an inversion error.

To summarize the above, α to lower the H level to the L level
If line noise occurs at a point in this flip-flop circuit, inversion errors caused by it can be completely prevented. After all, this operation utilizes the fact that when the RS latch is configured with a NOR gate, it is set or reset with an H level input, and is in a hold state with an L level input.

The OR gate 14 and its output 15 are not duplicated in this figure. Therefore, the output of the OR gate 14 must have a circuit configuration that does not generate α-ray noise.This will be explained later, but in other words, parts that cannot be duplicated in principle, for example, should not be duplicated. There is always a part that compares the output of the part that is running, and here it is.

It is expressed by the OR gate 14 and its output 15. The circuit structure of Japanese Patent Application Laid-Open No. 61-169015 filed by the present inventors and the present invention enables a structure in which α-ray noise does not occur in this portion.

FIG. 2 shows another embodiment according to the invention, in which R
This is a case in which α-ray noise does not occur in the output 24 of the NOR gate 23 as the S latch 21, and in this case, the OR gate 14 as shown in FIG. 1 can be omitted. Other circuit operations are the same as in the case of FIG.

FIG. 3 shows more specifically the embodiment shown in FIG. 1 applied to a D-type flip.

Here, we will introduce a series-gate emitter-coupled logic circuit (
ECL) is used. The operation of this circuit is such that when the clock input CK is at H level, a current flows through either one of the collector load resistors 318 and 319 according to the data input, and the contents of the flip-flop are determined. When CK is at L level, data is held by the pair of transistors 304 and 305. Connection 317 is a feedback line.

300 corresponds to the RS latch in Figure 1, and the OR
Transistors 307 and 30 correspond to gate 14.
This is a wired OR implemented by 8. In other words,
The respective emitters of transistors 307 and 308 are connected and fed back by 317. here,
Since α-ray noise cannot occur in the wired OR of transistors 307 and 308 due to its configuration, the assumption stated in the explanation of FIG. 1 is satisfied.

FIG. 4 shows a case where the feedback line in FIG. 3 is made differential. In other words, the wired OR output 405 from transistors 402 and 403 and the transistor 401
By utilizing the fact that the wired OR outputs 406 from the transistors 304 and 404 are in opposite phase to each other,
0 circuit operation and α that feed back to the base of 05
The operation for line noise is almost the same as in the case of FIG. 3, so a description thereof will be omitted.

5, 6, and 7 show specific configurations of the RS latch 300 in FIG. 3. A pair of transistors 501 and 502, a pair of transistors 601 and 602, and a pair of transistors 701 and 702, respectively.

This corresponds to the NOR gate 311 in FIG. Also.

Each of the pairs of transistors 503 and 504, the pair of transistors 603 and 604, and the pair of transistors 703 and 704 is connected to the NOR gate 312.
corresponds to

In the embodiment shown in FIG. 1, the OR gate 14 is used, but depending on the configuration of the flip-flop, the gate 14
A NOR gate can also be used as a gate.

In addition, if only noise that raises the L level to the H level is possible, the RS latch 11 of the present invention
It is clear from one or more discussions that a D gate can be used and an AND or NAND gate can be used as the gate 14.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a flip-flop circuit that does not cause any soft errors caused by the incidence of alpha rays.

[Brief explanation of the drawing]

1 is a diagram of one embodiment of the invention, FIG. 2 is a diagram of another embodiment of the invention, FIG. 3 is a detailed circuit diagram of FIG. 1, and FIG. 4 is another detail of FIG. 1. FIGS. 5 to 7 are detailed circuit diagrams of the set/reset latch shown in FIG. 3, and FIGS. 8 to 10 are diagrams showing configuration examples of conventional circuits. 1 l, 1y 1 n*... Input terminal of flip-flop, 10... Logic part of flip-flop, 11, 2
1,300°400...set/reset/latch,
Q...Flip-flop positive side output, Q-...Flip-flop depth 1 Figure W 2 Figure N, zIR57+17g. Fig. 4 Fig. 5￥J6 Fig. 1'JE5 Fig. 7 gx 洒♂ Fig. θ1
Kate 33 Ishibata

Claims (1)

[Claims] 1. In a flip-flop circuit that temporarily stores logic information, the output of a set/reset latch that uses a positive output signal and a negative output signal as set and reset inputs, respectively, and the positive output A flip-flop circuit characterized in that a feedback signal is a signal obtained by logically ORing a signal or a negative output signal. 2. Logically OR the two mutually opposite output signals of the set/reset latch with the positive side output signal or the negative side output signal, and use the two mutually opposite phase signals as a differential signal. 2. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is a feedback signal.