JPS63193232A - Parallel data processor - Google Patents

Abstract

PURPOSE:To obtain a speed increasing mechanism for high-performance by using two propagation arithmetic systems incorporated in respective processors and advancing two kinds of propagation arithmetic by the processors in parallel. CONSTITUTION:Oscillation processors are assigned by loading '1' in the control register 19 of a processor 1 in the processor block 20 at the leftmost end and '0' in other registers 19. While an address A0 of a storage part is accessed by each processor, an ALU 11 is set to addition and when propagation addition is started, an upper ad a lower propagation arithmetic system constituted in each block by cascading ALUs 11a and 11b perform 1-bit propagation addition regarding the address A0 in parallel as to both cases wherein an input is '0' or '1', so that the sum of the output is determined by the block 20 at the left end when the addition is finished. The determined sum is stored in the address A0 and its carry is stored in a register 18. similar processing is repeated as to A1-An of the storage part.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is characterized in that the built-in processor array is composed of a cascaded array of processors having almost the same configuration, and the connections between the processors are simple, regular and local. What's more, even though there are few connection lines between modules (such as LSIs, boards, etc.) equipped with multiple processors to implement a processor array, propagation calculations (configuring the array) that allow efficient calculations and transfers are possible. The present invention relates to a parallel data processing device that executes operations and transfers (operations and transfers that are sequentially propagated between processors) at higher speed.

(Prior Art) In designing a processor array type parallel data processing device (hereinafter referred to as an array processor), one of the important issues is how to transfer data and perform calculations between distant processors at high speed. This is because, in general, when high speed is pursued, the number of connection lines between processors increases significantly, and the simplicity of the connection configuration between processors deteriorates, making it difficult to realize the device. This problem is particularly serious in an array processor (two-dimensional array processor) consisting of a two-dimensional array of processors, which has a large number of processors. For this reason, in two-dimensional array processors, the propagation calculation method CA, P, REEVES is used, which is a high-speed method with a small increase in the number of connection lines.

'A Systematicmlly Designs
d Binary ArrayProcessor',
IEEE Trans,Comput,vol,C-
29°pp 278-287 (1980). Reference 1 below
That's what it means. ] is useful. (A propagation operation is an operation in which arithmetic operations are carried out within a processor and the results are propagated one after another via a connection line between adjacent processors, without synchronizing the processors with an intermediate clock.

If the arithmetic function is set to pass, it becomes a simple data transfer. )This is because although this calculation method does not significantly reduce the ease of implementing the device compared to a transfer method that uses a normal bus, (1) the number of synchronizations and memory/register accesses is reduced. Therefore, processing that can be realized by passing data between processors one after another while processing the data (
For example, summation calculations) can be accelerated. (2) P different from bus
Since the transfer system is not occupied by one set of data, it is possible to transfer multiple sets of data at the same time in the same system as long as the transfer sections do not overlap with each other. This is because it has the following advantages. The propagation calculation is also effective as a means for efficiently executing fill-in processing and connected region extraction processing in image processing [Reference 1]. However, with this calculation method, the propagation time increases in proportion to the number of processors passing through, so if there are many processors passing through, the disadvantage is that the transfer and calculation time becomes too long, or the processor that actually performs the calculation is This method has the disadvantage that the effective degree of parallelism is reduced because it is limited to the processors currently involved in the propagation calculation (in other words, the processors at the leading wavefront of the propagation). Therefore,
We have proposed a method (hereinafter referred to as bypass-added propagation calculation method) that adds bypasses to the propagation path at appropriate intervals and thereby performs propagation calculations hierarchically (hereinafter referred to as the bypass-added propagation calculation method). Publication No. 29550, patent application 1982-
No. 016659.

However, as a result of subsequent studies, it has become clear that this bypass is often too labor intensive to hierarchize and is not useful for speeding up. An example of this is the process of determining the run length of white or black connections on a binary line used for encoding for image information compression, feature extraction in character recognition, and the like.

The method of determining run length by propagation calculation is simple. Assuming that the pixels (white dots or black dots) constituting a line are attached to processors one-to-one, the leftmost first processor in each connection and black connection on the line is the originating processor, and the other processors are the adding processors. All we need to do is perform a rightward (from the beginning to the end) propagation addition. Here, the originating processor is a processor that ignores the input from the left neighbor during propagation addition and outputs a logical value "1" to the right neighbor processor, and is the p1 addition process.

is a processor that adds 1" to the input from the left neighbor and outputs it to the right neighbor processor.As is clear from the operation of these processors, as the process progresses, each processor receives the input from the left end of the connection to which it belongs. The distance is calculated. When the propagation reaches the right end of the connection, the run length of the connection is obtained by the processor at the right end. The above run length calculation is performed using a one-dimensional processor array (6th If you try to execute it hierarchically (see figure), the procedure becomes complicated as follows.

[Step 1] Check whether there is a processor at the beginning of a white or black connection among the four processors (110 & ~ 110d) that can be skilagged in the binoculars 113.
The result obtained by the propagation logical operation between the processors is written to the PAYAS control register 115. This results in 4
If there is no processor at the left end of the connection among the processors, the bypass selection selector 114 is selected to the bypass side, and if there is, the bypass selection selector 114 is programmed to be selected to the non-bypass side.

[Step 2] With the selector 114 set to the non-bypass side, each 110
A propagation addition is executed with the processor of a as the originating processor and the other processors as the addition processors, and the results are held in each PE (processor element).

[Step 3] Each 110d processor outputs 0, and each 110e processor outputs the value obtained by adding the result obtained in step 2 to its input if it is an addition processor, or outputs the value obtained by adding the result obtained in step 2 to its input if it is an originating processor. 1, the propagation addition is executed while the selector 114 is controlled by the bypass control register 115 programmed in step 1, and the result is held in the processor 110e.

[Step 4] The 110m processor that is not on the left end of the connection is used as the origination PE that outputs the result obtained in step 3, the leftmost processor on the connection is used as the origination PE that outputs 0, and the other processors are the transfer processors that output the input as is. A propagation transfer is executed and the result is held in each PE.

[Step, 7D5] Results obtained in step 2 and step,
The results obtained in step 4 are added at each PE, and the results are used as the final propagation addition results.

Since each of the above steps requires more than a few instructions to execute, the total number of machine cycles required is Q larger than that without hierarchization unless the array size is very large. Of course, most of these instructions/steps can be reduced by adding appropriate wiring logic nodes and executing them in parallel. However, if this is done, the simplicity and regularity of the hardware configuration of the array processor will be disrupted, and the ease of realizing the device will be reduced.

By the way, in a -dimensional array processor, if the column direction of the two-dimensional array data is allocated in the depth direction of the local memory of each processor, and the row direction is arranged in the array direction of the processor, Processing using propagation operations (e.g. projection processing, run length calculation,
(intersecting line number coefficient, etc.) can be efficiently emulated in the column direction. This is because in a -dimensional array processor, so-called raster scan scanning is possible simply by changing the local memory address and accessing data, and the one-dimensional array of the processor can be easily allocated to the leading wavefront of propagation. This is because there is no need for data transfer operations between distant processors. In the row direction, the entire local memory array of each processor is two-dimensional access memory (memory that can be accessed from both the row and column directions).
If so, it can be similarly emulated by reading the rows in the depth direction and the columns in the array direction. That is, in a -dimensional array processor, by using a two-dimensional access memory, propagation operations can be executed at high speed.

There are two main ways to configure a two-dimensional access memory. One method is to configure a two-dimensional access memory with equal constraints by adding an address conversion circuit and a data rearrangement network (this corresponds to a network for connecting between processors) to a normal memory array [Motooka et al. “Associative processing system using two-dimensional memory” IEICE Technical Report EC76-8
0° or less is referred to as Document 2. The other side is directly connected to the IC.

A method for configuring a two-dimensional access memory on a memory card [Morita and Yamane, "Circuit construction method for multi-address memory," 1985 IEICE General Conference 476, hereinafter referred to as Reference 3. It is Ko. However, in both methods, compared to the previous propagation calculation method, (1) the hardware of the two-dimensional access memory is relatively heavy; (2) It is not possible to increase the size of the processor array simply by vertically connecting identical components and modules. There are drawbacks such as.

(Problems to be Solved by the Invention) The present invention provides a parallel data processing device incorporating a regular array of multiple processors, in which the conventional mechanism for speeding up propagation operations between processors is insufficient to speed up operations. Another object of the present invention is to provide a parallel data processing device that can achieve a higher performance propagation operation speedup mechanism that solves the problem that it is not effective in processing such as run length calculation.

(Means and effects for solving the problem) The present invention is such that a processor row involved in inter-processor propagation operations is divided into processor rows of appropriate size, and the bit-wise input to each block is O. A configuration in which the propagation operations for both cases of 1 are performed before the input arrives, and one of the two propagation operations is selected as the correct propagation operation depending on the actual input to the block (0 or 1). The most important feature is that

Conventional technology is based on the premise that each processor uses one set of propagation calculation systems to perform one propagation calculation for a propagation calculation target. The difference is that two consecutive propagation operations are performed in parallel.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a regular array of 5×N 1-bit processors (in this case, a one-dimensional array consisting of N sets of processor blocks), a control unit, etc. according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating a parallel data processing device. In the overall configuration diagram in (a), 20 is a processor block consisting of five processors, 21, 22, 23 are block terminals, 25 is a connection line between blocks, 26 is an input terminal to the processor array, and 27 is a processor A Tagata terminal from the array, 30 is a control unit for generating a signal for controlling the processor array, and 31 is a signal line for broadcasting the generated signal to all processors.

Figure 1) is a processor block configuration diagram, where 1.1' is a 1-bit processor, 2 to 8 are terminals of the 1-bit processor,
9.10 is a connection line between processors.

Logic values "'0" and "1" are input to terminals 2 and 3 of the leftmost processor 1, respectively.(c)
(d) is a configuration diagram of a 1-bit processor of 1 and 1', where 11a and Ilb are 1-bit processors that have the same function during propagation calculation.
In the operation 22, G (ALU), 12.13 of the G configuration, if the input value of the terminal 6 is '0'' during the propagation calculation, the AL of 11a
A selector that selects and outputs the input from U, and conversely selects and outputs the input from the llb ALU if the input value is '1'' (other than propagation calculations, selects the input from the llh ALU and outputs it). 14 is a storage unit with a configuration of shrimp and t, 15m and 15b are terminals 2 and 3 during propagation calculation.
Selector that selects and outputs the input from the 1-bit register 16.
, 171i, during shift transfer from left to right between processors, in the case of processor 1, the input from the processor block on the left is selected, and in the case of processor 1', the input from the processor block on the left is selected, respectively. The output selector (inputs from the selector 12 is selected and output in cases other than shift transfer), 16r18.19, is a 1-bit register. Register 19 is for control to define the originating processor, and selectors 15m and 15b select input from register 16 when the content is 1, and select input from terminal 2 or 3 when the content is O. 1-bit processors 1 and 1'
The only difference is whether the signal from terminal 6 or the signal from terminal 2 is input as the left input of selector 17.

As an example of the propagation operation according to this embodiment, bit-serial type propagation addition (refer to the explanation of bit-serial type propagation addition described later) is used to calculate The case of calculating the sum of bit data will be explained step by step.

[Step 1] Control register 1 of the leftmost processor (leftmost processor 1 in the leftmost processor block)
9 is loaded with 1, the control registers of the other processors are loaded with O, and only the leftmost processor is assigned to the originating processor. As a result, the leading processor in propagation addition matches the physical leading processor. ) is set.

[Step 2] Memory unit A1~ for all processors
An address and register 16. Clear Ill to 0.

[Step, f3] With the AQ address of the storage unit accessed, set the ALU to addition and start propagation addition. Then, within each processor block, the upper propagation calculation system consisting of the cascade connection of ALUs 11a and the other llb
As is clear from the inputs to terminals 2 and 3 of the leftmost processor in Figure 1 (bl), the inputs to the processor block are "0" and "
1” regarding the AQ address in parallel for both cases.
Propagation addition for pits begins. The key point is that the propagation addition of each processor block proceeds without waiting for the input to terminal 2). When the two systems of propagation addition are completed in each processor block, the output sum (the value at the terminal 22) is first determined in the leftmost processor block that is performing the same calculation in the two systems of propagation calculation systems.

The processor block at the next stage receives this sum, and by simply switching the selector 12, the calculation is completed and the sum of the output of the block is determined. This is because the intra-block propagation addition has already been completed for both possible input cases (add" and 11"). Therefore, after two systems of propagation addition are completed in each processor block, the propagation between processor blocks is extremely fast, and the overall propagation addition time is greatly shortened.

[Step 4] The sum determined in step 3 is stored in the Aya address, and the carry is stored in the register 18.

[Step, f5] Clear the shift by repeating the same process as steps 3 and 4 for A1 to An. Now, the effect of reducing the addition time of the present invention will be briefly evaluated. The comparison target is a basic one-dimensional processor array consisting of processors that have only connection lines between adjacent processors and only one set of propagation arithmetic systems. For general discussion, the number of processors in the processor blocks of the previous embodiment is N1, and the total number of processor blocks is M, and in order to be consistent with the embodiment, the number of processors in the basic one-dimensional processor array is L (=MXN). do. Propagation addition time t of each processor
Both dp are 1 unit time. This assumption suggests that even if the propagation calculation system is duplicated as in the embodiment, the reason for the increase in the propagation calculation time is that each processor has 151 or 15 bits per processor.
This can be said to be reasonable since only one extra selector is added to the propagation path. (In the 10-block diagram in Figure 1, the propagation calculation system contains only one selector and one ALU, but in the actual process f, many selectors etc. are included, so an extra number of selectors are included. (Also, the proportion of increase in the overall propagation delay time is small.) In addition, when the input is input to terminal 21 with the propagation addition of two systems completed in each processor block,
It is also assumed that the time idp until the output is output at 2 is 1 unit time.

This value can be said to be larger than when the propagation addition time tdp of each processor is set to 1 unit time, since an output is immediately produced by simply switching the selector 12 upon input to the terminal 21. Based on these assumptions, the propagation addition time TO in the basic one-dimensional processor array is T O = L...11) The propagation addition time TI in the embodiment of the present invention is as follows: The sum of the normal propagation addition time M and the high-speed propagation addition time N-1 between processor blocks in the next stage and subsequent stages is TJ=M+N-1 (2). Since L=MXN, T1 is reduced by pRk by choosing M and N to be integer values close to r, and at this time, T J
= 2 y'T-1------(31.(1
1. As is clear from equation T21, the larger L is, the higher the speedup rate according to the present invention is. The table shows the results of examining the relationship between TI and T2 by inserting an appropriate value into L.

Table Comparison of propagation addition times TI and T2 Next, as another example of the bit-serial type propagation addition according to the first embodiment, the leading processor ( A case will be explained in which the processor at the end of the concatenation exists in the middle of the grosser array.

The setting of the leading processor is achieved by writing 1 into the control register 19 of that processor and setting it as the originating processor, as described above.

In the originating processor, the content of the output of the register 16 (preset to O) is selected as the output of the selectors 15m and 15b, regardless of the position of the processor or subblock. Therefore, in this processor, terminal 2
, 3 is ignored and replaced with 'O' as the input to both propagation calculation systems, so that propagation addition starts with this processor as the head (that is, the logical head processor). Naturally, the upper and lower propagation calculation systems perform the same addition from the originating processor to the rightmost processor in the same processor block.Also, since the originating processor operates independently of the input from its neighbor,
At the same time that the entire processor array is set to propagation addition, propagation addition starts from this processor in the right direction, and by the time it moves to propagation addition between processor blocks, propagation addition within the block has been completed like in other processor blocks. Therefore, even if the first processor in the propagation addition is located in the middle of the array, the time required for the entire propagation addition will increase p
Unlike the additional type propagation calculation formula with one bypass, the control becomes complicated and there is no overhead associated with it.

So far, we have described propagation addition in which addition is selected as the ALU function, but if logical operation is selected as the ALU function, propagation-type logical operations can similarly be executed at high speed.

The present invention can achieve even higher speeds by adopting the ``guiline processing'' method. Pipeline processing can be easily realized in the first embodiment by simply adding or adding so-called registers to the processors 1 and 1'.

FIG. 2 shows the configuration of processors 1 and 1' to which the pipeline register is added. Hereinafter, this ``yebline propagation calculation'' will be explained with respect to a second embodiment in which only the processor 1.sub.1' in the first embodiment is replaced with that shown in FIG. 2.

Pipelined Propagation Addition Processor Pro.

The propagation addition within the processor blocks (for two systems, upper and lower) and the propagation addition between processor blocks are executed in antiparallel by pipeline processing. The operation is as follows when all the processors calculate the sum of L pieces of 1-bit data held in the storage units Ao address and AW+1 address.

[Stella 7'l) Setting of the first processor Load 1 into the control register 19 of the leftmost processor and O into the control registers of the other processors.

[Stella f2] Clear memory units and registers on all processors, memory units A1 to AW rA
Addresses w+2 to A2w+2 and registers 16, 18.4
0m.

Clear 40b, 41m, and 41b.

[Step 3] Propagation addition [Substep 3-1] By accessing address A of the storage unit and selecting addition as the ALU function, propagation addition for the contents of Ao is started. Then, in the case of the first embodiment, the propagation addition within the processor block proceeds to mHM. At the stage of propagation to the rightmost processor in the processor block, in each processor, the contents of registers 41h and 41b are transferred to register 18, and the obtained sum and carry are transferred to registers 40a, 40b and 41a, 41.
Write in b.

[Substep 3-2] Address AW+1 of the storage unit is accessed, and propagation addition X is started for the contents of address AW+1 while the ALU function is still selected for addition. On the other hand, the results obtained in the previous step (substep 3-1 in this case) (register 40m,
40b), propagation addition between processor blocks regarding the contents of AO is also started at the same time. As both of these propagation additions progress and the propagation is completed both within the processor block and between processor blocks, each processor obtains the summation result of the 1st bit of the AQ address determined by the propagation addition between the processor blocks. and register 41a
.

41b is written to AW+1 and register 18, respectively, and the two systems of sum and carry determined by propagation addition within the processor block are written.
Registers 40m, 40b and 41m, 4zbK! Get into it.

[Substep 3-3] The same process as substep f3-2 is performed except that AW+1 and AI+AO are rewritten as Aw+1.

Hereinafter, by repeating the processing of substellar f3-2.3-3 W times while sequentially incrementing the address of the storage unit, the summation result from the leftmost processor at address A0 to that processor is calculated at addresses AW+1 to AW+2. Then, the summation result of AW+1 is obtained as bit serial data at address AQ%Aw.

As is clear from the above operation details, the process.

Since propagation addition within a subblock and propagation addition between processor blocks are performed in parallel, if the propagation addition time between blocks and within a block is made equal, the overall propagation addition time can be significantly shortened.

Next, the case of logical operation will be explained. In this case, carry is not relevant, so 41m, 41b.

There is no need to move 13.18 mag. When each processor calculates the logical sum of five pieces of bit serial data of word length W+1 held in memory unit addresses Ao to AV, the operation is as follows.

[Stella 7''l] Setting of the first fa and s Loads 1 into the control register 19 of the leftmost processor and the control registers KO of the processors other than ξ.

[Ste, 762] Clearing registers On all the programs, registers 40m and 40b have already been cleared.

[Step, f3] Propagation logical sum [Substep 3-1] By accessing address A3 of the storage unit and selecting the ALU function as logical sum'), propagation logical summation for the contents of address Aa is started. In this case, as in the case of propagation addition, the propagation OR within the processor block proceeds first. At the stage where the propagation reaches the rightmost processor in the processor block, the results of the propagation OR of the two systems in each processor are stored in the register 40m.

Write 40bK.

[Substep, 7'3-2] Access the A1 address of the storage unit, and start the propagation OR for the contents of the A1 address while keeping the ALU function selected for OR. On the other hand, using the results obtained in sub-step 3-1 (registers 40m and 4ob), the propagation OR between processor blocks regarding the contents of Ao is also started at the same time. The propagation OR of both of these proceeds, and the propagation is completed both within the processor block and between the processes and subblocks. At the 9th stage, the OR result regarding address A3 determined by the propagation OR between the processor blocks is processed in each processor. Write to address A1. At the same time, the result determined by the propagation OR of the two systems within the processor block is written into the register 40*, 40 kB.

Below, substep 7D3-2 is returned W times while incrementing the address of the storage unit by 1, resulting in the logical sum of the bit serial data of Ao-Aw from the leftmost processor (of the entire array) to that processor. is obtained at A1 y+1.

Similar to the analogy of propagation addition, the propagation operations between processor blocks and within the processor blocks are performed in parallel, so the operation time is significantly shortened.

Next, we will compare the amount of hardware and ease of implementation of the hardware. The amount of hardware in the present invention is somewhat increased compared to the two conventional propagation calculation methods. This is because the propagation calculation system of the processor, which is the basic repeating unit, is duplicated. However, the increment is small compared to the hardware amount of the two-dimensional access memory when the array size is large. For example, if the processor has a 1-bit configuration, the increment of the present invention (1 bit that allows the basic propagation operation shown in FIG.
M1 diagram (c) for a bit processor, (processor increment of dl) is described in Reference 4 (ClMead and L,
Corrway.

'Introduction to VLSI System
Addison-Wesley (198
If configured using the transmitter and processor shown in Chapter 5 of 0)), 10
It is about 0 transistors. Therefore, it is possible to develop an LSI equipped with one or more sets of processor blocks as in the prior art, and a large processor array can be constructed simply by cascading the LSIs. On the other hand,
In a two-dimensional access memory, if the size of the processor array is L when it is configured directly on the IC chip, then LXL
[From Reference 3, the increment of 9 per processor is L memory cells, and pL up to about 64 is equivalent to the present invention due to the high degree of integration of the memory array. However, if L becomes larger than this, the difference from the present invention will become larger and larger, and it will eventually become impossible to mount the entire two-dimensional access memory on one chip. Of course, a large two-dimensional access memory can be constructed from a square lattice array of smaller two-dimensional access memory ICs that can be integrated into a single chip, but the number of components required is greater than the simple cascade connection of the present invention. It also becomes complicated. In addition, standard memory,
Although we will not discuss in detail the case where a two-dimensional access memory is constructed using an address conversion circuit and a data rearrangement network, if the size of the array is large, it is difficult to similarly integrate it into an LSI with a processor array. Even if an attempt is made to realize this by combining basic small data rearranging network ICs, it is still not possible to configure it by simple cascade connections [Reference 2].

Next, bit serial type propagation addition will be explained.

This propagation operation is an addition method that obtains the total sum by adding -digits (one bit at a time) in the same way as the calculations that people normally do by hand. The following will specifically explain the case where the sum of 1-pit data stored in the AQ addresses of the storage units of four processors is calculated as an example.

FIG. 4 shows an extracted ALU, a partial area of a storage unit, a register (for carry), etc. related to the calculations of each processor. Here, the area within the dotted line corresponds to one processor, and the value of 0.1 is the contents (initial value) of the storage unit register.

This figure shows the state before calculation, and all fields other than Ao are 0. Furthermore, the leftmost processor is the head of propagation addition, and the left inputs of Q and ALU are fixed at 0. Next, this propagation addition will be specifically explained using FIG.

Figure 5 (&) shows the state at the time when the propagation of addition regarding Ao is completed, and in the leftmost processor, O is added as a fixed input value, 1 is added as the content of AQ, and O is added as the content of the carry register. , as a result, the sum is 1 and the carry is 0. The three processors on the right operate in the same way, and as shown in the figure, thumb and carry are obtained. next,
When the Ao and carry registers are updated with these sum and carry, the results are as shown in FIG. 5(b). Here, the content written in Ao is the summation result of the first bit. Here, the contents of the carry register are not all 0, and it is necessary to perform rounding propagation addition to clear the carry.

FIG. 5(0) is a diagram illustrating the propagation addition for clearing the carry, and the addition between the carry generated by the previous propagation addition regarding AQ and the contents of A1 (0 for all processors). This shows a state in which propagation has ended.

The contents of A1 are all 0, and the carry register is 1 only in the third processor from the left, so as shown in the figure, the carries generated by propagation addition are all 0, and the sum is 1 only in the third and fourth processors from the left. . FIG. 5(d) shows the state after updating A1 and the carry register with these carries and sums. In this state, the contents of the carry register are all 0, and there is no need to perform propagation addition X to clear the carry. In other words, a summation result is obtained for AoSAl. In fact, starting from the leftmost processor, 1, 1, and 2.3 are entered as decimal values, and the fourth
As is clear from the AQ data array in the figure, correct results are given.

(Effects of the Invention) As explained above, the present invention is different from the conventional propagation calculation method or the method using two-dimensional access memory. This can be achieved simply by cascading the processors, and high speed propagation operations can be achieved regardless of the location of the originating processor. Therefore, it is extremely effective for a two-dimensional array processor with a large array size that has severe restrictions on the amount of hardware and uses many propagation operations. It is also useful when data handled by a -dimensional array processor can only be processed as one-dimensional sequence data, or when using other means (two-dimensional access memo'))'Jk would require too much hardware. It is.

Of course, a configuration can also be considered in which the two methods are used in combination with other means to compensate for the computations in which each other is weak.

For example, in a configuration in which a two-dimensional array processor is used in combination with a two-dimensional access memory, the present invention allows a two-dimensional access memory to perform a 90-degree rotation that cannot be achieved, and a one-dimensional amount that is difficult to speed up with a two-dimensional access memory. High performance can be obtained by having the propagation calculation mechanism of the present invention share the propagation calculation of column data.

The present invention is expected to be applied to one-dimensional and two-dimensional array processors for the purpose of these processes, as propagation calculations are frequently used in feature extraction processing in image processing and character recognition, CAD for LSIs and PCBs, etc. be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
The figure is a block diagram of a processor used in the second embodiment of the present invention, Figure 3 is a block diagram of a basic processor constituting a conventional processor array capable of propagation calculations, and Figure 4 is an explanation of bit-serial type propagation addition. Figure 5 is a block diagram showing the procedure for bit-serial type propagation addition, and Figure 6 shows a one-dimensional processor array to which the bino2 addition type propagation calculation method is applied. FIG. 1.1'... Processor with double propagation calculation system,
2...Input terminal of upper propagation calculation system, 3...Input terminal of lower propagation calculation system, 4...Output terminal of upper propagation calculation system, 5...Lower propagation calculation system Output terminal of 6...
- Input terminal for receiving the output of the preceding processor block, 2...Output terminal for the processor block, 8
...Input terminal for receiving control signals common to all professionals,
9.10... Inter-processor connection line, 14... Note tt
Unit, lla, Ilb... performance (ALU)
), l 2 , l 3 , 15 * , 15 b
, 17-Selector, 16.18.19...1 bit register, 20...Processor block, 2-no....
Input terminal of processor block, 22... Output terminal of processor block, 23... Control signal receiving terminal common to all processor blocks, 25... Connection line between processor blocks, 30... Control unit, 31. ...Common control signal line for processor block, 40m, 40b. 41m, 41b...Pipeline register, 110h
. 110b, 110a, 110d, 110*=processor, 113... bypass, 114... pinos4 selection select p, 115... pinos4 control register. Applicant's agent Patent attorney Takehiko Suzue (C) Kan 1 Figure 1 Figure 2

Claims (1)

[Claims] In a parallel data processing device that incorporates a cascade array of multiple processors, the processor array is also a cascade array of blocks that incorporate a cascade array of multiple processors, and each processor simultaneously performs the same function. A processor located at the end of the block includes a first arithmetic unit, a second arithmetic unit, and an arithmetic unit output selector for selecting any of the outputs of these arithmetic units, and the processor located at the end of the block The output is guided to the last block through the connection line between the blocks and used as a control signal for the arithmetic unit output selector of the processor in the adjacent block, and the processor not located at the end in the block receives the output of the first arithmetic unit. The output of the second arithmetic unit is led to the input of the first arithmetic unit of the adjacent processor at the end via the connection line between the processors, and the output of the second arithmetic unit is connected to the second arithmetic operation of the adjacent processor via the connection line between the processors. A parallel data processing device, characterized in that the first processor in the block receives mutually complementary fixed values as inputs to the first and second arithmetic units.