JPS63191639U - - Google Patents
Info
- Publication number
- JPS63191639U JPS63191639U JP8203287U JP8203287U JPS63191639U JP S63191639 U JPS63191639 U JP S63191639U JP 8203287 U JP8203287 U JP 8203287U JP 8203287 U JP8203287 U JP 8203287U JP S63191639 U JPS63191639 U JP S63191639U
- Authority
- JP
- Japan
- Prior art keywords
- package
- integrated circuit
- semiconductor integrated
- view
- circuit according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8203287U JPS63191639U (US07709020-20100504-C00041.png) | 1987-05-28 | 1987-05-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8203287U JPS63191639U (US07709020-20100504-C00041.png) | 1987-05-28 | 1987-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63191639U true JPS63191639U (US07709020-20100504-C00041.png) | 1988-12-09 |
Family
ID=30934319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8203287U Pending JPS63191639U (US07709020-20100504-C00041.png) | 1987-05-28 | 1987-05-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63191639U (US07709020-20100504-C00041.png) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5918695A (ja) * | 1982-07-22 | 1984-01-31 | 富士通株式会社 | Ｌｓｉ実装用基板とプリント板の組合せ装置 |
-
1987
- 1987-05-28 JP JP8203287U patent/JPS63191639U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5918695A (ja) * | 1982-07-22 | 1984-01-31 | 富士通株式会社 | Ｌｓｉ実装用基板とプリント板の組合せ装置 |
