JPS63190329A - Thin film crystal growth method - Google Patents
Thin film crystal growth methodInfo
- Publication number
- JPS63190329A JPS63190329A JP2177887A JP2177887A JPS63190329A JP S63190329 A JPS63190329 A JP S63190329A JP 2177887 A JP2177887 A JP 2177887A JP 2177887 A JP2177887 A JP 2177887A JP S63190329 A JPS63190329 A JP S63190329A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- compound semiconductor
- growth method
- crystal growth
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 17
- 238000002109 crystal growth method Methods 0.000 title claims abstract description 9
- 239000013078 crystal Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 150000001875 compounds Chemical class 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 239000000470 constituent Substances 0.000 claims abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 15
- 230000004807 localization Effects 0.000 abstract description 2
- 230000001902 propagating effect Effects 0.000 abstract description 2
- 230000007704 transition Effects 0.000 abstract 2
- 239000012535 impurity Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- -1 GaAs Chemical class 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野］
この発明は、半導体装置作製に用いるエピタキシャル成
長薄膜結晶の成長法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for growing epitaxially grown thin film crystals used in manufacturing semiconductor devices.
（従来の技術］
化合物半導体結晶はシリコンに比べて電子の移動度が列
えばＧ ａ Ａ ｓの場合約５倍と大きいので。(Prior Art) Compound semiconductor crystals have electron mobility that is about five times higher than that of silicon in the case of GaAs.
高速、高果墳回路用基板として、又、光素子として用い
られる［ヒ合物混晶結晶の基、板として広い応用範囲が
、実現もしくは１期待されている。しかしながら、一般
に、構成元素の蒸気圧が高いために、単結晶の作成は、
高圧容器内で高圧雰囲気にして上記結晶材料の融液我面
を液体封止剤（Ｇ ａ Ａ ｓの壜台にはＢｅ（Ｊｓ）
で覆い、単結晶を引き上げる液本封止チョクラルスキー
去（ｆ、ＥＣ去〕が一般に行わ１ている。It is expected that a wide range of applications will be realized or expected as substrates and plates for arsenide mixed crystals, which can be used as substrates for high-speed, high-density circuits, and as optical devices. However, in general, the creation of single crystals is difficult due to the high vapor pressure of the constituent elements.
A high-pressure atmosphere is created in a high-pressure container, and a liquid sealant (Be(Js) is applied to the glass bottle base)
Liquid sealing Czochralski et al. (f, EC etching) is generally carried out in which the single crystal is pulled up.
ＧａＡｓ１Ｃのｉ３ ｆこのウェハーにシリコン等の不
純物をイオン注入した後、８００℃程度でアニールを施
し、注入不純物を活性化する。しかる後に。i3f of GaAs1C After ion implantation of impurities such as silicon into this wafer, annealing is performed at about 800° C. to activate the implanted impurities. After that.
ショットキー電極、オーミクク電極ｆ Ｔ ｌ ／ Ｐ
ｔ ／Ａｕ、ＡｕＧｅ等で形成することによｆｉ、Ｉ
Ｃの基本素子であるＦＥＴが製造される。Schottky electrode, ohmic electrode f T l / P
fi, I by forming t/Au, AuGe, etc.
An FET, which is a basic element of C, is manufactured.
こうして製造されたＦＥＴの特性分布とウニｌへ−面内
の直径方向について調べた結果を＠２図（ｂ）に示す、
ＦＥＴの閾値電圧（Ｖｔｈ）ぼウェハー直径（ここでは
、［１１０）方向）に沿って緩やかな巨視的変動とこれ
に伴ってＶｔｈが成る巾を示す。Figure 2 (b) shows the characteristic distribution of the FET manufactured in this way and the results of investigating the in-plane diametrical direction.
The threshold voltage (Vth) of the FET shows a gradual macroscopic variation along the wafer diameter (here, the [110) direction) and the corresponding width of Vth.
微視的な変動が見られる。これ等の原因として前者に対
しては、イオン注入方向と結晶面との１４１対位置によ
ることが笠原等（Ｋａｓａｈａｒａ Ｊ、、５ａｋｕｒ
ａｉＨ，、８ｕｚｕｋｉ Ｔ、 、Ａｒａｉ Ｍ、ａｎ
ｄ Ｗａｔａｎａｂａ Ｎ、（１９８５）ＧａＡｓ
Ｉ ＣＳｙｍｐｏｓｉｕｍ、 Ｍｏｎｔｅｒｅｙ ）
ＶＣより報告さルている。Microscopic fluctuations can be seen. Regarding the former, the cause of these problems is due to the 141 pair position between the ion implantation direction and the crystal plane, as reported by Kasahara et al.
aiH,,8uzuki T, ,Arai M,an
d Watanaba N, (1985) GaAs
I CSymposium, Monterrey)
It has been reported by VC.
イオン注入後にこの様な特性を持つ結晶基板と用いてエ
ピタキシャル成長によりｓ結晶ｒ成長させることにより
一般に欠陥密度の減少が期待される。しかしながら、先
に述べた基板中の転位に伴う点欠陥、或いは不純物の活
性比率を左右する組成の不均一性は、その上に成長させ
る結晶に引継がれると予想される。その結果、基板に直
接イオン注入を砲して作成したＩＣの特性（第２図〕に
比べて顕著な特性向上が期待できない。A reduction in defect density is generally expected by growing an s-crystal by epitaxial growth using a crystal substrate having such characteristics after ion implantation. However, it is expected that the aforementioned point defects associated with dislocations in the substrate or the compositional non-uniformity that influences the active ratio of impurities will be inherited by the crystal grown thereon. As a result, no significant improvement in characteristics can be expected compared to the characteristics of an IC produced by direct ion implantation into the substrate (FIG. 2).
（帛明が解決しようとする間＠ａ）
半辱本長は製造用ウェハとしては、可能外限り欠陥１点
欠陥、不純物の少い、もしくは点欠陥。(While the company is trying to solve the problem @a) The main point is that for manufacturing wafers, as far as possible, a single defect, a small amount of impurities, or a point defect.
不純物が均一に分布し１局所的な変動全極小にする結晶
が望まれる。A crystal in which impurities are uniformly distributed and all local fluctuations are minimized is desired.
本発明の目的に、上述の点に鑑み、結晶基板にエピタキ
シャル成長を行った後、熱処理を施すことにより、その
上に製造さｎる素子が均一となる薄幀結晶成長去を提供
することにある。In view of the above-mentioned points, an object of the present invention is to provide a method for thin crystal growth in which devices manufactured thereon are uniform by performing epitaxial growth on a crystal substrate and then subjecting it to heat treatment. .
（間毬点？解決するための手段）
エピタキシャル法により成長させた結晶薄膜の特性は、
用いる基板に存在する欠陥、しＵえば、転立号に直噴依
存する場合と、これ等に析出する不純物等の点欠陥に依
存する場合がある。特にＧａＡｓ等の化合物半導体では
後者が問題となるので、あらかじめ基板中のこうした点
欠陥を一様に分布させることにより、薄膜の結晶性を向
上させることが可能である。しかしながら、ＧａＡｓ等
の■−■族化合物半ｙＩ一本においては、Ｖ族元素の蒸
気圧が高いので、この熱処理をＶ族元累分圧下で行う必
要がある。(Interval point? Means to solve the problem) The characteristics of the crystalline thin film grown by epitaxial method are as follows.
Defects present in the substrate used, for example, may depend on direct injection on the inversion, or may depend on point defects such as impurities precipitated thereon. Since the latter is particularly a problem with compound semiconductors such as GaAs, it is possible to improve the crystallinity of the thin film by uniformly distributing such point defects in the substrate in advance. However, since the vapor pressure of group V elements is high in a single half-yI group compound such as GaAs, it is necessary to perform this heat treatment under the cumulative pressure of group V elements.
本発明は化合物結晶基板、＠えば■−■族化会物上に、
エピタキシャル成長法によって成長させた結晶薄ｌ［を
、蒸気圧の高い■族元素例えば、Ａｓ元素雰囲気中で熱
処理を施す薄膜結晶成長法である。The present invention is based on a compound crystal substrate, such as a ■-■ group compound,
This is a thin film crystal growth method in which a thin crystal l[ grown by an epitaxial growth method is heat-treated in an atmosphere of a group Ⅰ element having a high vapor pressure, such as an element of As.
（作用〕
本発明のように熱処理することにより、＠記慴晶基板か
ら伝播した転位等の欠陥に局在するＥＬ２をはじめとす
る深い準位を作る固有欠陥等は、転位から拡散し、結晶
＃膜中に、一様に分布する様になる。この結果、上記固
有欠陥の局在による４気的特性の変化が極めて少く、一
様な結晶薄膜が得られ、その上に形成される素子は均一
な電気的特性を連取し得る。(Function) By heat treatment as in the present invention, intrinsic defects that create deep levels, such as EL2 localized in defects such as dislocations propagated from the crystal substrate, are diffused from the dislocations and # It becomes uniformly distributed in the film.As a result, there are very few changes in the four-dimensional characteristics due to the localization of the above-mentioned inherent defects, and a uniform crystalline thin film is obtained, and the elements formed on it are can exhibit uniform electrical characteristics.
（実施列） 以下本発明の一実施例を図面と用いて説明する。(Implementation row) An embodiment of the present invention will be described below with reference to the drawings.
第１図は熱処理の概略を示す。有機溶剤による洗浄等に
よる前処理を施したエピタキシャル成長法によって成長
させた結晶薄膜を有するＧ ａ Ａ ｓ結晶基板１と石
英管で作られた炉心管２中に置かれた支持台３上に置く
、ヒータ４で所定の温度、こＣＣは８００℃ニ保チ、Ａ
ｓ１５分圧で３ Ｔｏｒｒ含むＡｒガス５を流しながら
８時間熱処理を行う。FIG. 1 shows an outline of the heat treatment. A GaAs crystal substrate 1 having a crystal thin film grown by an epitaxial growth method with pretreatment such as cleaning with an organic solvent is placed on a support base 3 placed in a reactor core tube 2 made of a quartz tube. Heater 4 is used to maintain the specified temperature, CC is 800°C, A
Heat treatment is performed for 8 hours while flowing Ar gas 5 containing 3 Torr at a partial pressure of s15.
この過程で、結晶￥１模中の、点欠陥等が均一に分布す
ることになる。エピタキシャル成長法としては、列えば
、ＯｉｖｉＣＶＤ（Ｏｒｇａｎｏ Ｍｅｔａｌｌｉｃ
Ｖａｐｏｕｒ Ｐｈａｓｅ ｇｐｉｔａｘｙ ） 去
等を用い、半絶縁性Ｇ ａ 、’ｋ ｓ ｔｉ晶基板上
に、半絶縁性Ｇ ａ Ａ ｓ結晶簿膜を成長させる。In this process, point defects and the like are uniformly distributed in each crystal. Epitaxial growth methods include OiviCVD (Organo Metallic
A semi-insulating GaAs crystal film is grown on a semi-insulating Ga, 'ksti crystal substrate using a vapor phase gpitaxy method or the like.
第２図（ａ） 、 （ｂ）はこうして得られた半絶縁性
ＧａＡｓ結晶薄模上薄膜びエピタそシャル成艮模ｒ持た
ない従来の液内封止チョクラルスキー去によって年収し
た半絶縁性Ｇ ａ Ａ ｓ結晶基板にイオン注入によっ
て作成した電界効果トランジスタ（ＦＥＴ）アレイの特
性分布を示す、［１１０）方向に沿ったウェハ直径上に
、２００μｍピッチで咋らルたＦＥＴの閾値電圧の変物
は第２図１ｂ）に見られる閾陳覗圧変動に比べておよそ
１／１０に減少する。Figures 2 (a) and (b) show the semi-insulating film obtained in this manner by the conventional submerged sealing Czochralski et al. The characteristic distribution of a field effect transistor (FET) array fabricated by ion implantation on a GaAs crystal substrate is shown. The object is reduced by approximately 1/10 compared to the threshold pressure fluctuation seen in FIG. 2 1b).
本発明によって以下の効果が得られる。 The present invention provides the following effects.
１）薄膜成長時ＶＣ発生するまた、基板から伝播する点
欠陥、不純物が減少、もしくは均一化することによシ、
特性の均一なウニ八−が得られる。1) VC generated during thin film growth, as well as point defects and impurities propagating from the substrate, are reduced or made uniform.
Sea urchins with uniform characteristics can be obtained.
２〕 特性の均一なウェハーが得られることにより、こ
れを基板として作成した素子特性が均一になる。2] By obtaining a wafer with uniform characteristics, the characteristics of devices created using this as a substrate become uniform.
第１図は、本発明の一実施例を説明する為に用いた熱処
理の概略図、第２図は本発明の一実施例で得られたｌ″
ＥＴＥＴアレイの方法で得られたＦｌ１８Ｔアレイの閾
埴゛藏圧（Ｖｔｈ）のウェハー面内分布を示す図である
。
１・・・Ｇ ａ Ａ ｓ結晶基、仮、２・・・炉心管、
３・・・支持台、４・・・ヒータ、５・・・Ａｒガス。FIG. 1 is a schematic diagram of heat treatment used to explain one embodiment of the present invention, and FIG. 2 is a schematic diagram of l'' obtained in one embodiment of the present invention.
FIG. 3 is a diagram showing the in-wafer distribution of the threshold cell pressure (Vth) of the Fl18T array obtained by the ETET array method. 1...G a As crystal group, provisional, 2... Furnace tube,
3... Support stand, 4... Heater, 5... Ar gas.
Claims (5)
より、第２の化合物半導体を成長させる薄膜結晶成長法
において、第２の化合物半導体を成長させた後、構成元
素のうち蒸気圧の高い元素を含む雰囲気中で、熱処理を
施すことを特徴とする薄膜結晶成長法。(1) In a thin film crystal growth method in which a second compound semiconductor is grown on a compound semiconductor crystal substrate by an epitaxial growth method, after growing the second compound semiconductor, the second compound semiconductor is grown in an atmosphere containing an element with a high vapor pressure among the constituent elements. A thin film crystal growth method characterized by applying heat treatment.
徴とする特許請求の範囲第１項記載の薄膜結晶成長法。(2) The thin film crystal growth method according to claim 1, wherein the first compound semiconductor is a III-V group compound semiconductor.
ることを特徴とする特許請求の範囲第１項記載の薄膜結
晶成長法。(3) The thin film crystal growth method according to claim 1, wherein the second compound semiconductor is a group III-V or group II-VI compound semiconductor.
り作製するＧａＡｓ結晶とすることを特徴とする特許請
求の範囲第１項記載の薄膜結晶成長法。(4) The thin film crystal growth method according to claim 1, wherein the first compound is a GaAs crystal produced by a liquid-sealed Czochralski method.
結晶の作製の際に磁場を印加することを特徴とする特許
請求の範囲第４項記載の薄膜結晶成長法。(5) GaAs obtained by the above-mentioned liquid book sealing Czochralski method
5. The thin film crystal growth method according to claim 4, wherein a magnetic field is applied during crystal production.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2177887A JPS63190329A (en) | 1987-02-03 | 1987-02-03 | Thin film crystal growth method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2177887A JPS63190329A (en) | 1987-02-03 | 1987-02-03 | Thin film crystal growth method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63190329A true JPS63190329A (en) | 1988-08-05 |
Family
ID=12064517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2177887A Pending JPS63190329A (en) | 1987-02-03 | 1987-02-03 | Thin film crystal growth method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63190329A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05183189A (en) † | 1991-11-08 | 1993-07-23 | Nichia Chem Ind Ltd | Manufacture of p-type gallium nitride based compound semiconductor |
| JPH11274083A (en) * | 1998-03-24 | 1999-10-08 | Sumitomo Electric Ind Ltd | Compound semiconductor device and manufacture thereof |
-
1987
- 1987-02-03 JP JP2177887A patent/JPS63190329A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05183189A (en) † | 1991-11-08 | 1993-07-23 | Nichia Chem Ind Ltd | Manufacture of p-type gallium nitride based compound semiconductor |
| JPH11274083A (en) * | 1998-03-24 | 1999-10-08 | Sumitomo Electric Ind Ltd | Compound semiconductor device and manufacture thereof |
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