JPS6318835A - M-series code generator - Google Patents

Abstract

PURPOSE:To realize a general-purpose IC by attaining the mutual cascade connection of code generators comprising a steering gate and a flipflop circuit. CONSTITUTION:The titled device consists of a steering gate G whose input signal subjected to gate control by a strobe pulse and a flip-flop circuit SR connected to the steering gate and outputting a signal at the leading edge of the clock signal and is constituted by plural circuits connected in series. When the circuits are used in cascade connection, a chip select signal, the inverse of CS is used for the preparation of code generation to apply each code generator.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an M-sequence code generator for digital data.

[Summary of the Invention] The M-sequence code generator according to the present invention has the following functions: (1) Feedback input terminal (FBO) (2) Input terminal to the first stage steering gate (FBI) (3) Input terminal from the final stage exclusive OR gate Output terminal (CA
S) (4) Three-chip 1 to output terminals (FB2) from the multiplexer circuit, and (5) control input terminal (FBCNT) of the three-state output multiplexer circuit, and can be connected in cascade.

When connected in cascade, it has a flip-flop circuit whose data input is a feedback control signal (FBCNT) that controls whether to feed back the output of the multiplexer circuit in the M-series code generator, and whose clock input is a strobe pulse (STB). Furthermore, the output of this flip-flop circuit is used as an enable input of a three-state output multiplexer circuit. Furthermore, two signals are input: a latch enable pulse (LE) and a chip select (6e) for latching (i) the initial state of the flip-flop, (3i) the feedback state, and (iii) the final stage selection state of the flip-flop. An AND gate (ANDO) and a latch for latching the data in (i) to (iii) (7) above by applying the output of this AND gate (ANDO) to two select signals (SELO~l). It has a demultiplexer circuit for distribution to the circuits.

[Prior Art] As a conventional method, for example, an M-sequence code generator (hereinafter referred to as the present specification) is described in Japanese Patent Application No. 122071/1988 filed by Mizu Applicant on June 5, 1985. In this book, it is abbreviated as code generator).

[Problems to be Solved by the Invention] However, the device described in the above-mentioned patent application does not have a configuration that takes into consideration IC implementation. In other words, when considering the possibility of converting the code generator into 1C, the number of flip-flop stages in the code generator must be limited, and in order to enable long-time code generation even under such conditions, the device must be It is desirable to have a configuration that allows cascade connections between the two.

An object of the present invention is to provide an M
An object of the present invention is to provide a sequence code generator.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a steering gate to which an input signal is gate-controlled by a strobe pulse, and a steering gate connected to the steering gate to gate the input signal at the rising edge of a clock signal. a plurality of circuits connected in series, each consisting of a flip-flop circuit that outputs
an AND gate that outputs a signal that is half-added to the output of the flip-flop; second latch means that is controlled by the strobe pulse and provides control information to one of the AND gate inputs; A multiplexer circuit having a three-state output to which an output is input, and fourth latch means controlled by the strobe pulse and providing selection information for the final stage of the flip-flop to the multiplexer circuit. A sequence code generator comprising the following (i)
~(ni) data (i) Initial state of each flip-flop (ii) Feedback state (■) The final stage selection state of each flip-flop is set to the first . Third. The fifth latch means includes an AND gate which receives two signals, a latch enable pulse for latching and a chip select of the M-sequence code generator, and its A
The output of the ND gate is input, and the output light is controlled by two control signals, and the output of the demultiplexer circuit is controlled by the above (i
) a first latch means that holds the data of (i) and outputs it to one input of each of the steering gates, and a second latch that holds the data of (i) and is controlled by the output of the demultiplexer circuit. a fifth latch means that is controlled by the output of the demultiplexer circuit, holds the data of (i), and outputs the data to the fourth latch means; are the feedback output section of the multiplexer circuit, the other signal input section of each of the AND gates, the signal input section to the other first stage of the steering gate, the AND gate output of the final stage, and the flip-flop output of the final stage. When connected in cascade with the output section of the signal obtained by adding half of
and a sixth latch means for outputting the enable control signal of the multiplexer circuit to the enable input of the multiplexer circuit using the strobe pulse as a trigger. do.

[Operations] An example in which two M-sequence code generators according to the present invention are cascaded is shown in FIG. 5, but any number of them can be similarly cascaded.

[Examples of the Invention] The present invention will be explained in more detail using Examples below with reference to a drawing, but these are merely illustrative and various modifications and improvements can be made without going beyond the scope of the present invention. Of course, this is possible.

FIG. 1 is a block diagram showing the configuration of a code generator according to the present invention. In the figure, G is a steering gate circuit, which can be configured using, for example, a NAND gate as shown in FIG. As shown in FIG. 1, the initial information required for code generation by the code generator includes primary information (i) to (ni).

(i) Initial state of flip-flops SRI to SRn (ii) Feedback state (iii) Final stage selection state of flip-flop In FIG. 1, CLK is a supply clock, STB is a sign switching strobe, and C8 is a chip select.

LE latch enable, DATO-”n
are the data in (i) to (iii) above, and 5ELO to 1 are data selects to select data as shown in Table 1, for example.

FBO~2. CAS is input/output for cascade connection.

FB2 represents a three-state output, and PN represents a code output.

First, the operation when the code generator of the present invention is used alone will be explained.

A connection diagram when Table 1 is used alone is shown in Figure 4. The circuit operation of FIG. 4 will be explained using the timing chart shown in FIG. 3 and the symbols in FIG. 1.

It is now assumed that the code 1 is being output from the code output terminal PN. When the strobe pulse STB is input, the following operation is performed.

(a) The contents of latch 1 are set through steering gate G to the data inputs of flip-flops SRI to SRn. This data is transferred to the flip-flops SRL to SRn by the rising edge (a) of the clock pulse CLK.
appears in the output of

Note that the contents of latch 1 are flip-flops SRI to SR.
This is the initial state of n.

(b) The contents of latch 3 are output from latch 2, and the FBO
The feedback input signal from the AND gate AND1~AN
The exclusive OR gate to which the feedback is fed is controlled through Dn, and the contents of the latch are output from the latch 4, and when the latch 6 enables the multiplexer by inputting the feedback control FBCNT and the strobe pulse STB, Flip-flops SRI to SRn selected corresponding to the output value of latch 4
The output of FB2 is output as a feedback signal.

However, the multiplexer output of latch 6 is “L hp
Enable state when , disable when 7
Set to e state.

Note that the content of latch 3 is a feedback state, and the content of latch 5 is a final stage selection state of flip-flops SRI to SRn.

(c) As a result of (a) and (b), a new code 2 is output from the code output terminal PN by the clock pulse CLK after (a).

That is, the code 1 is switched to the code 2.

(d) On the other hand, the strobe pulse STB is also used as an interrupt pulse to an external control circuit such as a microprocessor, and using this interrupt pulse as a trigger, the external control circuit such as a microprocessor receives the code 3 to be generated next. Make preparations.

That is, ''L11 is input to the chip select signal, and the latch enable pulse LE is input to the AND gate 1.
−, is input to the demultiplexer through ANDO,
The corresponding latches 1, 3, and 5 are sequentially enabled by control signals 5ELO to 5ELO1 of the demultiplexer.

At this time, the data D A T of the above (i) to (m)
O''n is also sequentially latched into latches 1, 3.5, and the preparation for code 3 generation is completed.

Then, when the strobe pulse STB is input again,
The operations (a) to (c) above are repeated, and a new code 3 is output from the code output terminal PN by the tarock pulse CLK from (c) onwards.

Next, the operation when the code generator of the present invention is used in a cascade connection will be explained.

As an example, the operation shown in FIG. 5 in which two code generators are connected in cascade will be described. Second, the correspondence between the terminals a+ b, C+ d, and e in FIG. 4.5 and the signal names in FIG. 1 is shown.

When used in cascade, (d
) The chip select d1 prepares for code generation as described in
This is done for each code generator using

Table 2 Next, using the feedback control FBCNT, enable the multiplexer of the code generator in the final stage of the flip-flop, and input the strobe pulse STB to the two code generators to generate codes. let

However, the multiplexer output is a three-state output. Table 3 shows the correspondence between the feedback control FBCNT and the accessed code generators.

Table 3 Note that it is also possible to use the connection shown in FIG. 5 for three or more code generators, and it is possible to generate codes with a longer period.

As an application, the desired information can be transmitted by outputting the correlation between the M-sequence code from the transmitting side and the M-sequence code generated on the receiving side, and the type and phase of the M-sequence code on both the transmitting side and the receiving side can be determined. There is a spread spectrum communication system that has an M-sequence code generator that can be changed arbitrarily.

[Effects of the Invention] As explained above, it is possible to realize a versatile IC using the 1M sequence code generator of the present invention. Furthermore, since it is possible to connect the M-sequence code generators in cascade, it is possible to generate an M-sequence code with a longer period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a code generation device according to the present invention, FIG. 2 is a diagram showing an example of the configuration of a steering gate circuit, and FIG. 3 is a timing chart for explaining the operation of the device shown in FIG. 1. chart. FIG. 4 is a connection diagram when the device shown in FIG. 1 is used alone, and FIG. 5 is a connection diagram when the device shown in FIG. 1 is used in cascade. Patent Applicant Clarion Co., Ltd. Single Buff-'' Irubaji, 11j Collection Figure 4 Gu 1-' 7:-A Vlroba 7 case sacrilege Σ Figure 5 Procedural Amendment May 2, 1986 Day

Claims (3)

[Claims] (1) (a) first latch means outputting to the steering gate; (b) second and fourth latch means outputting to one input of the flip-flop; (c) connecting the steering gate and the flip-flop together. (d) an AND gate that outputs an addition signal to the output of each of the flip-flops; (e) a multiplexer to which the outputs of each of the flip-flops are input; and (f) a plurality of pairs arranged in cascade as two pairs; (g) an initial state, a feedback state and a final stage selection state of each flip-flop in the first, third and fifth latch means for controlling the multiplexer; a latch enable for latching to the fifth latching means;
an AND gate that receives two signals, a pulse and a chip select of the M-sequence code generator; (h) an output of the AND gate is input, and the first, third, and fifth An M-sequence code generator comprising: a demultiplexer circuit for selectively controlling the latch means by output, and outputting from the third and fifth latch means to the second and fourth latch means. . (2) (a) first latch means outputting to the steering gate; (b) second and fourth latch means outputting to one input of the flip-flop; (c) connecting the steering gate and the flip-flop together. (d) an AND gate that outputs a summation signal to the output of each of the flip-flops; (e) an AND gate into which each of the flip-flop outputs is input and has a three-state output; A multiplexer circuit; and (f) third and fifth latch means for controlling the multiplexer; an input part for a control signal for enabling the output of the multiplexer circuit in the device;
Sixth latch means for outputting to the ble input. (i) the input terminal to each of the AND gates, (j) the input terminal to the first-stage steering gate, and (k) the output of the final-stage AND gate and the output of the final-stage flip-flop. 1. An M-series code generator comprising: a cascade connection output terminal to which a signal is output. (3) (a) first latch means outputting to the steering gate; (b) second and fourth latch means outputting to one input of the flip-flop; (c) connecting the steering gate and the flip-flop together. (d) an AND gate that outputs an addition signal to the output of each of the flip-flops; (e) a multiplexer to which the outputs of each of the flip-flops are input; and (f) a plurality of pairs arranged in cascade as two pairs; (g) an initial state, a feedback state and a final stage selection state of each flip-flop in the first, third and fifth latch means for controlling the multiplexer; a latch enable for latching to the fifth latching means;
an AND gate that receives two signals, a pulse and a chip select of the M-sequence code generator; (h) an output of the AND gate is input, and the first, third, and fifth (i) a cascade of a plurality of M-sequence code generators; (j) an input part for a control signal for enabling the output of the multiplexer circuit in any M-sequence code generator when connected; (j) an enable control signal for the multiplexer circuit as a strobe pulse supplied to the steering gate; ena of the multiplexer circuit above as a trigger
ble input, (k) an input terminal to each AND gate, (l) an input terminal to the first stage steering gate, and (m) a final stage AND gate output and a final stage flip-flop. 1. An M-series code generator comprising: a cascade connection output terminal to which a signal obtained by half-adding the outputs of the M-sequence code generator and the output of the M-sequence code generator.